CS110ComputerArchitectureMIPSInstructionFormats

Instructor:SörenSchwertfeger

http://shtech.org/courses/ca/

School of Information Science and Technology SIST

ShanghaiTech University

1Slides based on UC Berkley's CS61C

LevelsofRepresentation/Interpretation

lw $t0,0($2)lw $t1,4($2)sw $t1,0($2)sw $t0,4($2)

HighLevelLanguageProgram(e.g.,C)

AssemblyLanguageProgram(e.g.,MIPS)

MachineLanguageProgram(MIPS)

HardwareArchitectureDescription(e.g.,blockdiagrams)

Compiler

Assembler

MachineInterpretation

temp=v[k];v[k]=v[k+1];v[k+1]=temp;

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

ArchitectureImplementation

Anythingcanberepresentedasanumber,

i.e.,dataorinstructions

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LogicCircuitDescription(CircuitSchematicDiagrams)

Review:AllocatingSpaceonStack• Chastwostorageclasses:automaticandstatic– Automatic variablesarelocaltofunctionanddiscardedwhenfunctionexits

– Staticvariablesexistacrossexitsfromandentriestoprocedures

• Usestackforautomatic(local)variablesthatdon’tfitinregisters

• Procedureframeor activationrecord:segmentofstackwithsavedregistersandlocalvariables

• SomeMIPScompilersuseaframepointer($fp)topointtofirstwordofframe

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StackBefore,During,AfterCall

4

RecursiveFunctionFactorialint fact (int n)

{

if (n < 1) return (1);

else return (n * fact(n-1));

}

5

RecursiveFunctionFactorialFact:

# adjust stack for 2 itemsaddi $sp,$sp,-8# save return addresssw $ra, 4($sp) # save argument nsw $a0, 0($sp) # test for n < 1slti $t0,$a0,1 # if n >= 1, go to L1beq $t0,$zero,L1# Then part (n==1) return 1addi $v0,$zero,1 # pop 2 items off stackaddi $sp,$sp,8 # return to callerjr $ra

L1: # Else part (n >= 1) # arg. gets (n – 1)addi $a0,$a0,-1 # call fact with (n – 1)jal Fact # return from jal: restore nlw $a0, 0($sp)# restore return addresslw $ra, 4($sp) # adjust sp to pop 2 itemsaddi $sp, $sp,8 # return n * fact (n – 1)mul $v0,$a0,$v0# return to the callerjr $ra

6mul isapseudoinstruction

LevelsofRepresentation/Interpretation

lw $t0,0($2)lw $t1,4($2)sw $t1,0($2)sw $t0,4($2)

HighLevelLanguageProgram(e.g.,C)

AssemblyLanguageProgram(e.g.,MIPS)

MachineLanguageProgram(MIPS)

HardwareArchitectureDescription(e.g.,blockdiagrams)

Compiler

Assembler

MachineInterpretation

temp=v[k];v[k]=v[k+1];v[k+1]=temp;

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

ArchitectureImplementation

Anythingcanberepresentedasanumber,

i.e.,dataorinstructions

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LogicCircuitDescription(CircuitSchematicDiagrams)

ENIAC(U.Penn.,1946)FirstElectronicGeneral-PurposeComputer

8

• Blazinglyfast(multiplyin2.8ms!)– 10decimaldigitsx10decimaldigits

• Butneeded2-3daystosetupnewprogram,asprogrammedwithpatchcordsandswitches

BigIdea:Stored-Program

Computer

– Instructionsarerepresentedasbitpatterns- canthinkoftheseasnumbers

– Therefore,entireprogramscanbestoredinmemorytobereadorwrittenjustlikedata

– Canreprogramquickly(seconds),don’thavetorewirecomputer(days)

– Knownasthe“vonNeumann”computersafterwidelydistributedtechreportonEDVACproject• Wrote-updiscussionsofEckertandMauchly• AnticipatedearlierbyTuringandZuse

FirstDraftofaReportontheEDVACby

JohnvonNeumannContractNo.W–670–ORD–4926

BetweentheUnitedStatesArmyOrdnanceDepartmentandthe

UniversityofPennsylvaniaMooreSchoolofElectricalEngineering

UniversityofPennsylvania

June 30,1945

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Consequence#1:EverythingAddressed

• Sinceallinstructionsanddataarestoredinmemory,everythinghasamemoryaddress:instructions,datawords– bothbranchesandjumpsusethese

• Cpointersarejustmemoryaddresses:theycanpointtoanythinginmemory– Unconstraineduseofaddressescanleadtonastybugs;upto

youinC;limitedinJavabylanguagedesign• Oneregisterkeepsaddressofinstructionbeingexecuted:

“ProgramCounter”(PC)– Basicallyapointertomemory:IntelcallsitInstructionPointer(a

bettername)

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Consequence#2:BinaryCompatibility

• Programsaredistributedinbinaryform– Programsboundtospecificinstructionset– DifferentversionforMacintoshesandPCs

• Newmachineswanttorunoldprograms(“binaries”)aswellasprogramscompiledtonewinstructions

• Leadsto“backward-compatible”instructionsetevolvingovertime

• SelectionofIntel8086in1981for1st IBMPCismajorreasonlatestPCsstilluse80x86instructionset;couldstillrunprogramfrom1981PCtoday

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InstructionsasNumbers(1/2)

• Currentlyalldataweworkwithisinwords(32-bitchunks):– Eachregisterisaword.– lw andsw bothaccessmemoryonewordatatime.

• Sohowdowerepresentinstructions?– Remember:Computeronlyunderstands1sand0s,so“add $t0,$0,$0”ismeaningless.

– MIPS/RISCseekssimplicity:sincedataisinwords,makeinstructionsbefixed-size32-bitwordsalso

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InstructionsasNumbers(2/2)

• Onewordis32bits,sodivideinstructionwordinto“fields”.

• Eachfieldtellsprocessorsomethingaboutinstruction.

• Wecoulddefinedifferentfieldsforeachinstruction,butMIPSseekssimplicity,sodefine3basictypesofinstructionformats:– R-format– I-format– J-format

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InstructionFormats

• I-format:usedforinstructionswithimmediates,lw andsw (sinceoffsetcountsasanimmediate),andbranches(beq andbne)– (butnottheshiftinstructions;later)

• J-format:usedforj andjal• R-format:usedforallotherinstructions• Itwillsoonbecomeclearwhytheinstructionshavebeenpartitionedinthisway

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R-FormatInstructions(1/5)

• Define“fields”ofthefollowingnumberofbitseach:6+5+5+5+5+6=32

• Forsimplicity,eachfieldhasaname:

• Important:Ontheseslidesandinbook,eachfieldisviewedasa5- or6-bitunsignedinteger,notaspartofa32-bitinteger– Consequence:5-bitfieldscanrepresentanynumber0-31,while

6-bitfieldscanrepresentanynumber0-63

6 5 5 5 65

opcode rs rt rd functshamt

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R-FormatInstructions(2/5)

• Whatdothesefieldintegervaluestellus?– opcode:partiallyspecifieswhatinstructionitis• Note:Thisnumberisequalto0 forallR-Formatinstructions

– funct:combinedwithopcode,thisnumberexactlyspecifiestheinstruction

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• Question:Whyaren’topcode andfunct asingle12-bitfield?–We’llanswerthislater

R-FormatInstructions(3/5)

• Morefields:– rs (SourceRegister):usually usedtospecifyregistercontainingfirstoperand

– rt (TargetRegister):usually usedtospecifyregistercontainingsecondoperand(notethatnameismisleading)

– rd (DestinationRegister):usually usedtospecifyregisterwhichwillreceiveresultofcomputation

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R-FormatInstructions(4/5)

• Notesaboutregisterfields:– Eachregisterfieldisexactly5bits,whichmeansthatitcanspecifyanyunsignedintegerintherange0-31.Eachofthesefieldsspecifiesoneofthe32registersbynumber.

– Theword“usually”wasusedbecausethereareexceptionsthatwe’llseelater

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R-FormatInstructions(5/5)• Finalfield:– shamt:Thisfieldcontainstheamountashiftinstructionwillshiftby.Shiftinga32-bitwordbymorethan31isuseless,sothisfieldisonly5bits(soitcanrepresentthenumbers0-31)

– Thisfieldissetto0 inallbuttheshiftinstructions

• Foradetaileddescriptionoffieldusageforeachinstruction,seegreeninsertinCOD(Youcanbringwithyoutoallexams)

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R-FormatExample(1/2)• MIPSInstruction:

add $8,$9,$10

opcode =0(lookupintableinbook)funct =32(lookupintableinbook)rd =8(destination)rs =9(firstoperand)rt =10(secondoperand)shamt =0(notashift)

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R-FormatExample(2/2)• MIPSInstruction:

add $8,$9,$10Decimalnumberperfieldrepresentation:

Binarynumberperfieldrepresentation:

hexrepresentation: 012A 4020hex

CalledaMachineLanguageInstruction

0 9 10 8 320

000000 01001 01010 01000 10000000000hex

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opcode rs rt rd functshamt

= 19,546,144ten

I-FormatInstructions(1/4)

• Whataboutinstructionswithimmediates?– 5-bitfieldonlyrepresentsnumbersuptothevalue31:immediatesmaybemuchlargerthanthis

– Ideally,MIPSwouldhaveonlyoneinstructionformat(forsimplicity):unfortunately,weneedtocompromise

• DefinenewinstructionformatthatispartiallyconsistentwithR-format:– Firstnoticethat,ifinstructionhasimmediate,thenitusesatmost2registers.

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I-FormatInstructions(2/4)• Define“fields”ofthefollowingnumberofbitseach:6+5+5+16=32bits

– Again,eachfieldhasaname:

– KeyConcept:OnlyonefieldisinconsistentwithR-format.Mostimportantly,opcode isstillinsamelocation.

6 5 5 16

opcode rs rt immediate

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I-FormatInstructions(3/4)• Whatdothesefieldsmean?– opcode:sameasbeforeexceptthat,sincethere’snofunct field,opcode uniquelyspecifiesaninstructioninI-format

– ThisalsoanswersquestionofwhyR-formathastwo6-bitfieldstoidentifyinstructioninsteadofasingle12-bitfield:inordertobeconsistentaspossiblewithotherformatswhileleavingasmuchspaceaspossibleforimmediatefield.

– rs:specifiesaregisteroperand(ifthereisone)– rt:specifiesregisterwhichwillreceiveresultofcomputation(thisiswhyit’scalledthetarget register“rt”)orotheroperandforsomeinstructions.

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I-FormatInstructions(4/4)• TheImmediateField:– addi,slti,sltiu,theimmediateissign-extended to32bits.Thus,it’streatedasasignedinteger.

– 16bitsè canbeusedtorepresentimmediateupto216 differentvalues

– Thisislargeenoughtohandletheoffsetinatypicallw orsw,plusavastmajorityofvaluesthatwillbeusedintheslti instruction.

– Later,we’llseewhattodowhenavalueistoobigfor16bits

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I-FormatExample(1/2)• MIPSInstruction:

addi $21,$22,-50

opcode =8(lookupintableinbook)rs =22(registercontainingoperand)rt =21(targetregister)immediate =-50(bydefault,thisisdecimalinassemblycode)

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I-FormatExample(2/2)• MIPSInstruction:

addi $21,$22,-50

8 22 21 -50

001000 10110 10101 1111111111001110

Decimal/field representation:

Binary/field representation:

hexadecimal representation: 22D5 FFCEhex

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QuestionWhichinstructionhassamerepresentationasinteger35ten?

a) add$0,$0,$0b) subu $s0,$s0,$s0c) lw $0,0($0)d) addi $0,$0,35e) subu $0,$0,$0

Registersnumbersandnames:0:$0,..8:$t0,9:$t1,..15:$t7,16:$s0,17:$s1,..23:$s7

Opcodesandfunctionfields:add:opcode =0,funct =32subu:opcode =0,funct =35addi:opcode =8lw:opcode =35

opcode rs rt offset

rd functshamtopcode rs rt

opcode rs rt immediate

rd functshamtopcode rs rt

rd functshamtopcode rs rt

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DealingWithLargeImmediates

• Howdowedealwith32-bitimmediates?– Sometimeswanttouseimmediates >± 215 withaddi,lw,sw andslti

– Bitwiselogicoperationswith32-bitimmediates

• Solution:Don’tmesswithinstructionformats,justaddanewinstruction

• LoadUpperImmediate (lui)– lui reg,imm–Moves16-bitimm intoupperhalf(bits16-31)ofreg andzerosthelowerhalf(bits0-15)

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lui Example

• Want:addiu $t0,$t0,0xABABCDCD– Thisisapseudo-instruction!

• Translatesinto:lui $at,0xABAB # upper 16ori $at,$at,0xCDCD # lower 16addu $t0,$t0,$at # move

• Nowwecanhandleeverythingwitha16-bitimmediate!

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Onlytheassemblergetstouse$at($1)

BranchingInstructions

• beq andbne– Needtospecifyatargetaddressifbranchtaken– Alsospecifytworegisterstocompare

• UseI-Format:

– opcode specifiesbeq (4)vs.bne (5)– rs andrt specifyregisters– Howtobestuseimmediate tospecifyaddresses?

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opcode rs rt immediate31 0

BranchingInstructionUsage

• Branchestypicallyusedforloops(if-else,while,for)– Loopsaregenerallysmall(<50instructions)– Functioncallsandunconditionaljumpshandledwithjumpinstructions(J-Format)

• Recall: Instructionsstoredinalocalizedareaofmemory(Code/Text)– Largestbranchdistancelimitedbysizeofcode– Addressofcurrentinstructionstoredintheprogramcounter(PC)

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PC-RelativeAddressing

• PC-RelativeAddressing: Usetheimmediatefieldasatwo’scomplementoffsettoPC– BranchesgenerallychangethePCbyasmallamount

– Canspecify± 215 addressesfromthePC

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BranchCalculation

• Ifwedon’t takethebranch:– PC = PC + 4 = nextinstruction

• Ifwedo takethebranch:– PC = (PC+4) + (immediate*4)

• Observations:– immediate isnumberofinstructionstojump(remember,specifieswords)eitherforward(+)orbackwards(–)

– BranchfromPC+4 forhardwarereasons;willbeclearwhylaterinthecourse

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BranchExample(1/2)

• MIPSCode:Loop: beq $9,$0,End

addu $8,$8,$10addiu $9,$9,-1j Loop

End:

• I-Formatfields:opcode =4 (lookuponGreenSheet)rs =9 (firstoperand)rt =0 (secondoperand)immediate =???

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StartcountingfrominstructionAFTERthebranch

123

3

BranchExample(2/2)

• MIPSCode:Loop: beq $9,$0,End

addu $8,$8,$10addiu $9,$9,-1j Loop

End:

Fieldrepresentation(decimal):

Fieldrepresentation(binary):

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4 9 0 331 0

000100 01001 00000 000000000000001131 0

QuestionsonPC-addressing

• Doesthevalueinbranchimmediatefieldchangeifwemovethecode?– Ifmovingindividuallinesofcode,thenyes– Ifmovingallofcode,thenno

• Whatdowedoifdestinationis>215instructionsawayfrombranch?– Otherinstructionssaveus– beq $s0,$0,far bne $s0,$0,next# next instr à j far

next: # next instr37

J-FormatInstructions(1/4)

• Forbranches,weassumedthatwewon’twanttobranchtoofar,sowecanspecifyachangeinthePC

• Forgeneraljumps(j andjal),wemayjumptoanywhere inmemory– Ideally,wewouldspecifya32-bitmemoryaddresstojumpto

– Unfortunately,wecan’tfitbotha6-bitopcodeanda32-bitaddressintoasingle32-bitword

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J-FormatInstructions(2/4)

• Definetwo“fields”ofthesebitwidths:

• Asusual,eachfieldhasaname:

• KeyConcepts:– Keepopcode fieldidenticaltoR-FormatandI-Formatforconsistency

– Collapseallotherfieldstomakeroomforlargetargetaddress 39

6 2631 0

opcode target address31 0

J-FormatInstructions(3/4)

• Wecanspecify226 addresses– Stillgoingtoword-alignedinstructions,soadd00 aslasttwobits(multiplyby4)

– Thisbringsusto28bitsofa32-bitaddress

• Takethe4highestorderbitsfromthePC– Cannotreacheverywhere,butadequatealmostallofthetime,sinceprogramsaren’tthatlong

– Onlyproblematicifcodestraddlesa256MBboundary• Ifnecessary,use2jumpsorjr (R-Format)instead

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J-FormatInstructions(4/4)

• Jumpinstruction:– NewPC={ (PC+4)[31..28],targetaddress,00}

• Notes:– {,,}meansconcatenation{4bits,26bits,2bits}=32bitaddress• Bookuses||instead

– Arrayindexing:[31..28]meanshighest4bits– Forhardwarereasons,usePC+4insteadofPC

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AssemblerPseudo-Instructions• CertainCstatementsareimplementedunintuitivelyinMIPS– e.g.assignment(a=b)viaadd$zero

• MIPShasasetof“pseudo-instructions”tomakeprogrammingeasier– Moreintuitivetoread,butgettranslatedintoactualinstructionslater

• Example:move dst,src

translatedintoaddi dst,src,0

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AssemblerPseudo-Instructions

• Listofpseudo-instructions:http://en.wikipedia.org/wiki/MIPS_architecture#Pseudo_instructions

– Listalsoincludesinstructiontranslation• LoadAddress(la)– la dst,label– Loadsaddressofspecifiedlabelintodst

• LoadImmediate (li)– li dst,imm– Loads32-bitimmediateintodst

• MARShasadditionalpseudo-instructions– SeeHelp(F1)forfulllist

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AssemblerRegister

• Problem:–Whenbreakingupapseudo-instruction,theassemblermayneedtouseanextraregister

– Ifitusesaregularregister,it’lloverwritewhatevertheprogramhasputintoit

• Solution:– Reservearegister($1 or$at for“assemblertemporary”)thatassemblerwillusetobreakuppseudo-instructions

– Sincetheassemblermayusethisatanytime,it’snotsafetocodewithit

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MultiplyandDivide• Examplepseudo-instruction:

mul $rd,$rs,$rt– Consistsofmult whichstorestheoutputinspecialhiandloregisters,andamovefromtheseregistersto$rd

mult $rs,$rtmflo $rd

• mult anddiv havenothingimportantintherd fieldsincethedestinationregistersarehi andlo

• mfhi andmflo havenothingimportantinthers andrt fieldssincethesourceisdeterminedbytheinstruction(seeCOD)

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IntegerMultiplication(1/3)

• Paperandpencilexample(unsigned):Multiplicand 1000 8 Multiplier x1001 9

10000000

0000+100001001000

• m bitsx n bits=m +n bitproduct

IntegerMultiplication(2/3)

• InMIPS,wemultiplyregisters,so:– 32-bitvaluex 32-bitvalue=64-bitvalue

• SyntaxofMultiplication(signed):– mult register1,register2–Multiplies32-bitvaluesinthoseregisters&puts64-bitproductinspecialresultregs:• putsproductupperhalfinhi,lowerhalfin lo

– hi andlo are2registersseparatefromthe32generalpurposeregisters

– Usemfhi register&mflo register tomovefromhi,lo toanotherregister

IntegerMultiplication(3/3)• Example:– inC: a = b * c;– inMIPS:

• letb be$s2;letc be$s3;andleta be$s0 and$s1 (sinceitmaybeupto64bits)

mult $s2,$s3 # b*cmfhi $s0 # upper half of

# product into $s0mflo $s1 # lower half of

# product into $s1•Note:Often,weonlycareaboutthelowerhalfoftheproduct.•Pseudo-inst.mul expandstomult/mflo.

IntegerDivision(1/2)

• Paperandpencilexample(unsigned):1001 Quotient Divisor

1000|1001010 Dividend-1000

101011010

-100010 Remainder

(or Modulo result)• Dividend=Quotientx Divisor+Remainder

• SyntaxofDivision(signed):– div register1,register2

– Divides32-bitregister1by32-bitregister2:

– putsremainderofdivisioninhi,quotientinlo

• ImplementsCdivision(/)andmodulo(%)

• ExampleinC: a = c / d; b = c % d;

• inMIPS:a«$s0;b«$s1;c«$s2;d«$s3

div $s2,$s3 # lo=c/d, hi=c%dmflo $s0 # get quotientmfhi $s1 # get remainder

IntegerDivision(2/2)

MALvs.TAL

• TrueAssemblyLanguage(TAL)– Theinstructionsacomputerunderstandsandexecutes

• MIPSAssemblyLanguage(MAL)– Instructionstheassemblyprogrammercanuse(includespseudo-instructions)

– EachMALinstructionbecomes1ormoreTALinstruction

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Question

WhichofthefollowingplacetheaddressofLOOPin$v0?1) la $t1, LOOP

lw $v0, 0($t1)

2) jal LOOPLOOP: addu $v0, $ra, $zero

3) la $v0, LOOP

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1 2 3A)T, T, TB)T, T, FC)F, T, TD)F, T, FE)F, F, T

Summary• I-Format: instructionswithimmediates,lw/sw (offsetisimmediate),andbeq/bne– Butnottheshiftinstructions– BranchesusePC-relativeaddressing

• J-Format: j andjal (butnotjr)– Jumpsuseabsoluteaddressing

• R-Format: allotherinstructions

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opcode rs rt immediateI:

opcode target addressJ:

opcode functrs rt rd shamtR: