Embed Size (px)
Citation preview
CADSL
CS-683: Advanced Computer Architecture
Course Introduction
Virendra Singh Associate Professor
Computer Architecture and Dependable Systems Lab Department of Electrical Engineering
Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/
E-mail: [email protected]
Lecture 0
CADSL
Computer Architecture’s Changing Definition
• 1950s to 1960s: Computer Architecture Course = Computer Arithme7c
• 1970s to mid 1980s: Computer Architecture Course = Instruc7on Set Design, especially ISA appropriate for compilers
• 1990s onwards: Computer Architecture Course = Design of CPU (Processor Microarchitecture), memory system, I/O system, Mul7processors
20 Jul 2013 CS-683@IITB 2
CADSL
Instruction Set Architecture (ISA)
instruc7on set
SoMware
Hardware
20 Jul 2013 CS-683@IITB 3
CADSL
Running Program on Processor
Processor Performance = -‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐ Time
Program
Architecture
Compiler Designer
Instructions Time
Program Instruction
(code size)
= X
CS-‐683@IITB 20 Jul 2013 4
CADSL
Computer Architecture
• Instruc7on Set Architecture (IBM 360) – … the a'ributes of a [compu3ng] system as seen by the programmer. I.e. the conceptual structure and func3onal behavior, as dis3nct from the organiza3on of the data flows and controls, the logic design, and the physical implementa3on. -‐-‐ Amdahl, Blaaw, & Brooks, 1964
20 Jul 2013 CS-683@IITB 5
CADSL
Running Program on Processor
Processor Performance = -‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐ Time
Program
Architecture -‐-‐> Implementa;on
Compiler Designer Processor Designer
Instructions Cycles
Program Instruction Time
Cycle
(code size)
= X X
(CPI)
CS-‐683@IITB 20 Jul 2013 6
CADSL
Running Program on Processor
Processor Performance = -‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐ Time
Program
Architecture -‐-‐> Implementa;on -‐-‐> Realiza;on
Compiler Designer Processor Designer Chip Designer
Instructions Cycles
Program Instruction Time
Cycle
(code size)
= X X
(CPI) (cycle time)
CS-‐683@IITB 20 Jul 2013 7
CADSL
Iron Law • Instruc7ons/Program
Ø Instruc7ons executed, not sta7c code size Ø Determined by algorithm, compiler, ISA
• Cycles/Instruc7on Ø Determined by ISA and CPU organiza7on Ø Overlap among instruc7ons reduces this term
• Time/cycle Ø Determined by technology, organiza7on, clever circuit design
20 Jul 2013 CS-683@IITB 8
CADSL
Computer Architecture
• Exercise in engineering tradeoff analysis – Find the fastest/cheapest/power-‐efficient/etc. solu7on – Op7miza7on problem with 100s of variables
• All the variables are changing – At non-‐uniform rates – With inflec7on points
• Two high-‐level effects: – Technology push – Applica7on Pull
20 Jul 2013 CS-683@IITB 9
CADSL 10
Microprocessor Designs
20 Jul 2013 CS-683@IITB
CADSL
Trends
• Moore’s Law for device integra7on • Chip power consump7on • Single-‐thread performance trend
[source: Intel] 20 Jul 2013 11 CS-683@IITB
CADSL CS-683@IITB
Single Processor Performance
RISC
Move to multi-processor
ILP Exploita7on
CADSL CS-683@IITB
Frequency Scaling
20 Jul 2013 13
CADSL CS-683@IITB
Memory Performance Gap
20 Jul 2013 14
CADSL
Express way
20 Jul 2013 CS-683@IITB 15
CADSL 16
Course Outline v Review: CISC vs. RISC, and Pipelining
v Superscalar Design
v VLIW, Mul7-‐scalar Architectures
v Simultaneous Mul7-‐threaded (SMT) Architecture
v Mul7-‐core Architecture
v Performance Evalua7on
v Memory System Design
20 Jul 2013 CS-683@IITB
CADSL 17
Course Schedule
Class Hours
v Wednesday: 9:30 am to 11:00 am
v Friday: 9:30 am to 11:30 am
Office Hours:
20 Jul 2013 CS-683@IITB
CADSL 18
Course Evaluation v Mid Term Exam (15%)
Ø Open Book/Notes Exam v Final Exam (30%)
Ø Open Book/Notes Exam v Assignments (15%)
Ø Set of assignments will be given periodically v Course Projects (20%)
Ø 1 projects Ø Group ( Max size 3 )
v Con7nuous Evalua7ons (15%) – weekly quiz Ø Weekly Quiz – Open Book (80% best will be counted)
Ø Presenta7on and Viva (5%) Ø [BONUS] Research Project (15%) Ø Satura7ng counter sums to 100
20 Jul 2013 CS-683@IITB
CADSL
Books • Computer Architecture: A quan7ta7ve approach
Ø Hennessy and Pamerson Ø Morgan Kaufman, 5e, 2012
• Modern Processor Design Ø Shen and Lipas7 Ø Mc Graw Hill, 2005
• Current Literature (ISCA/Micro/HPCA/ICCD/DSN)
20 Jul 2013 CS-683@IITB 19
CADSL
Acknowledgement • Prof. Mikko Lipas7, Univ. of Wisconsin • Prof. Kewal Saluja, Univ. of Wisconsin • Prof. Adit Singh, Auburn Univ. • Prof. Mamhew Jacob, IISc • Prof. Arun Somani, Iowa State Univ.
20 Jul 2013 CS-683@IITB 20
CADSL
Thank You
20 Jul 2013 CS-683@IITB 21
