CS152 Final Project Verilog Supplement

Ted HongChuan Jiang

Jin LuoJeff Min

May 17, 2004

Contents

A Select Project Verilog Code 1A.1 FPGA TOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A.2 Processor Datapath . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18A.3 Reg File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25A.4 ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26A.5 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27A.6 Branch Predictor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31A.7 Forwarding Module and Hazard Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34A.8 Stalling Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36A.9 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37A.10 Instruction Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50A.11 SDRAM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

A Select Project Verilog Code

A.1 FPGA TOP

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// FPGA TOP. v// Top l e v e l i n t e r f a c e from a Xi l inx V2000−E FG680 FPGA// to U.C. Berke ley CalLinx board .//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−‘ include ”C:\Program F i l e s \ s y n p l i c i t y \ Synp l i f y 734 \ l i b \ x i l i n x \ v i r t e x e . v”//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Module : FPGA TOP// Desc : This i s the root module on the VirtexE XCV2000E chip on// the CalLinx board . This i n c l ude s a l l o f the pin// assignments and I /O.//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−module FPGA TOP(

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Clock Inputs//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−Y5 CLK, // IN(1 b ) , 27MHz Video Crys ta lY4 CLK, // IN(1 b ) , Crys ta l at lower l e f tY3 CLK, // IN(1 b ) , Crys ta l at top r i g h tJ18 CLK , // IN(1 b ) , SMA Connector at lower r i g h t//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// RJ45 LEDs [ Bank 2 Le f t Top ]//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−RJ45 TRC , // OUT(2 b ) , LEDs on the Top RightRJ45 BRC , // OUT(2 b ) , LEDs on the Bottom RightRJ45 TLC , // OUT(2 b ) , LEDs on the Top Le f tRJ45 BLC , // OUT(2 b ) , LEDs on the Bottom Le f t//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Ethernet Phys ica l Layer [ Bank 0 ,1 Top ]//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// These s i g n a l s prov ide a s e r i a l readout o f the Ethernet// ch ips LED outputs . The chip w i l l d r i v e the PHY LEDENA// output h igh and then c l o c k out 24 b i t s o f LED s t a t u s// data , d r i v i n g both PHY LEDDAT and PHY LEDCLKPHY LEDCLK, // IN(1 b ) , ClockPHY LEDDAT, // IN(1 b ) , DataPHY LEDENA, // IN(1 b ) , Enable

PHY ADD, // OUT(3 b ) , Address s e t ( 0 f o r CalLinx )

1

PHY MDIO, // INOUT(1 b ) , MII Data BusPHY MDINT , // IN(1 b ) , MII Control In t e r rup tPHY MDC, // OUT(1 b ) , MII ClockPHY MDDIS, // OUT(1 b ) , MII Disab l e

PHYPWRDN, // OUT(1 b ) , Powerdown ControlPHY RESET, // OUT(1 b ) , Act ive Low ResetPHY FDE, // OUT(1 b )PHY AUTOENA, // OUT(1 b )PHY BYPSCR, // OUT(1 b )PHY CFG, // OUT(3 b ) , Phy Chip con f i g l i n e s

PHY LED0 , // IN(3 b ) , LEDs fo r por t 0PHY LED1 , // IN(3 b ) , LEDs fo r por t 1PHY LED2 , // IN(3 b ) , LEDs fo r por t 2PHY LED3 , // IN(3 b ) , LEDs fo r por t 3PHY RXD0, // IN(4 b ) , Receive Data port 0PHY RXD1, // IN(4 b ) , Receive Data port 1PHY RXD2, // IN(4 b ) , Receive Data port 2PHY RXD3, // IN(4 b ) , Receive Data port 3PHY RX DV, // IN(4 b ) , Receive Data Valid [ Port ]PHY RX CLK, // IN(4 b ) , Receive Data Clock [ Port ]PHY RX ER, // IN(4 b ) , Receive Error [ Port ]PHY TX ER, // OUT(4 b ) , Transmit Error [ Port ]PHY TX CLK, // IN(4 b ) , Transmit Data Clock [ Port ]PHY TX EN, // OUT(4 b ) , Transmit Data Clock [ Port ]PHY TXD0, // OUT(4 b ) , Transmit Data por t 0PHY TXD1, // OUT(4 b ) , Transmit Data por t 1PHY TXD2, // OUT(4 b ) , Transmit Data por t 2PHY TXD3, // OUT(4 b ) , Transmit Data por t 4PHY COL, // IN(4 b ) , Co l l i s i o n DetectPHY CRS, // IN(4 b ) , Carrier SensePHY TRSTE, // OUT(4 b ) , Tr i s t a t e Control [ Port ]//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Audio Codec [ Bank 1 Top−Le f t ]//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−AP SDATA OUT,AP BIT CLOCK,AP SDATA IN,AP SYNC,AP RESET ,AP PC BEEP,AA MUTE, // Audio Amp Mute//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// SDRAM [ Bank 7 Top−Right ]//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−RAM1 DQ, // INOUT(32 b ) , Data BusRAM1 CLK, // OUT(1 b ) , ClockRAM1 CLKE, // OUT(1 b ) , Clock EnableRAM1 DQMH,RAM1 DQML,// These s i g n a l s are used to s p e c i f y the SDRAM commandRAM1 CS , // OUT(1 b ) , Chip S e l e c tRAM1 RAS , // OUT(1 b ) , Row Address S e l e c tRAM1 CAS , // OUT(1 b ) , Column Address S e l e c tRAM1 WE , // OUT(1 b ) , Write EnableRAM1 BA, // OUT(2 b ) , Bank AddressRAM1 A, // OUT(12 b ) , Address

RAM2 DQ, // INOUT(32 b ) , Data BusRAM2 CLK, // OUT(1 b ) , ClockRAM2 CLKE, // OUT(1 b ) , Clock EnableRAM2 DQMH,

2

RAM2 DQML,// These s i g n a l s are used to s p e c i f y the SDRAM commandRAM2 CS , // OUT(1 b ) , Chip S e l e c tRAM2 RAS , // OUT(1 b ) , Row Address S e l e c tRAM2 CAS , // OUT(1 b ) , Column Address S e l e c tRAM2 WE , // OUT(1 b ) , Write EnableRAM2 BA, // OUT(2 b ) , Bank AddressRAM2 A, // OUT(12 b ) , Address//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Buttons and DIPSwitches [ Bank 7 ,6 Right ]//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−SW9 , // IN(8 b ) , Act ive Low DIP Switch #9SW10 , // IN(8 b ) , Act ive Low DIP Switch #10SW , // IN(8 b ) , Act ive Low Push Buttons//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// System ACE Chip [ Bank 2 Left−Top ]//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−ACE MPBRDY,ACE MPIRQ,ACE MPCE B,ACE MPWE B,ACE MPOE B,ACE MPA, // (7 b )ACE MPD, // (16 b )//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Video Encoder [ Bank 3 Left−Bottom ]//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−VE P, // (10 b )VE SCLK,VE SDA,VE PAL NTSC,VE RESET B ,VE HSYNC B ,VE VSYNC B ,VE BLANK B ,VE SCRESET,VE CLKIN,//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Video Decoder [ Bank 3 Left−Bottom ]//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−VD LLC, // (2 b )VD P, // (10 b )VD SCLK,VD SDA,VD ISO ,VD RESET B ,VD XTAL,

VD AEF,VD AFF,VD CLKIN,VD DV,VD HFF,VD RD,//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// USB In t e r f a c e//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−USB MODE,

3

USB SPEED,USB SUSPEND,

USB RCV,USB VM,USB VP,

USB OE ,USB VMO FSEO,USB VPO,//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// General Purpose LEDs//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−LED , // OUT(8 b ) , Act ive LOW//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// 7 Segment LEDs x8 [ Bank 4 ,5 Bottom ]//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−SEG1, // OUT(7 b ) , Act ive High (MSb i s Seg ’ a ’ )SEG2, // OUT(7 b ) , Act ive High (MSb i s Seg ’ a ’ )SEG3, // OUT(7 b ) , Act ive High (MSb i s Seg ’ a ’ )SEG4, // OUT(7 b ) , Act ive High (MSb i s Seg ’ a ’ )SEG5, // OUT(7 b ) , Act ive High (MSb i s Seg ’ a ’ )SEG6, // OUT(7 b ) , Act ive High (MSb i s Seg ’ a ’ )SEG7, // OUT(7 b ) , Act ive High (MSb i s Seg ’ a ’ )SEG8, // OUT(7 b ) , Act ive High (MSb i s Seg ’ a ’ )SEG POINT, // OUT(8 b ) , Act ive High (MSb i s SEG8 )SEG COM , // OUT(8 b ) , Act ive Low (MSb i s SEG8 )//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Test−Point Headers Around FPGA//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−PINOUT TOP,PINOUT LEFT CLOSE,PINOUT LEFT FAR,PINOUT BOTTOM CLOSE,PINOUT BOTTOM FAR,PINOUT RIGHT//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

) ; /∗ s yn t h e s i s syn noprune=1 ∗/

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Clock Inputs//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−input Y5 CLK; /∗ s yn t h e s i s x c l o c = ”A20”∗/input Y4 CLK; /∗ s yn t h e s i s x c l o c = ”AU22”∗/input Y3 CLK; /∗ s yn t h e s i s x c l o c = ”D21”∗/input J18 CLK ; /∗ s yn t h e s i s x c l o c = ”AW19”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// RJ45 LEDs//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−output [ 2 : 1 ] RJ45 TRC ; /∗ s yn t h e s i s x c l o c = ”E1 ,D3”∗/output [ 2 : 1 ] RJ45 BRC ; /∗ s yn t h e s i s x c l o c = ”F1 ,E2”∗/output [ 2 : 1 ] RJ45 TLC ; /∗ s yn t h e s i s x c l o c = ”F3 ,F2”∗/output [ 2 : 1 ] RJ45 BLC ; /∗ s yn t h e s i s x c l o c = ”G1,F4”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Ethernet Phys ica l Layer//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−input PHY LEDCLK; /∗ s yn t h e s i s x c l o c = ”D14”∗/input PHY LEDDAT; /∗ s yn t h e s i s x c l o c = ”A15”∗/

4

input PHY LEDENA; /∗ s yn t h e s i s x c l o c = ”B15”∗/

output [ 4 : 2 ] PHY ADD; /∗ s yn t h e s i s x c l o c = ”A16 ,D15 ,C15”∗/

inout PHY MDIO; /∗ s yn t h e s i s x c l o c = ”B32”∗/input PHY MDINT ; /∗ s yn t h e s i s x c l o c = ”A32”∗/output PHY MDC; /∗ s yn t h e s i s x c l o c = ”D33”∗/output PHY MDDIS; /∗ s yn t h e s i s x c l o c = ”C33”∗/

output PHYPWRDN; /∗ s yn t h e s i s x c l o c = ”B33”∗/output PHY RESET; /∗ s yn t h e s i s x c l o c = ”A34”∗/output PHY FDE; /∗ s yn t h e s i s x c l o c = ”D35”∗/output PHY AUTOENA; /∗ s yn t h e s i s x c l o c = ”C35”∗/output PHY BYPSCR; /∗ s yn t h e s i s x c l o c = ”B35”∗/output [ 2 : 0 ] PHY CFG; /∗ s yn t h e s i s x c l o c = ”A35 ,B36 ,A36”∗/

input [ 2 : 0 ] PHY LED0 ; /∗ s yn t h e s i s x c pu l l u p = 1 x c l o c = ”C14 ,B14 ,A14”∗/

input [ 2 : 0 ] PHY LED1 ; /∗ s yn t h e s i s x c pu l l u p = 1 x c l o c = ”D13 ,C13 ,B13”∗/

input [ 2 : 0 ] PHY LED2 ; /∗ s yn t h e s i s x c pu l l u p = 1 x c l o c = ”A13 ,C12 ,B12”∗/

input [ 2 : 0 ] PHY LED3 ; /∗ s yn t h e s i s x c pu l l u p = 1 x c l o c = ”A12 ,D11 ,C11”∗/

input [ 3 : 0 ] PHY RXD0; /∗ s yn t h e s i s x c l o c = ”B16 ,C16 ,D16 ,A17”∗/input [ 3 : 0 ] PHY RXD1; /∗ s yn t h e s i s x c l o c = ”D19 ,C21 ,B20 ,B21”∗/input [ 3 : 0 ] PHY RXD2; /∗ s yn t h e s i s x c l o c = ”C24 ,B24 ,A24 ,D25”∗/input [ 3 : 0 ] PHY RXD3; /∗ s yn t h e s i s x c l o c = ”B28 ,A28 ,D29 ,C29”∗/input [ 3 : 0 ] PHY RX DV; /∗ s yn t h e s i s x c l o c = ”B29 ,C25 ,A21 ,B17”∗/input [ 3 : 0 ] PHY RX CLK; /∗ s yn t h e s i s syn noc lockbu f = 1 x c l o c = ”A29

,B25 ,E22 ,C17”∗/input [ 3 : 0 ] PHY RX ER; /∗ s yn t h e s i s x c l o c = ”D30 ,A25 ,D22 ,D17”∗/output [ 3 : 0 ] PHY TX ER; /∗ s yn t h e s i s x c l o c = ”C30 ,D26 ,C22 ,E17”∗/input [ 3 : 0 ] PHY TX CLK; /∗ s yn t h e s i s syn noc lockbu f = 1 x c l o c = ”B30

,C26 ,B22 ,A18”∗/output [ 3 : 0 ] PHY TX EN; /∗ s yn t h e s i s x c l o c = ”A30 ,B26 ,A22 ,B18”∗/output [ 3 : 0 ] PHY TXD0; /∗ s yn t h e s i s x c l o c = ”A19 ,E18 ,D18 ,C18”∗/output [ 3 : 0 ] PHY TXD1; /∗ s yn t h e s i s x c l o c = ”B23 ,C23 ,D23 ,E23”∗/output [ 3 : 0 ] PHY TXD2; /∗ s yn t h e s i s x c l o c = ”A26 ,D27 ,C27 ,B27”∗/output [ 3 : 0 ] PHY TXD3; /∗ s yn t h e s i s x c l o c = ”A31 ,B31 ,C31 ,D31”∗/input [ 3 : 0 ] PHY COL; /∗ s yn t h e s i s x c l o c = ”D32 ,A27 ,A23 ,B19”∗/input [ 3 : 0 ] PHY CRS; /∗ s yn t h e s i s x c l o c = ”C32 ,C28 ,D24 ,C19”∗/output [ 3 : 0 ] PHY TRSTE; /∗ s yn t h e s i s x c l o c = ”A33 ,D34 ,C34 ,B34”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Audio Codec//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−output AP SDATA OUT; /∗ s yn t h e s i s x c l o c = ”A4”∗/input AP BIT CLOCK; /∗ s yn t h e s i s x c l o c = ”A5”∗/input AP SDATA IN ; /∗ s yn t h e s i s x c l o c = ”B5”∗/output AP SYNC; /∗ s yn t h e s i s x c l o c = ”C5”∗/output AP RESET ; /∗ s yn t h e s i s x c l o c = ”A6”∗/output AP PC BEEP; /∗ s yn t h e s i s x c l o c = ”B6”∗/output AA MUTE; /∗ s yn t h e s i s x c l o c = ”D1”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// SDRAM//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−inout [ 1 5 : 0 ] RAM1 DQ; /∗ s yn t h e s i s x c l o c = ”G36 ,G37 ,G38 ,G39 , F36 ,

F37 , F38 , F39 ,E37 ,E38 ,E39 ,D37 ,D38 ,D39 ,C38 ,B37”∗/output RAM1 CLK; /∗ s yn t h e s i s x c l o c = ”N38”∗/output RAM1 CLKE; /∗ s yn t h e s i s x c l o c = ”N39”∗/output RAM1DQMH; /∗ s yn t h e s i s x c l o c = ”N37”∗/output RAM1 DQML; /∗ s yn t h e s i s x c l o c = ”N36”∗/output RAM1 CS ; /∗ s yn t h e s i s x c l o c = ”W37”∗/

5

output RAM1 RAS ; /∗ s yn t h e s i s x c l o c = ”P37”∗/output RAM1 CAS ; /∗ s yn t h e s i s x c l o c = ”P38”∗/output RAM1 WE ; /∗ s yn t h e s i s x c l o c = ”P39”∗/output [ 1 : 0 ] RAM1 BA; /∗ s yn t h e s i s x c l o c = ”AA37,W36”∗/output [ 1 2 : 0 ] RAM1 A; /∗ s yn t h e s i s x c l o c = ”AC36,AC35,AB39,AB38,

AB37,AB36,AB35,AA39,AA38,AA36,Y39 ,Y38 ,W39”∗/

inout [ 1 5 : 0 ] RAM2 DQ; /∗ s yn t h e s i s x c l o c = ”L36 , L37 , L38 , L39 ,K36 ,K37 ,K38 ,K39 , J36 , J37 , J38 , J39 ,H36 ,H37 ,H38 ,H39”∗/

output RAM2 CLK; /∗ s yn t h e s i s x c l o c = ”M39”∗/output RAM2 CLKE; /∗ s yn t h e s i s x c l o c = ”M38”∗/output RAM2DQMH; /∗ s yn t h e s i s x c l o c = ”M37”∗/output RAM2 DQML; /∗ s yn t h e s i s x c l o c = ”P36”∗/output RAM2 CS ; /∗ s yn t h e s i s x c l o c = ”R36”∗/output RAM2 RAS ; /∗ s yn t h e s i s x c l o c = ”R37”∗/output RAM2 CAS ; /∗ s yn t h e s i s x c l o c = ”R38”∗/output RAM2 WE ; /∗ s yn t h e s i s x c l o c = ”R39”∗/output [ 1 : 0 ] RAM2 BA; /∗ s yn t h e s i s x c l o c = ”T38 ,T39”∗/output [ 1 2 : 0 ] RAM2 A; /∗ s yn t h e s i s x c l o c = ”W38,V35 ,V36 ,V37 ,V38 ,

V39 ,U35 ,U36 ,U37 ,U38 ,U39 ,T36 ,T37”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Buttons and DIP Switches//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−input [ 8 : 1 ] SW9 ; /∗ s yn t h e s i s x c l o c = ”AN37,AN36,AM39,AM38,

AM37,AM36,AL39 ,AL38”∗/input [ 8 : 1 ] SW10 ; /∗ s yn t h e s i s x c l o c = ”AR37,AR36,AP39,AP38,

AP37,AP36,AN39,AN38”∗/input [ 8 : 1 ] SW ; /∗ s yn t h e s i s x c l o c = ”AT39,AT38,AR39,AR38,

AF36 ,AE39,AE38,AE37”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// System ACE Chip//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−input ACEMPBRDY; /∗ s yn t h e s i s x c l o c = ”M2”∗/output ACE MPIRQ; /∗ s yn t h e s i s x c l o c = ”M3”∗/output ACE MPCE B; /∗ s yn t h e s i s x c l o c = ”N1”∗/output ACE MPWE B; /∗ s yn t h e s i s x c l o c = ”N2”∗/output ACE MPOE B; /∗ s yn t h e s i s x c l o c = ”N3”∗/output [ 6 : 0 ] ACE MPA; /∗ s yn t h e s i s x c l o c = ”T1,R4,R3,R2,P2 ,P1 ,N4”

∗/inout [ 1 5 : 0 ] ACE MPD; /∗ s yn t h e s i s x c l o c = ”W4,W3,W2,V5,V4,V3,V2,

V1,U5,U4,U3,U2,U1,T4,T3,T2”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Video Encoder//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−output [ 9 : 0 ] VE P ; /∗ s yn t h e s i s x c l o c = ”AM3,AM4,AL1,AL2,AL3,

AL4,AK1,AK2,AK3,AK4”∗/output VE SCLK; /∗ s yn t h e s i s x c l o c = ”AM2”∗/output VE SDA; /∗ s yn t h e s i s x c l o c = ”AM1”∗/output VE PAL NTSC; /∗ s yn t h e s i s x c l o c = ”AN4”∗/output VE RESET B ; /∗ s yn t h e s i s x c l o c = ”AN3”∗/output VE HSYNC B ; /∗ s yn t h e s i s x c l o c = ”AN2”∗/output VE VSYNC B ; /∗ s yn t h e s i s x c l o c = ”AN1”∗/output VE BLANK B ; /∗ s yn t h e s i s x c l o c = ”AP4”∗/output VE SCRESET; /∗ s yn t h e s i s x c l o c = ”AP3”∗/output VE CLKIN; /∗ s yn t h e s i s x c l o c = ”AP2”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Video Decoder//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−input [ 2 : 1 ] VD LLC; /∗ s yn t h e s i s x c l o c = ”AA3,AB2”∗/input [ 9 : 0 ] VD P; /∗ s yn t h e s i s x c l o c = ”AC5,AB1,AB3,AB4,AB5,

6

AA1,AA2,Y1,Y2,W1”∗/output VD SCLK; /∗ s yn t h e s i s x c l o c = ”AC4”∗/output VD SDA; /∗ s yn t h e s i s x c l o c = ”AC3”∗/output VD ISO ; /∗ s yn t h e s i s x c l o c = ”AC2”∗/output VD RESET B ; /∗ s yn t h e s i s x c l o c = ”AC1”∗/output VD XTAL; /∗ s yn t h e s i s x c l o c = ”AA4”∗/

output VD AEF; /∗ s yn t h e s i s x c l o c = ”D6”∗/output VD AFF; /∗ s yn t h e s i s x c l o c = ”B7”∗/output VD CLKIN; /∗ s yn t h e s i s x c l o c = ”C6”∗/output VD DV; /∗ s yn t h e s i s x c l o c = ”C7”∗/output VD HFF; /∗ s yn t h e s i s x c l o c = ”A7”∗/output VD RD; /∗ s yn t h e s i s x c l o c = ”D7”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// USB In t e r f a c e (CHECK THIS)//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−output USB MODE; /∗ s yn t h e s i s x c l o c = ”A10”∗/output USB SPEED; /∗ s yn t h e s i s x c l o c = ”D8”∗/output USB SUSPEND; /∗ s yn t h e s i s x c l o c = ”A9”∗/

input USB RCV; /∗ s yn t h e s i s x c l o c = ”C8”∗/input USB VM; /∗ s yn t h e s i s x c l o c = ”C9”∗/input USB VP; /∗ s yn t h e s i s x c l o c = ”B9”∗/

output USB OE ; /∗ s yn t h e s i s x c l o c = ”D9”∗/output USB VMO FSEO; /∗ s yn t h e s i s x c l o c = ”B8”∗/output USB VPO; /∗ s yn t h e s i s x c l o c = ”A8”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// General Purpose LEDs//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−output [ 8 : 1 ] LED ; /∗ s yn t h e s i s x c l o c = ”AE36,AD39,AD38,AD37,

AD36,AC39,AC38,AC37”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// 7 segment LEDs x8//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−output [ 6 : 0 ] SEG1 ; /∗ s yn t h e s i s x c l o c = ”AV8,AW8,AU8,AT8,AV9,

AU9,AT9”∗/output [ 6 : 0 ] SEG2 ; /∗ s yn t h e s i s x c l o c = ”AU10,AV10,AT10,AW11,

AU11,AT11,AW12”∗/output [ 6 : 0 ] SEG3 ; /∗ s yn t h e s i s x c l o c = ”AT18,AR18,AU18,AV18,

AR17,AT17,AU17”∗/output [ 6 : 0 ] SEG4 ; /∗ s yn t h e s i s x c l o c = ”AU21,AT19,AT21,AV20,

AV21,AW21,AR22”∗/output [ 6 : 0 ] SEG5 ; /∗ s yn t h e s i s x c l o c = ”AW28,AT29,AV28,AU28,

AV27,AU27,AT27”∗/output [ 6 : 0 ] SEG6 ; /∗ s yn t h e s i s x c l o c = ”AT31,AU31,AW30,AV30,

AT30,AW29,AV29”∗/output [ 6 : 0 ] SEG7 ; /∗ s yn t h e s i s x c l o c = ”AU33,AV33,AT33,AW32,

AU32,AT32,AW31”∗/output [ 6 : 0 ] SEG8 ; /∗ s yn t h e s i s x c l o c = ”AU36,AV36,AW35,AV35,

AV34,AU34,AT34”∗/output [ 8 : 1 ] SEG POINT; /∗ s yn t h e s i s x c l o c = ”AW34,AV32,AU30,AW27,

AW20,AW18,AV11,AW9”∗/output [ 8 : 1 ] SEG COM ; /∗ s yn t h e s i s x c l o c = ”AW36,AW33,AV31,AU29,

AU19,AV19,AW10,AT7”∗///−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−output [ 1 9 : 0 ] PINOUT TOP; /∗ s yn t h e s i s x c l o c = ”M1,L4 ,L3 , L2 , L1 ,K4,K3,

K2,K1, J4 , J3 , J2 , J1 ,H4,H3,H2,H1,G4,G3,G2”∗/output [ 1 9 : 0 ] PINOUT LEFT CLOSE; /∗ s yn t h e s i s x c l o c = ”AP1,AR3,AR2,AR1,AT3,

AT2,AT1,AV3,AW4,AV4,AU4,AW5,AV5,AW6,AV6,AU6,AT6,AW7,AV7,AU7”∗/

7

output [ 1 9 : 0 ] PINOUT LEFT FAR; /∗ s yn t h e s i s x c l o c = ”AD4,AD2,AD1,AE4,AE3,AE2,AE1,AF4,AF3,AF2,AF1,AG4,AG3,AG1,AH3,AH2,AJ4 ,AJ3 ,AJ2 ,AJ1”∗/

output [ 1 9 : 0 ] PINOUT BOTTOM CLOSE; /∗ s yn t h e s i s x c l o c = ”AT22,AV22,AW22,AR23,AT23,AU23,AV23,AW23,AT24,AU24,AV24,AW24,AT25,AU25,AV25,AW25,AT26,AU26,AV26,AW26”∗/

output [ 1 9 : 0 ] PINOUT BOTTOM FAR; /∗ s yn t h e s i s x c l o c = ”AV12,AU12,AW13,AV13,AU13,AT13,AW14,AV14,AU14,AT14,AW15,AV15,AU15,AT15,AW16,AV16,AU16,AT16,AW17,AV17”∗/

output [ 1 9 : 0 ] PINOUT RIGHT; /∗ s yn t h e s i s x c l o c = ”AF37 ,AF38 ,AF39 ,AG36,AG37,AG38,AG39,AH37,AH38,AH39,AJ36 ,AJ37 ,AJ38 ,AJ39 ,AK36,AK37,AK38,AK39,AL36 ,AL37”∗/

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// SDRAM Wires from FPGA TOP//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−wire [ 3 1 : 0 ] RAMDQ;wire RAM CLK;wire RAM CLKE;wire RAMDQMH;wire RAMDQML;wire RAM CS ;wire RAM RAS ;wire RAM CAS ;wire RAM WE ;wire [ 1 : 0 ] RAM BA;wire [ 1 2 : 0 ] RAM A;//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Connect SDRAM wires to Pins//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−assign RAM1 DQ = RAMDQ[ 1 5 : 0 ] ;assign RAM1 CLK = RAM CLK;assign RAM1 CLKE = RAM CLKE;assign RAM1DQMH = RAMDQMH;assign RAM1 DQML = RAMDQML;assign RAM1 CS = RAM CS ;assign RAM1 RAS = RAM RAS ;assign RAM1 CAS = RAM CAS ;assign RAM1 WE = RAM WE ;assign RAM1 BA = RAM BA;assign RAM1 A = RAM A;

assign RAM2 DQ = RAMDQ[ 3 1 : 1 6 ] ;assign RAM2 CLK = RAM CLK;assign RAM2 CLKE = RAM CLKE;assign RAM2DQMH = RAMDQMH;assign RAM2 DQML = RAMDQML;assign RAM2 CS = RAM CS ;assign RAM2 RAS = RAM RAS ;assign RAM2 CAS = RAM CAS ;assign RAM2 WE = RAM WE ;assign RAM2 BA = RAM BA;assign RAM2 A = RAM A;//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Y5 Clock Buf fer//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−wire Y5 Clock ;

// Jgibson : removed to make s in g l e−s t epp ing the c l o c k work proper l y//BUFG Y5Buffer ( . I (Y5 CLK) , .O(Y5 Clock ) ) ;//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Route VE Clock

8

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−wire [ 9 : 0 ] VE P RAW;

assign VE CLKIN = ˜Y5 Clock ;assign VE P = VE P RAW;//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Replace Connections Hard−Wired on CaLinx1//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−assign VD RD = 1 ’ b0 ;assign VD CLKIN = 1 ’ b0 ;assign VD XTAL = ˜Y5 Clock ;//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Reset// Desc : Generate a board l e v e l r e s e t s i g n a l in order to// g i v e the user a way to r e s e t a l l o f the s t a t e// machines and pe r i ph e ra l ch ips//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−wire Reset , Reset raw ;

IBUF r e s e t b u f f e r ( . I (SW [ 5 ] ) , .O( Reset raw ) ) ;assign Reset = ˜ Reset raw ;//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−wire TFTP Clock ; // TFTP Clock

wire TFTP GoodFileName ;wire TFTP BadFileName ;wire [ 4 7 : 0 ] TFTP FileName ;wire Error ;wire DataReady ;wire [ 1 : 0 ] Board Address ; // The address o f your boardwire [ 1 0 : 0 ] TFTPMemAddress ;wire [ 3 1 : 0 ] TFTPMemDataOut ;wire TFTPMemEnable ;

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Clocks//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

// S ing l e Step Clockwire s i n g l e c l o c k ;

wire c lock button , c lock button raw ;IBUF c l o c k sw i t ch bu f ( . I (SW [ 4 ] ) , .O( c lock button raw ) ) ;assign c l o ck but ton = ˜ c lock button raw ;e d g e t r i g g e r s i n g l e s t ep d ebounc e r ( . in ( c l o ck but ton ) , . out ( s i n g l e c l o c k ) , . c l k (

memory clock ) ) ;

// Because o f i n c on s i s t e n c i e s between the Calinx1 and Calinx2 boards , you need tof eed a

// BUFGed 27MHz c l o ck back to the output Y5 Clock . I f you don ’ t then t h in g s may notwork proper l y .

// Unt i l you understand DLLs don ’ t change anything between DLL START and DLL END// This i s cu r r en t l y wired up to g i v e you your processor c l o c k on the wire :

p ro c e s s o r c l o c k// and your memory c l o c k on the wire : memory clock

// DLL START−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

9

wire VE CLOCK BUFFED;IBUFG ve buf ( . I (Y5 CLK) , .O(VE CLOCK BUFFED) ) ;

wire d l l 2x c l o ck , d l l 2 x l o ck ed ;wire l c k2de l ay ;wire clkmem dll , raw c lock ;wire memory clock , p r o c e s s o r c l o c k ;wire c l o c k s l o c k ed ;

CLKDLL d l l d b l ( .CLKIN(VE CLOCK BUFFED) , .CLKFB( d l l 2 x c l o c k ) , .RST(1 ’ b0 ) ,.CLK0( ) , . CLK90( ) , . CLK180 ( ) , . CLK270 ( ) ,.CLK2X( d l l 2 x c l o c k ) , .CLKDV() , .LOCKED( d l l 2 x l o ck ed ) ) /∗ s yn t h e s i s xc props

= ”LOC=DLL3S”∗/ ;

SRL16 rstSRL ( .D( d l l 2 x l o ck ed ) , .CLK( d l l 2 x c l o c k ) , .Q( l ck2de l ay ) , . A3(1 ’ b1 ) , . A2(1 ’ b1 ) , . A1(1 ’ b1 ) , . A0(1 ’ b1 ) ) ;

CLKDLL d l l p r c ( . CLKIN( d l l 2 x c l o c k ) , .CLKFB( memory clock ) , .RST(˜ l ck2de l ay ) ,.CLK0( clkmem dll ) , . CLK90( ) , . CLK180 ( ) , . CLK270 ( ) ,

.CLK2X( ) , .CLKDV( raw c lock ) , .LOCKED( c l o c k s l o c k ed ) ) /∗ s yn t h e s i sxc props = ”LOC=DLL3P”∗/ ;

defparam d l l p r c .CLKDV DIVIDE = ” 1 .5 ” ;

BUFG memory clkg ( . I ( c lkmem dll ) , .O( memory clock ) ) ;BUFG pr o c e s s o r c l k g ( . I ( raw c lock ) , .O( p r o c e s s o r c l o c k ) ) ;

/∗wire VE CLOCK BUFFED, CLK0, CLK0 dll , CLK2X180 , CLK2X180 dll , CLK DIV, CLK DIV dll ,

CLK90 dll ;wire CLK0b dll , CLK DIVB dll , CLK DIVB;

wire proce s so r c l o ck , proces sor c lock raw , raw clock , memory clock ;parameter d i v i d ed = 1 ’ b1 ;

IBUFG ve bu f ( . I (Y5 CLK) , .O(VE CLOCK BUFFED) ) ;

CLKDLLE d l l ( .CLKIN(VE CLOCK BUFFED) , .CLKFB(CLK0 dll ) , .RST(1 ’ b0 ) ,.CLK0(CLK0 dll ) , .CLK90() , .CLK180() , .CLK270() ,.CLK2X() , .CLKDV(CLK DIV dll ) , .LOCKED() , .CLK2X180() ) ;

// These params may not work i f you are not us ing Synp l i f y f o r Syn thes i s// These are the v a l i d d i v i s i o n f a c t o r s 1 . 5 , 2 , 2 . 5 , 3 , 4 , 5 , 8 , or 16// When you are s yn t h e s i z i n g you must enc lo se the va lue in ”” s and you shou ld use a

. 0 a f t e r// whole numbers , eg . ”2 . 0”// However , when you are s imu la t ing you must exc lude the quotes .

defparam d l l .STARTUP WAIT = ”TRUE”;‘ i f d e f s yn t h e s i s

defparam d l l .CLKDV DIVIDE = ”4.0” ;‘ e l s e

defparam d l l .CLKDV DIVIDE = 4.0 ;‘ end i f

a s s i gn raw c lock = d i v i d ed ? CLK DIV dll : CLK0 dll ;a s s i gn proce s so r c l o ck raw = ˜SW10 [ 1 ] ? raw c lock : s i n g l e c l o c k ;

BUFG pro c e s s o r c l k g ( . I ( p roce s so r c l o ck raw ) , .O( p roc e s s o r c l o c k ) ) ;// as s i gn memory clock = proc e s s o r c l o c k ;

BUFG memory clkg ( . I ( CLK0 dll ) , .O(memory clock ) ) ;∗//∗

// DLL START−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

wire d l l 2 x c l o c k , d l l 2 x l o c k ed , c lkmem dl l ;wire proce s so r c l o ck , proces sor c lock raw , raw clock , memory clock ;parameter d i v i d ed = 1 ’ b1 ;

10

IBUFG ve bu f ( . I (Y5 CLK) , .O(VE CLOCK BUFFED) ) ;

CLKDLLE d l l b d l ( .CLKIN(VE CLOCK BUFFED) , .CLKFB( d l l 2 x c l o c k ) , .RST(1 ’ b0 ) ,.CLK0() , .CLK90() , .CLK180() , .CLK270() ,.CLK2X( d l l 2 x c l o c k ) , .CLKDV() , .LOCKED( d l l 2 x l o c k e d ) , .CLK2X180

() ) ;CLKDLLE d l l p r c ( .CLKIN( d l l 2 x c l o c k ) , .CLKFB(memory clock ) , .RST(˜ d l l 2 x l o c k e d ) ,

.CLK0( c lkmem dl l ) , .CLK90() , .CLK180() , .CLK270() ,.CLK2X() , .CLKDV( raw c lock ) , .LOCKED() , .

CLK2X180() ) ;

// These params may not work i f you are not us ing Synp l i f y f o r Syn thes i s// These are the v a l i d d i v i s i o n f a c t o r s 1 . 5 , 2 , 2 . 5 , 3 , 4 , 5 , 8 , or 16// When you are s yn t h e s i z i n g you must enc lo se the va lue in ”” s and you shou ld use a

. 0 a f t e r// whole numbers , eg . ”2 . 0”// However , when you are s imu la t ing you must exc lude the quotes .defparam d l l b d l .STARTUP WAIT = ”TRUE”;defparam d l l p r c .STARTUP WAIT = ”TRUE”;‘ i f d e f s yn t h e s i s

defparam d l l p r c .CLKDV DIVIDE = ”4.0” ;‘ e l s e

defparam d l l p r c .CLKDV DIVIDE = 4;‘ end i f

a s s i gn proce s so r c l o ck raw = ˜SW10 [ 1 ] ? raw c lock : s i n g l e c l o c k ;

BUFG pro c e s s o r c l k g ( . I (VE CLOCK BUFFED) , .O( p ro c e s s o r c l o c k ) ) ;BUFG memory clkg ( . I (VE CLOCK BUFFED) , .O(memory clock ) ) ;//BUFG pro c e s s o r c l k g ( . I ( p roce s so r c l o ck raw ) , .O( p roc e s s o r c l o c k ) ) ;//BUFG memory clkg ( . I ( c lkmem dl l ) , .O(memory clock ) ) ;// DLL END−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

∗/lab4group01blackbox network black box (.TXD0 (PHY TXD0) ,.TXD1 (PHY TXD1) ,.TXD2 (PHY TXD2) ,.TXD3 (PHY TXD3) ,.TX EN (PHY TX EN) ,.TX ER (PHY TX ER) ,.TX CLK (PHY TX CLK) ,.RXD0 (PHY RXD0) ,.RXD1 (PHY RXD1) ,.RXD2 (PHY RXD2) ,.RXD3 (PHY RXD3) ,.RX DV (PHY RX DV) ,.RX ER (PHY RX ER) ,.RX CLK (PHY RX CLK) ,.COL (PHY COL) ,. CRS (PHY CRS) ,.MDIO (PHY MDIO) ,.MDINT (PHY MDINT ) ,.MDC (PHY MDC) ,.MDDIS (PHY MDDIS) ,.TRSTE (PHY TRSTE) ,.CFG (PHY CFG) ,. FDE (PHY FDE) ,.BYPSCR (PHY BYPSCR) ,.AUTOENA (PHY AUTOENA) ,.ADD (PHY ADD) ,.RESET OUT (PHY RESET) ,.PWRDN (PHYPWRDN) ,. LED0 (PHY LED0 ) ,. LED1 (PHY LED1 ) ,. LED2 (PHY LED2 ) ,. LED3 (PHY LED3 ) ,.LEDENA (PHY LEDENA) ,

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.LEDCLK (PHY LEDCLK) ,

.LEDDAT (PHY LEDDAT) ,

. RJ45 TRC (RJ45 TRC ) ,

. RJ45 BRC (RJ45 BRC ) ,

. RJ45 TLC (RJ45 TLC ) ,

. RJ45 BLC (RJ45 BLC ) ,

. TFTP Clock (TFTP Clock ) ,// . TFTP BadFileName (TFTP BadFileName) ,. TFTP BadFileName (1 ’ b0 ) ,. TFTP GoodFileName (TFTP GoodFileName) ,. TFTP FileName (TFTP FileName) ,. Board Address ( Board Address ) ,. DataReady (DataReady ) ,. Er ror ( Error ) ,. Externa lAddress (TFTPMemAddress) ,. Externa lClock ( p r o c e s s o r c l o c k ) ,. ExternalDataOut (TFTPMemDataOut) ,. Externa lEnable (TFTPMemEnable) ,. RESET IN ( Reset )

) ;

// ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

//IO S t u f freg [ 3 1 : 0 ] IO LED ;wire [ 7 : 0 ] STAT;wire [ 3 1 : 0 ] DP0 , DP1;wire [ 6 3 : 0 ] ASCII REG ;

wire [ 3 1 : 0 ] SWITCH;

assign SWITCH = {24 ’ b0 , SW9 } ;

wire [ 1 : 0 ] i o S e l = {˜SW10 [ 5 ] , ˜ SW10 [ 6 ] } ;wire [ 6 3 : 0 ] c y c l e s ;

always@ (∗ )begin

case ( i o S e l )2 ’ b00 : IO LED = {24 ’ b0 , STAT} ;2 ’ b01 : IO LED = DP0;2 ’ b11 : IO LED = DP1;2 ’ b10 : IO LED = 32 ’ h f f f f f f f f ;endcase

end

//Break Inputwire b r e a k r e l e a s e ;wire break buf , break buf neg ;assign break buf = ˜ break buf neg ;IBUF b r e a k r e l b u f ( . I (SW [ 8 ] ) , .O( break buf neg ) ) ;e d g e t r i g g e r b r e a k t r i g g e r ( . c l k ( p r o c e s s o r c l o c k ) , . in ( break buf ) , . out ( b r e a k r e l e a s e

) ) ;

//Resetwire p r o c e s s o r r e s e t ;wire p r o c e s s o r r e s e t bu f , p r o c e s s o r r e s e t bu f n e g ;assign p r o c e s s o r r e s e t b u f = ˜ p r o c e s s o r r e s e t bu f n e g ;IBUF p r o c e s s o r r e l b u f ( . I (SW [ 3 ] ) , .O( p r o c e s s o r r e s e t bu f n e g ) ) ;assign p r o c e s s o r r e s e t = ˜ p r o c e s s o r r e s e t bu f n e g ;

// e d g e t r i g g e r p r o c e s s o r t r i g g e r ( . c l k ( p ro c e s s o r c l o c k ) , . in ( p r o c e s s o r r e s e t b u f ) , . out (p r o c e s s o r r e s e t ) ) ;

wire [ 8 : 1 ] p o i n t r e g ;wire [ 3 1 : 0 ] boot0Data ;

// In s t r u c t i on Memory VIA TFTPwire [ 3 1 : 0 ] INSTR ADDR /∗ s yn t h e s i s syn maxfan=4∗/ ;

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wire [ 3 1 : 0 ] INSTR DOUT, boot0Data ;

// ass i gn INSTR DOUT = TFTPMemDataOut ;assign boot0Data = TFTPMemDataOut ;

//Data Cache S i gna l swire [ 3 1 : 0 ] DATA ADDR;wire [ 3 1 : 0 ] DATA DIN;wire [ 3 1 : 0 ] DATA DOUT;wire data wr i t e ;wire data enab le ;wire data miss ;wire da t a f l u sh ;

// ass i gn TFTPMemAddress = DATAADDR[ 1 2 : 2 ] ; / /INSTR ADDR[ 1 2 : 2 ] ;

//SDRAM Cont ro l l e r + Arb i t e r S i gna l swire [ 2 5 5 : 0 ] output from SDC ;wire [ 2 5 5 : 0 ] wr ite data to SDC ;wire [ 3 1 : 0 ] dmem arb addr ;wire dmem arb read , dmem arb write , arb dmem ready ;

wire sdc read , sdc wr i t e , sdc ready ;wire [ 3 1 : 0 ] a rb to sdc addr ;wire sd c t o a rb r eady ;wire a rb to sd c a ck ;

wire r s t = p r o c e s s o r r e s e t | ˜ DataReady | ˜ c l o c k s l o c k ed ;wire i n s t r m i s s ;

wire i s t a l l , l a t ch i d , branch mispred i c t ;

PipelinedCPU lab5 proc ( . c l k ( p r o c e s s o r c l o c k ) , . r s t ( r s t ) ,. b r e a k r e l e a s e ( b r e a k r e l e a s e ) , .STAT(STAT) ,.INST MEMADDR(INSTR ADDR) , .INST MEMDATA(INSTR DOUT) ,.DMEMADDR(DATA ADDR) , .DMEM DIN(DATA DOUT) , .DMEMDOUT(DATA DIN)

,. dmem write ( da ta wr i t e ) , . dmem enable ( data enab le ) ,. dcache miss ( data miss ) , . d ca che f l u sh ( da t a f l u sh ) , .CYCLE COUNT(

cy c l e s ) ,. i c a che m i s s ( i n s t r m i s s ) , . i s t a l l ( i s t a l l ) ,

. b ranch mispred i c t ( branch mispred i c t) , . l a t c h i d ( l a t c h i d)

) ;

wire [ 3 1 : 0 ] imem arb addr ;wire imem arb read , arb imem ready ;

reg [ 3 1 : 0 ] pctmp /∗ s yn t h e s i s syn maxfan=4∗/ ;always@ (INSTR ADDR) pctmp = INSTR ADDR;

imem instrMemory ( . c l k ( p r o c e s s o r c l o c k ) , . r s t ( r s t ) ,

.ADDRESS(pctmp) , .DOUT(INSTR DOUT) ,

. i c a che m i s s ( i n s t r m i s s ) , . p i p e l i n e s t a l l ( i s t a l l ) ,

.DRAM DIN( output from SDC ) , .DRAMADDR( imem arb addr ) ,. b ranch mispred i c t ( branch mispred i c t

) , . l a t c h i d ( l a t c h i d ) ,. dram read ( imem arb read ) , . dram ready ( arb imem ready ) ) /∗ s yn t h e s i s

syn maxfan=4∗/ ;

//Data Memory

13

wire buf dmem ready , bu f a rb wr i t e , bu f arb read , dmem buf read , dmem buf write ,arb buf ready , arb wr ready ;

wire [ 2 5 5 : 0 ] CACHE WIDE OUT, CACHE WIDE IN;wire [ 3 1 : 0 ] dmem buf addr , bu f arb addr ;

dmem dataMemory ( . c l k ( p r o c e s s o r c l o c k ) , . r s t ( r s t ) ,

.ADDRESS(DATA ADDR) , .DIN(DATA DIN) , .DOUT(DATA DOUT) , . wr i t e (da ta wr i t e ) , . enable ( data enab le ) ,

. dcache miss ( data miss ) , . d ca che f l u sh ( da t a f l u sh ) ,

.DRAM DIN( output from SDC ) , .DRAMDOUT( write data to SDC ) , .DRAMADDR(dmem buf addr ) ,

. dram read ( bu f a rb r ead ) , . dram write ( bu f a rb wr i t e ) , . dram ready (arb bu f r eady | arb wr ready ) ,

.BOOT0 DATA( boot0Data ) , .BOOT0 ADDR(TFTPMemAddress) , . boot0wr i te ( ) ,

.SWITCH(SWITCH) , .DP0(DP0) , .DP1(DP1) ,

. ASCII REG(ASCII REG) , .POINT REG( po in t r e g ) ,

.CYCLE COUNT( cy c l e s ) ) ;

a r b i t e r arb ( . c l k ( p r o c e s s o r c l o c k ) , . r s t ( r s t ) ,. INST ADDR( imem arb addr ) , . i n s t r e a d ( imem arb read ) , . i n s t r e ady (

arb imem ready ) ,.DATA ADDR( dmem buf addr ) , . data read ( bu f a rb r ead ) , . da ta wr i t e (

bu f a rb wr i t e ) , .DATA WRITE ADDR( dmem buf addr ) ,. data ready ( arb bu f r eady ) , . data wr ready ( arb wr ready ) ,

//TO SDRAM COntro l ler. mem read ( sdc read ) , . mem write ( sd c wr i t e ) , .ADDR OUT( arb to sdc addr ) ,. mem done ( sdc t o a rb r eady ) , . mem ack ( a rb to sd c a ck ) ) ;

sdramContro l l e r sdc ( . sdrcClk ( memory clock ) , . r s t ( r s t ) ,.RAM DQ (RAMDQ) ,.RAM CLK (RAM CLK) ,.RAM CLKE (RAM CLKE) ,.RAM DQMH (RAMDQMH) ,.RAM DQML (RAMDQML) ,.RAM CS (RAM CS ) ,.RAM RAS (RAM RAS ) ,.RAM CAS (RAM CAS ) ,.RAM WE (RAM WE ) ,.RAM BA (RAM BA) ,.RAM A (RAM A) ,

.ADDRESS( a rb to sdc addr ) ,

. wr i t e ( sd c wr i t e ) , . read ( sdc read ) , . ack ( a rb t o sd c a ck ) ,

. ready ( sd c t o a rb r eady ) ,

.DIN( write data to SDC ) , .DOUT( output from SDC ) ) ;

assign TFTPMemEnable = 1 ’ b1 ;assign SEG POINT = { po in t r e g [ 1 ] , p o i n t r e g [ 2 ] , p o i n t r e g [ 3 ] , p o i n t r e g [ 4 ] ,

p o i n t r e g [ 5 ] , p o i n t r e g [ 6 ] , p o i n t r e g [ 7 ] , p o i n t r e g [ 8 ] } ;

// ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

//LED Outputassign Board Address = {˜SW10 [ 7 ] , ˜ SW10 [ 8 ] } ;

assign SEG COM = 8 ’ b0000 0000 ;wire [ 4 : 0 ] s eg in1 , s eg in2 , s eg in3 , s eg in4 , s eg in5 , s eg in6 , s eg in7 , s e g i n 8 ;

14

l e d t o o l uLed1 ( . code ( s e g i n 1 ) , . l ed (SEG1) ) ;l e d t o o l uLed2 ( . code ( s e g i n 2 ) , . l ed (SEG2) ) ;l e d t o o l uLed3 ( . code ( s e g i n 3 ) , . l ed (SEG3) ) ;l e d t o o l uLed4 ( . code ( s e g i n 4 ) , . l ed (SEG4) ) ;l e d t o o l uLed5 ( . code ( s e g i n 5 ) , . l ed (SEG5) ) ;l e d t o o l uLed6 ( . code ( s e g i n 6 ) , . l ed (SEG6) ) ;l e d t o o l uLed7 ( . code ( s e g i n 7 ) , . l ed (SEG7) ) ;l e d t o o l uLed8 ( . code ( s e g i n 8 ) , . l ed (SEG8) ) ;

assign LED = ˜STAT;

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// TFTP Test C i r cu i t// This i s a t e s t c i r c u i t t ha t I b u i l t to v e r i f y t ha t the network i n t e r f a c e was ok .// Before a t r an s f e r the segments w i l l read i d l e , i f t he re i s an error they w i l l

read f a i l .// You may wr i t e once to the board and then read once from the board . Af ter t ha t

you have to r e s e t i t .// After a f i l e i s s u c c e s s f u l l y uploaded to the board then the segment l e d s w i l l

read the content s o f memory// un l e s s d ip sw i t ch #2 of 10 i s on then the the segment l e d s w i l l show the f i l ename

of the f i l e t ha t was sent to the board .//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

// ass i gn TFTP GoodFileName = ˜SW10 [ 2 ] ;assign TFTP GoodFileName = 1 ’ b1 ;

reg [ 4 : 0 ] s e g i n1 r , s e g i n2 r , s e g i n3 r , s e g i n4 r , s e g i n5 r , s e g i n6 r , s e g i n7 r ,s e g i n 8 r ;

assign s e g i n 1 = s e g i n 1 r ;assign s e g i n 2 = s e g i n 2 r ;assign s e g i n 3 = s e g i n 3 r ;assign s e g i n 4 = s e g i n 4 r ;assign s e g i n 5 = s e g i n 5 r ;assign s e g i n 6 = s e g i n 6 r ;assign s e g i n 7 = s e g i n 7 r ;assign s e g i n 8 = s e g i n 8 r ;

wire [ 7 : 0 ] char8 = ASCII REG [ 7 : 0 ] ,char7 = ASCII REG [ 1 5 : 8 ] ,

char6 = ASCII REG [ 2 3 : 1 6 ] ,char5 = ASCII REG [ 3 1 : 2 4 ] ,char4 = ASCII REG [ 3 9 : 3 2 ] ,char3 = ASCII REG [ 4 7 : 4 0 ] ,char2 = ASCII REG [ 5 5 : 4 8 ] ,char1 = ASCII REG [ 6 3 : 5 6 ] ;

wire [ 4 : 0 ] asc iSeg1 , asc iSeg2 , asc iSeg3 , asc iSeg4 , asc iSeg5 , asc iSeg6 , asc iSeg7 ,a s c iSeg8 ;

a s c i i c o n v e r t ac1 ( . a s c i iCode In ( char1 ) , . encodingCodeOut ( a s c iSeg1 ) ) ;a s c i i c o n v e r t ac2 ( . a s c i iCode In ( char2 ) , . encodingCodeOut ( a s c iSeg2 ) ) ;a s c i i c o n v e r t ac3 ( . a s c i iCode In ( char3 ) , . encodingCodeOut ( a s c iSeg3 ) ) ;a s c i i c o n v e r t ac4 ( . a s c i iCode In ( char4 ) , . encodingCodeOut ( a s c iSeg4 ) ) ;a s c i i c o n v e r t ac5 ( . a s c i iCode In ( char5 ) , . encodingCodeOut ( a s c iSeg5 ) ) ;a s c i i c o n v e r t ac6 ( . a s c i iCode In ( char6 ) , . encodingCodeOut ( a s c iSeg6 ) ) ;a s c i i c o n v e r t ac7 ( . a s c i iCode In ( char7 ) , . encodingCodeOut ( a s c iSeg7 ) ) ;a s c i i c o n v e r t ac8 ( . a s c i iCode In ( char8 ) , . encodingCodeOut ( a s c iSeg8 ) ) ;

always @ ( ∗ ) begini f (˜SW10 [ 2 ] )begin

s e g i n 1 r <= asc iSeg1 ;s e g i n 2 r <= asc iSeg2 ;s e g i n 3 r <= asc iSeg3 ;s e g i n 4 r <= asc iSeg4 ;s e g i n 5 r <= asc iSeg5 ;

15

s e g i n 6 r <= asc iSeg6 ;s e g i n 7 r <= asc iSeg7 ;s e g i n 8 r <= asc iSeg8 ;

endelsei f (˜SW10 [ 3 ] )begin

s e g i n 1 r <= IO LED [ 3 1 : 2 8 ] ;s e g i n 2 r <= IO LED [ 2 7 : 2 4 ] ;s e g i n 3 r <= IO LED [ 2 3 : 2 0 ] ;s e g i n 4 r <= IO LED [ 1 9 : 1 6 ] ;s e g i n 5 r <= IO LED [ 1 5 : 1 2 ] ;s e g i n 6 r <= IO LED [ 1 1 : 8 ] ;s e g i n 7 r <= IO LED [ 7 : 4 ] ;s e g i n 8 r <= IO LED [ 3 : 0 ] ;

endelse

i f ( Error )begin

s e g i n 1 r <= 5’ h0f ;s e g i n 2 r <= 5’h0a ;s e g i n 3 r <= 5’h12 ;s e g i n 4 r <= 5’h14 ;s e g i n 5 r <= 5’h1e ;s e g i n 6 r <= 5’h1e ;s e g i n 7 r <= 5’h1e ;s e g i n 8 r <= 5’h1e ;

endelsebegin

i f (˜DataReady )begin

s e g i n 1 r <= 5’h1e ;s e g i n 2 r <= 5’h1e ;s e g i n 3 r <= 5’h12 ;s e g i n 4 r <= 5’h0d ;s e g i n 5 r <= 5’h14 ;s e g i n 6 r <= 5’h0e ;s e g i n 7 r <= 5’h1e ;s e g i n 8 r <= 5’h1e ;

endelsebegin

i f (˜SW10 [ 4 ] )begin

s e g i n 1 r <= {1 ’b0 , INSTR ADDR[ 3 1 : 2 8 ] } ;s e g i n 2 r <= {1 ’b0 , INSTR ADDR[ 2 7 : 2 4 ] } ;s e g i n 3 r <= {1 ’b0 , INSTR ADDR[ 2 3 : 2 0 ] } ;s e g i n 4 r <= {1 ’b0 , INSTR ADDR[ 1 9 : 1 6 ] } ;s e g i n 5 r <= {1 ’b0 , INSTR ADDR[ 1 5 : 1 2 ] } ;s e g i n 6 r <= {1 ’b0 , INSTR ADDR[ 1 1 : 8 ] } ;s e g i n 7 r <= {1 ’b0 , INSTR ADDR [ 7 : 4 ] } ;s e g i n 8 r <= {1 ’b0 , INSTR ADDR [ 3 : 0 ] } ;

/∗s e g in1 r <= {1’b0 , TFTP FileName [ 4 7 : 4 4 ] } ;s e g in2 r <= {1’b0 , TFTP FileName [ 4 3 : 4 0 ] } ;s e g in3 r <= {1’b0 , TFTP FileName [ 3 9 : 3 6 ] } ;s e g in4 r <= {1’b0 , TFTP FileName [ 3 5 : 3 2 ] } ;s e g in5 r <= {1’b0 , TFTP FileName [ 3 1 : 2 8 ] } ;s e g in6 r <= {1’b0 , TFTP FileName [ 2 7 : 2 4 ] } ;s e g in7 r <= {1’b0 , TFTP FileName [ 2 3 : 2 0 ] } ;s e g in8 r <= {1’b0 , TFTP FileName [ 1 9 : 1 6 ] } ;

∗/endelsebegin

s e g i n 1 r <= {1 ’b0 , INSTR DOUT[ 3 1 : 2 8 ] } ;

16

s e g i n 2 r <= {1 ’b0 , INSTR DOUT[ 2 7 : 2 4 ] } ;s e g i n 3 r <= {1 ’b0 , INSTR DOUT[ 2 3 : 2 0 ] } ;s e g i n 4 r <= {1 ’b0 , INSTR DOUT[ 1 9 : 1 6 ] } ;s e g i n 5 r <= {1 ’b0 , INSTR DOUT[ 1 5 : 1 2 ] } ;s e g i n 6 r <= {1 ’b0 , INSTR DOUT[ 1 1 : 8 ] } ;s e g i n 7 r <= {1 ’b0 , INSTR DOUT [ 7 : 4 ] } ;s e g i n 8 r <= {1 ’b0 , INSTR DOUT [ 3 : 0 ] } ;

/∗

s e g in1 r <= {1’b0 , TFTPMemDataOut [ 3 1 : 2 8 ] } ;s e g in2 r <= {1’b0 , TFTPMemDataOut [ 2 7 : 2 4 ] } ;s e g in3 r <= {1’b0 , TFTPMemDataOut [ 2 3 : 2 0 ] } ;s e g in4 r <= {1’b0 , TFTPMemDataOut [ 1 9 : 1 6 ] } ;s e g in5 r <= {1’b0 , TFTPMemDataOut [ 1 5 : 1 2 ] } ;s e g in6 r <= {1’b0 , TFTPMemDataOut [ 1 1 : 8 ] } ;s e g in7 r <= {1’b0 , TFTPMemDataOut [ 7 : 4 ] } ;s e g in8 r <= {1’b0 , TFTPMemDataOut [ 3 : 0 ] } ;

∗/end

endend

end

/∗wire [ 3 5 : 0 ] c s c on t r o l ;wire [ 2 5 5 : 0 ] c s da ta ;wire [ 7 : 0 ] c s t r i g 0 ;

a s s i gn cs da ta = { proce s sor c l o ck ,imem arb read , arb imem ready ,

bu f arb read , bu f a r b wr i t e ,arb bu f ready , arb wr ready ,

b r eak r e l ea s e , 24 ’ h0 ,

INSTR ADDR, INSTR DOUT, 21 ’ h0 , TFTPMemAddress , TFTPMemDataOut , DATA DIN, 64 ’ h0 } ;

a s s i gn c s t r i g 0 = {5 ’h0 , b r eak r e l ea s e , in s t r mi s s , data miss } ;

i l a i i l a(

. con t ro l ( c s c on t r o l ) ,

. c l k ( p ro c e s s o r c l o c k ) ,

. data ( c s da ta ) ,

. t r i g 0 ( c s t r i g 0 )) ;

icon i i c on(

. con t ro l 0 ( c s c on t r o l )) ;

∗/endmodule

module i con(

con t r o l 0) /∗ s yn t h e s i s s yn b l a c k box syn noprune=1 ∗/ ;output [ 3 5 : 0 ] c on t r o l 0 ;

endmodule

module i l a(

cont ro l ,c lk ,data ,t r i g 0

) /∗ s yn t h e s i s s yn b l a c k box syn noprune=1 ∗/ ;input [ 3 5 : 0 ] c on t r o l ;

17

input c l k ;input [ 2 5 5 : 0 ] data ;input [ 7 : 0 ] t r i g 0 ;

endmodule

A.2 Processor Datapath

// $Header : U:\\CVSLab3\\CVSLab3/ lab6b /PipelinedCPU . v , v 1 .2 2004/05/16 06 :53 :20 cs152−ah Exp$

// $Author : cs152−ah $// $Date : 2004/05/16 06 :53 :20 $

‘ t ime s ca l e 1 ns /10 ps

module PipelinedCPU ( clk , r s t ,b r e ak r e l e a s e , STAT,INST MEMADDR, INST MEMDATA,DMEMADDR, DMEM DIN, DMEMDOUT,dmem write , dmem enable ,dcache miss , dcache f lu sh , CYCLE COUNT, i cache mis s , i s t a l l ,

branch mispred ict , l a t c h i d ) ;input c lk , r s t ;

output i s t a l l ;

input [ 3 1 : 0 ] CYCLE COUNT;input b r e a k r e l e a s e ;output [ 7 : 0 ] STAT;

input [ 3 1 : 0 ] INST MEMDATA;output [ 3 1 : 0 ] INST MEMADDR;

output [ 3 1 : 0 ] DMEMADDR;input [ 3 1 : 0 ] DMEM DIN;output [ 3 1 : 0 ] DMEMDOUT;output dmem write , dmem enable ;

input dcache miss ;input i c a che m i s s ;output dcache f l u sh ;output branch mispred i c t ;input l a t c h i d ;

wire [ 3 1 : 0 ] INSTRUCTION;

wire [ 5 : 0 ] ALU OP;wire [ 4 : 0 ] REG DST;wire [ 2 : 0 ] JB TYPE;wire [ 2 : 0 ] ALU SRCB;wire ext op , mem write , mem read , mem to reg , r eg wr i t e , u s e r s , u s e r t , mfhi lo ,

mul t s ta r t , d i v s t a r t ;wire [ 1 : 0 ] SHIFT OP ;wire s h i f t ;

wire g l o b s t a l l ;wire [ 3 1 : 0 ] i f i ;

wire [ 4 : 0 ] SMNT;

c o n t r o l l e r myControl ler ( c lk , r s t , INSTRUCTION, ALU OP, REG DST, JB TYPE , ALU SRCB,ext op , mem write , mem read , mem to reg , r eg wr i t e , u s e r s , u s e r t ,mfhi lo , mul t s ta r t , d i v s t a r t , SHIFT OP , s h i f t , SMNT) ;

datapath proc datapath (. c l k ( c l k ) ,. r s t ( r s t ) ,. g l o b a l s t a l l ( g l o b s t a l l ) ,. mu l t s t a r t ( mu l t s t a r t ) ,. d i v s t a r t ( d i v s t a r t ) ,

18

. mfh i lo ( mfh i lo ) ,

. u s e r t ( u s e r t ) ,

. u s e r s ( u s e r s ) ,

.ALU SRCB(ALU SRCB) ,

.ALU OP(ALU OP) ,

. ext op ( ext op ) ,

.REG DST(REG DST) ,

. r e g w r i t e ( r e g w r i t e ) ,

. mem write ( mem write ) ,

. mem read (mem read ) ,

. mem to reg ( mem to reg ) ,

. INSTRUCTION(INSTRUCTION) ,

.JUMP OP(JB TYPE) ,

.INST MEMADDR(INST MEMADDR) ,

.INST MEMDATA(INST MEMDATA) ,

. dcache miss ( dcache miss ) ,

. i c a che m i s s ( i c a che m i s s ) ,

.RD DATA MEM OUT(DMEM DIN) ,

.DMEMADDR(DMEMADDR) ,

.DMEM DIN(DMEMDOUT) ,

. memenable ex1 ( dmem enable ) ,

. memwrite ex1 ( dmem write ) ,

. f l u s h ( dcache f l u sh ) ,

. s h i f t ( s h i f t ) ,

. SHIFT OP(SHIFT OP) , . i f i d s t a l l ( ) , . SMNT IN(SMNT) , . branch miss (branch mispred i c t ) , . l a t c h i d ( l a t c h i d ) , . p i p e l i n e s t a l l ( i s t a l l )

) ;

break module myBreakModule ( . c l k ( c l k ) , . r s t ( r s t ) , . INSTRUCTION(INSTRUCTION) , . b r e a k r e l e a s e( b r e a k r e l e a s e ) , . s t a l l ( g l o b s t a l l ) , .STAT(STAT) ) ;

//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−// Test S ca f f o l d S t u f f//−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

//TEST SCAFFOLD// s yn t h e s i s t r a n s l a t e o f fwire ha l t ;

//module d i sas semb le ( c lk , PC , IR , DOUTS , DOUTT , RD , MEM IN ) ;// input c l k ;// input [ 3 1 : 0 ] PC , IR , DOUTS , DOUTT , RD , MEM IN ;

//PC and IR are from IF s tage//DOUTS and DOUTT are from ID s tage//RD i s from WB stage (RD input to r e gF i l e )//MEM IN i s from MEM Stage ( output o f synchronous ram)

d i sa s s emble da ( . c l k ( c l k ) ,. PC ({ proc datapath . InstrMod .PC, 2 ’ b0 }) ,. IR ( proc datapath . InstrMod .INSTRUCTION) , . l a t c h i d ( l a t c h i d ) ,.DOUTS ( proc datapath . XLXN 416) ,.DOUTT ( proc datapath . XLXN 420) ,.RD ( proc datapath . RegFi le .DIN) ,.MEM IN (DMEMDOUT) ,. ha l t ( ha l t ) ,. cycleCount (CYCLE COUNT) ,. i f i d b ubb l e ( proc datapath . S t a l l L o g i c . i f i d b ubb l e ) , . i f i d s t a l l (

proc datapath . S t a l l L o g i c . i f i d s t a l l ) ,. id fw bubble ( proc datapath . S t a l l L o g i c . id fw bubble ) , . i d f w s t a l l (

proc datapath . S t a l l L o g i c . i d f w s t a l l ) ,. fwex1 bubble ( proc datapath . S t a l l L o g i c . fwex1 bubble ) , . f w e x 1 s t a l l (

proc datapath . S t a l l L o g i c . f w e x 1 s t a l l ) ,. ex1tc1 bubble (1 ’ b0 ) , . e x 1 t c 1 s t a l l ( proc datapath . S t a l l L o g i c . e x 1 e x 2 s t a l l

) ,. t c1 t c2 bubb l e (1 ’ b0 ) , . t c 1 t c 2 s t a l l ( proc datapath . S t a l l L o g i c .

ex2mem2 stal l ) ,. tc2mem bubble (1 ’ b0 ) , . t c2mem sta l l ( proc datapath . S t a l l L o g i c .

19

ex2mem2 stal l ) ,. memwb bubble ( proc datapath . S t a l l L o g i c . ex2mem2 stal l ) ) ;

integer f i l eD ;always@ ( ha l t )

begini f ( ha l t )

begin$d i sp l ay ( $time , ” SIMULATION ENDING . . . ” ) ;

//Dump Reg i s t e r sf i l eD = $fopen ( ” p ro c e s s o r . reg . dump . txt ” ) ;

/∗ $ f d i s p l a y ( f i l eD , ” $r0 = 0x%H” , proc datapath . RegFi le .mem[ 0 ] ) ;$ f d i s p l a y ( f i l eD , ” $r1 = 0x%H” , proc datapath . RegFi le .mem[ 1 ] ) ;$ f d i s p l a y ( f i l eD , ” $r2 = 0x%h” , proc datapath . RegFi le .mem[ 2 ] ) ;$ f d i s p l a y ( f i l eD , ” $r3 = 0x%h” , proc datapath . RegFi le .mem[ 3 ] ) ;$ f d i s p l a y ( f i l eD , ” $r4 = 0x%h” , proc datapath . RegFi le .mem[ 4 ] ) ;$ f d i s p l a y ( f i l eD , ” $r5 = 0x%h” , proc datapath . RegFi le .mem[ 5 ] ) ;$ f d i s p l a y ( f i l eD , ” $r6 = 0x%h” , proc datapath . RegFi le .mem[ 6 ] ) ;$ f d i s p l a y ( f i l eD , ” $r7 = 0x%h” , proc datapath . RegFi le .mem[ 7 ] ) ;$ f d i s p l a y ( f i l eD , ” $r8 = 0x%h” , proc datapath . RegFi le .mem[ 8 ] ) ;$ f d i s p l a y ( f i l eD , ” $r9 = 0x%h” , proc datapath . RegFi le .mem[ 9 ] ) ;$ f d i s p l a y ( f i l eD , ” $r10 = 0x%h” , proc datapath . RegFi le .mem[ 1 0 ] ) ;$ f d i s p l a y ( f i l eD , ” $r11 = 0x%h” , proc datapath . RegFi le .mem[ 1 1 ] ) ;$ f d i s p l a y ( f i l eD , ” $r12 = 0x%h” , proc datapath . RegFi le .mem[ 1 2 ] ) ;$ f d i s p l a y ( f i l eD , ” $r13 = 0x%h” , proc datapath . RegFi le .mem[ 1 3 ] ) ;$ f d i s p l a y ( f i l eD , ” $r14 = 0x%h” , proc datapath . RegFi le .mem[ 1 4 ] ) ;$ f d i s p l a y ( f i l eD , ” $r15 = 0x%h” , proc datapath . RegFi le .mem[ 1 5 ] ) ;$ f d i s p l a y ( f i l eD , ” $r16 = 0x%h” , proc datapath . RegFi le .mem[ 1 6 ] ) ;$ f d i s p l a y ( f i l eD , ” $r17 = 0x%h” , proc datapath . RegFi le .mem[ 1 7 ] ) ;$ f d i s p l a y ( f i l eD , ” $r18 = 0x%h” , proc datapath . RegFi le .mem[ 1 8 ] ) ;$ f d i s p l a y ( f i l eD , ” $r19 = 0x%h” , proc datapath . RegFi le .mem[ 1 9 ] ) ;$ f d i s p l a y ( f i l eD , ” $r20 = 0x%h” , proc datapath . RegFi le .mem[ 2 0 ] ) ;$ f d i s p l a y ( f i l eD , ” $r21 = 0x%h” , proc datapath . RegFi le .mem[ 2 1 ] ) ;$ f d i s p l a y ( f i l eD , ” $r22 = 0x%h” , proc datapath . RegFi le .mem[ 2 2 ] ) ;$ f d i s p l a y ( f i l eD , ” $r23 = 0x%h” , proc datapath . RegFi le .mem[ 2 3 ] ) ;$ f d i s p l a y ( f i l eD , ” $r24 = 0x%h” , proc datapath . RegFi le .mem[ 2 4 ] ) ;$ f d i s p l a y ( f i l eD , ” $r25 = 0x%h” , proc datapath . RegFi le .mem[ 2 5 ] ) ;$ f d i s p l a y ( f i l eD , ” $r26 = 0x%h” , proc datapath . RegFi le .mem[ 2 6 ] ) ;$ f d i s p l a y ( f i l eD , ” $r27 = 0x%h” , proc datapath . RegFi le .mem[ 2 7 ] ) ;$ f d i s p l a y ( f i l eD , ” $r28 = 0x%h” , proc datapath . RegFi le .mem[ 2 8 ] ) ;$ f d i s p l a y ( f i l eD , ” $r29 = 0x%h” , proc datapath . RegFi le .mem[ 2 9 ] ) ;$ f d i s p l a y ( f i l eD , ” $r30 = 0x%h” , proc datapath . RegFi le .mem[ 3 0 ] ) ;$ f d i s p l a y ( f i l eD , ” $r31 = 0x%h” , proc datapath . RegFi le .mem[ 3 1 ] ) ; ∗/

// $ f c l o s e ( f i l eD ) ;// $ f c l o s e ( da . t r a c eF i l e ) ;

//Recognize s imu la t ion h a l t$ f i n i s h ;

endend

// s yn t h e s i s t r an s l a t e onendmodule

module datapath (ALU OP, ALU SRCB, clk , dcache miss , d i v s t a r t , ext op ,g l o b a l s t a l l , i cache mi s s , INST MEMDATA, JUMP OP, l a t ch i d , mem read ,mem to reg , mem write , mfhi lo , mu l t s ta r t , RD DATA MEM OUT, REG DST,r eg wr i t e , r s t , s h i f t , SHIFT OP , SMNT IN , use r s , u s e r t , branch miss ,DMEMADDR, DMEM DIN, f lu sh , i f i d s t a l l , INSTRUCTION, INST MEMADDR,memenable ex1 , memwrite ex1 , p i p e l i n e s t a l l ) ;

input [ 5 : 0 ] ALU OP;input [ 2 : 0 ] ALU SRCB;input c l k ;input dcache miss ;input d i v s t a r t ;

20

input ext op ;input g l o b a l s t a l l ;input i c a che m i s s ;input [ 3 1 : 0 ] INST MEMDATA;input [ 2 : 0 ] JUMP OP;input l a t c h i d ;input mem read ;input mem to reg ;input mem write ;input mfhi lo ;input mul t s t a r t ;input [ 3 1 : 0 ] RD DATA MEM OUT;input [ 4 : 0 ] REG DST;input r e g w r i t e ;input r s t ;input s h i f t ;input [ 1 : 0 ] SHIFT OP ;input [ 4 : 0 ] SMNT IN;input u s e r s ;input u s e r t ;

output branch miss ;output [ 3 1 : 0 ] DMEMADDR;output [ 3 1 : 0 ] DMEM DIN;output f l u s h ;output i f i d s t a l l ;output [ 3 1 : 0 ] INSTRUCTION;output [ 3 1 : 0 ] INST MEMADDR;output memenable ex1 ;output memwrite ex1 ;output p i p e l i n e s t a l l ;

wire fwx1 bubble ;wire fwx1 keepfwdvals ;wire f w x 1 s t a l l ;wire [ 5 : 0 ] iALUOP;wire id fw bubble ;wire i d f w s t a l l ;wire i f i d b ubb l e ;wire memread ex1 ;wire memread ex2 ;wire memread mem2 ;wire memread mem3 ;wire memtoreg ex2 ;wire memwb bubble ;wire memwrite ex2 ;wire mem to reg mem2 ;wire mem to reg mem3 ;wire [ 6 3 : 0 ] MULTANSWER;wire mult done ;wire [ 3 1 : 0 ] PC PLUS 8 ;wire [ 3 1 : 0 ] RD DATA EX2;wire [ 3 1 : 0 ] RD DATA MEM2;wire [ 3 1 : 0 ] RD DATA MEM3;wire [ 3 1 : 0 ] RD DATA WR;wire [ 4 : 0 ] REGDST EX1;wire [ 4 : 0 ] REGDST EX2;wire [ 4 : 0 ] REGDST FW;wire [ 4 : 0 ] REGDST MEM2;wire [ 4 : 0 ] REGDST MEM3;wire [ 4 : 0 ] REGDST WR;wire r e gwr i t e ex1 ;wire r e gwr i t e ex2 ;wire r egwr i t e fw ;wire regwrite mem2 ;wire regwrite mem3 ;wire r egwr i t e wr ;wire s h i f t e r e x 1 ;wire s h i f t e r e x 2 ;

21

wire XLXN 125 ;wire XLXN 126 ;wire XLXN 127 ;wire XLXN 137 ;wire XLXN 149 ;wire [ 4 : 0 ] XLXN 152 ;wire [ 3 1 : 0 ] XLXN 205 ;wire [ 3 1 : 0 ] XLXN 206 ;wire [ 4 : 0 ] XLXN 209 ;wire XLXN 219 ;wire XLXN 222 ;wire [ 3 1 : 0 ] XLXN 225 ;wire [ 3 1 : 0 ] XLXN 239 ;wire [ 3 1 : 0 ] XLXN 328 ;wire [ 3 1 : 0 ] XLXN 330 ;wire XLXN 335 ;wire [ 4 : 0 ] XLXN 363 ;wire [ 4 : 0 ] XLXN 364 ;wire [ 3 1 : 0 ] XLXN 379 ;wire [ 3 1 : 0 ] XLXN 380 ;wire [ 3 1 : 0 ] XLXN 387 ;wire XLXN 410 ;wire XLXN 411 ;wire XLXN 412 ;wire XLXN 413 ;wire [ 3 1 : 0 ] XLXN 414 ;wire [ 3 1 : 0 ] XLXN 416 ;wire [ 3 1 : 0 ] XLXN 417 ;wire [ 3 1 : 0 ] XLXN 420 ;wire [ 3 1 : 0 ] XLXN 421 ;wire [ 2 : 0 ] XLXN 430 ;wire XLXN 440 ;wire XLXN 441 ;wire [ 3 1 : 0 ] XLXN 444 ;wire [ 3 1 : 0 ] XLXN 450 ;wire XLXN 469 ;wire XLXN 482 ;wire XLXN 483 ;wire XLXN 484 ;wire [ 5 : 0 ] XLXN 486 ;wire [ 1 5 : 0 ] XLXN 489 ;wire [ 3 1 : 0 ] XLXN 518 ;wire [ 2 5 : 0 ] XLXN 519 ;wire [ 1 : 0 ] XLXN 523 ;wire [ 1 : 0 ] XLXN 530 ;wire [ 3 1 : 0 ] XLXN 536 ;wire [ 3 1 : 0 ] XLXN 551 ;wire [ 3 1 : 0 ] XLXN 555 ;wire XLXN 556 ;wire XLXN 557 ;wire [ 3 1 : 0 ] XLXN 581 ;wire [ 3 1 : 0 ] XLXN 598 ;wire XLXN 608 ;wire XLXN 609 ;wire XLXN 611 ;wire [ 3 1 : 0 ] XLXN 612 ;wire [ 3 1 : 0 ] XLXN 613 ;wire [ 2 : 0 ] XLXN 615 ;wire [ 2 : 0 ] XLXN 616 ;wire [ 2 : 0 ] XLXN 620 ;wire [ 2 : 0 ] XLXN 621 ;wire [ 3 1 : 0 ] XLXN 622 ;wire [ 3 1 : 0 ] XLXN 623 ;wire XLXN 624 ;wire XLXN 626 ;wire [ 1 : 0 ] XLXN 658 ;wire [ 1 : 0 ] XLXN 659 ;wire x 1 x 2 s t a l l ;

22

wire x2mem stal l ;

extend Extender ( . DIN(XLXN 489 [ 1 5 : 0 ] ) , . s i gn ex tend ( ext op ) ,.DOUT(XLXN 387 [ 3 1 : 0 ] ) ) ;

ForwardingModule2 ForwardingModule ( . mfh i lo ( mfh i lo ) , . mult done ( mult done ) ,.RD FROM EX1(REGDST FW[ 4 : 0 ] ) , .RD FROM EX2(REGDST EX1 [ 4 : 0 ] ) ,.RD FROM MEM2(REGDST EX2 [ 4 : 0 ] ) , .RD FROM MEM3(REGDST MEM2[ 4 : 0 ] ) ,.RDFROM WR(REGDST MEM3[ 4 : 0 ] ) , . read mem from ex2 ( memread ex1 ) ,. read mem from mem2 ( memread ex2 ) , . read mem from mem3 (memread mem2) ,.RS(XLXN 363 [ 4 : 0 ] ) , .RT(XLXN 364 [ 4 : 0 ] ) , . s h i f t e x 2 ( s h i f t e r e x 1 ) ,. u s e r s ( u s e r s ) , . u s e r t ( u s e r t ) , . write mem ( mem write ) ,. wr from ex1 ( r egwr i t e fw ) , . wr from ex2 ( r egwr i t e ex1 ) ,. wr from mem2 ( r egwr i t e ex2 ) , . wr from mem3 ( regwrite mem2 ) ,. wr from wr ( regwrite mem3 ) , .FW OP RS(XLXN 615 [ 2 : 0 ] ) ,.FW OP RT(XLXN 616 [ 2 : 0 ] ) , . mem forward mem2 (XLXN 608) ,. mem2 forward ex1 (XLXN 411) , . mem2 forward ex2 (XLXN 410) ,. s t a l l (XLXN 469) ) ;

fowardreg ForwardingRegs ( . c l k ( c l k ) , . f r e g s t a l l (XLXN 556) ,. i RD DATA EX1(DMEMADDR[ 3 1 : 0 ] ) , . i RD DATA EX2(RD DATA EX2 [ 3 1 : 0 ] ) ,. i RD DATA MEM2(RD DATA MEM2[ 3 1 : 0 ] ) ,. i RD DATA MEM3(RD DATA MEM3[ 3 1 : 0 ] ) , . r s t ( r s t ) ,. o RD DATA EX2(XLXN 444 [ 3 1 : 0 ] ) , . o RD DATA MEM2(XLXN 598 [ 3 1 : 0 ] ) ,.o RD DATA MEM3(XLXN 551 [ 3 1 : 0 ] ) , . o RD DATA WR(XLXN 623 [ 3 1 : 0 ] ) ) ;

i n s t ruc t i on modu l e InstrMod ( .BRANCH OFFSET(XLXN 489 [ 1 5 : 0 ] ) , . c l k ( c l k ) ,. eq (XLXN 482) , . id fw bubble ( id fw bubble ) , . i d f w s t a l l ( i d f w s t a l l ) ,.INST MEMDATA(INST MEMDATA[ 3 1 : 0 ] ) , .JUMP ADDR(XLXN 519 [ 2 5 : 0 ] ) ,.JUMP OP(JUMP OP[ 2 : 0 ] ) , . JUMP OP FAST(XLXN 658 [ 1 : 0 ] ) ,.JUMP REG ADDR(XLXN 205 [ 3 1 : 0 ] ) , . l t z (XLXN 483) , . r s t ( r s t ) ,. s t a l l ( i f i d s t a l l ) , . b ranch in fo rward (XLXN 557) ,. b ranch mispred i c t ( branch miss ) , . INSTRUCTION(XLXN 518 [ 3 1 : 0 ] ) ,.INST MEMADDR(INST MEMADDR[ 3 1 : 0 ] ) , . PC PLUS 8(PC PLUS 8 [ 3 1 : 0 ] ) ) ;

m u l t i p l i e r c i r c u i t Mu l t i p l i e r ( . c l k ( c l k ) , . d i v i d e (XLXN 126) ,.MULTIPLICAND(XLXN 416 [ 3 1 : 0 ] ) , .MULTIPLIER(XLXN 420 [ 3 1 : 0 ] ) ,. r s t (XLXN 125) , .ANSWER(MULTANSWER[ 6 3 : 0 ] ) , . done ( mult done ) ) ;

m32x2 MuxALUOut ( .A(XLXN 450 [ 3 1 : 0 ] ) , .B(XLXN 239 [ 3 1 : 0 ] ) , . SEL( s h i f t e r e x 2 ) ,.DOUT(RD DATA EX2 [ 3 1 : 0 ] ) ) ;

m32x5 MuxALUSrcB ( .A(XLXN 420 [ 3 1 : 0 ] ) , .B(XLXN 421 [ 3 1 : 0 ] ) ,.C(XLXN 555 [ 3 1 : 0 ] ) , .D(MULTANSWER[ 6 3 : 3 2 ] ) , .E(MULTANSWER[ 3 1 : 0 ] ) ,. SEL(XLXN 430 [ 2 : 0 ] ) , .DOUT(XLXN 536 [ 3 1 : 0 ] ) ) ;

m32x2 MuxMemForward1 ( .A(XLXN 225 [ 3 1 : 0 ] ) , .B(RD DATA MEM3[ 3 1 : 0 ] ) ,. SEL(XLXN 484) , .DOUT(XLXN 330 [ 3 1 : 0 ] ) ) ;

m32x2 MuxMemForward2 ( .A(XLXN 328 [ 3 1 : 0 ] ) , .B(RD DATA MEM3[ 3 1 : 0 ] ) ,. SEL(XLXN 335) , .DOUT(XLXN 613 [ 3 1 : 0 ] ) ) ;

m32x2 MuxMemToReg ( .A(XLXN 581 [ 3 1 : 0 ] ) , .B(RD DATA MEM OUT[ 3 1 : 0 ] ) ,. SEL(mem to reg mem3 ) , .DOUT(RD DATA MEM3[ 3 1 : 0 ] ) ) ;

a lu myALU ( .A(XLXN 205 [ 3 1 : 0 ] ) , .ALUOP(iALUOP [ 5 : 0 ] ) , .B(XLXN 206 [ 3 1 : 0 ] ) ,. c l k ( c l k ) , .ALU OUT(DMEMADDR[ 3 1 : 0 ] ) , .ALU REG OUT() ) ;

s h i f t e r myShi fter ( . c l k ( c l k ) , . DIN(XLXN 206 [ 3 1 : 0 ] ) ,. SHIFT OP(XLXN 523 [ 1 : 0 ] ) , .SMNT(XLXN 209 [ 4 : 0 ] ) , .DOUT(XLXN 239 [ 3 1 : 0 ] ) ) ;

regArray RegFi le ( . c l k ( c l k ) , . DIN(RD DATA MEM3[ 3 1 : 0 ] ) ,.RD(REGDST MEM3[ 4 : 0 ] ) , .RS(XLXN 363 [ 4 : 0 ] ) , . r s t ( r s t ) ,.RT(XLXN 364 [ 4 : 0 ] ) , . w en ( regwrite mem3 ) , .DOUTS(XLXN 379 [ 3 1 : 0 ] ) ,.DOUTT(XLXN 380 [ 3 1 : 0 ] ) ) ;

CRegsFWX1 RegsFWX1 ( . ALUOP IN(XLXN 486 [ 5 : 0 ] ) ,.ALUSRCBDATA IN(XLXN 536 [ 3 1 : 0 ] ) , . bubble ( fwx1 bubble ) , . c l k ( c l k ) ,. keepfwdvals ( fwx1 keepfwdvals ) , . memforwardex1 in (XLXN 412) ,. memforwardex2 in (XLXN 413) , . memforwardmem2 in (XLXN 609) ,. memread in (XLXN 137) , . memtoreg in (XLXN 149) , . memwrite in (XLXN 440) ,.REGDST IN(REGDST FW[ 4 : 0 ] ) , . r e gw r i t e i n ( r egwr i t e fw ) , . r s t ( r s t ) ,. SDATA IN(XLXN 416 [ 3 1 : 0 ] ) , . SHAMT IN(XLXN 152 [ 4 : 0 ] ) ,. s h i f t e r i n (XLXN 441) , . SHIFTOP IN(XLXN 530 [ 1 : 0 ] ) , . s t a l l ( f w x 1 s t a l l ) ,.TDATA IN(XLXN 420 [ 3 1 : 0 ] ) , .ALUOP(iALUOP [ 5 : 0 ] ) ,.ALUSRCBDATA(XLXN 206 [ 3 1 : 0 ] ) , . memforwardex1 (XLXN 484) ,. memforwardex2 (XLXN 219) , . memforwardmem2(XLXN 624) ,. memread( memread ex1 ) , . memtoreg (XLXN 222) , . memwrite ( memwrite ex1 ) ,.REGDST(REGDST EX1 [ 4 : 0 ] ) , . r e gwr i t e ( r e gwr i t e ex1 ) ,.SDATA(XLXN 205 [ 3 1 : 0 ] ) , .SHAMT(XLXN 209 [ 4 : 0 ] ) , . s h i f t e r ( s h i f t e r e x 1 ) ,.SHIFTOP(XLXN 523 [ 1 : 0 ] ) , .TDATA(XLXN 225 [ 3 1 : 0 ] ) ) ;

23

CRegsIDFW RegsIDFW ( . ALUOP IN(ALU OP [ 5 : 0 ] ) , .ALUSRCB IN(ALU SRCB [ 2 : 0 ] ) ,. bubble ( id fw bubble ) , . c l k ( c l k ) , . d i v s t a r t i n ( d i v s t a r t ) ,.EXTENDDATA IN(XLXN 387 [ 3 1 : 0 ] ) , .FWOPRS IN(XLXN 615 [ 2 : 0 ] ) ,.FWOPRT IN(XLXN 616 [ 2 : 0 ] ) , . memforwardex1 in (XLXN 411) ,. memforwardex2 in (XLXN 410) , . memforwardmem2 in (XLXN 608) ,. memread in (mem read ) , . memtoreg in ( mem to reg ) ,. memwrite in ( mem write ) , . mu l t s t a r t i n ( mu l t s t a r t ) ,. PC PLUS 8 IN(PC PLUS 8 [ 3 1 : 0 ] ) , .REGDST IN(REG DST [ 4 : 0 ] ) ,. r e gw r i t e i n ( r e g w r i t e ) , . r s t ( r s t ) , . RS IN(XLXN 363 [ 4 : 0 ] ) ,. RT IN(XLXN 364 [ 4 : 0 ] ) , . SDATA IN(XLXN 379 [ 3 1 : 0 ] ) ,.SHAMT IN(SMNT IN [ 4 : 0 ] ) , . s h i f t e r i n ( s h i f t ) ,. SHIFTOP IN(SHIFT OP [ 1 : 0 ] ) , . s t a l l ( i d f w s t a l l ) ,.TDATA IN(XLXN 380 [ 3 1 : 0 ] ) , .ALUOP(XLXN 486 [ 5 : 0 ] ) ,.ALUSRCB(XLXN 430 [ 2 : 0 ] ) , . d i v s t a r t (XLXN 126) ,.EXTENDDATA(XLXN 421 [ 3 1 : 0 ] ) , .FWOPRS(XLXN 620 [ 2 : 0 ] ) ,.FWOPRT(XLXN 621 [ 2 : 0 ] ) , . memforwardex1 (XLXN 412) ,. memforwardex2 (XLXN 413) , . memforwardmem2(XLXN 609) ,. memread(XLXN 137) , . memtoreg (XLXN 149) , . memwrite (XLXN 440) ,. mu l t s ta r t (XLXN 127) , . PC PLUS 8(XLXN 555 [ 3 1 : 0 ] ) ,.REGDST(REGDST FW[ 4 : 0 ] ) , . r e gwr i t e ( r egwr i t e fw ) , .RS( ) , .RT( ) ,.SDATA(XLXN 414 [ 3 1 : 0 ] ) , .SHAMT(XLXN 152 [ 4 : 0 ] ) , . s h i f t e r (XLXN 441) ,.SHIFTOP(XLXN 530 [ 1 : 0 ] ) , .TDATA(XLXN 417 [ 3 1 : 0 ] ) ) ;

CRegsIFID RegsIFID ( . bubble ( i f i d b ubb l e ) , . c l k ( c l k ) ,. INSTR IN(XLXN 518 [ 3 1 : 0 ] ) , . J OP FAST IN(XLXN 659 [ 1 : 0 ] ) ,. l a t c h i d ( l a t c h i d ) , . r s t ( r s t ) , . s t a l l ( i f i d s t a l l ) ,. IMM16(XLXN 489 [ 1 5 : 0 ] ) , . INSTR OUT(INSTRUCTION[ 3 1 : 0 ] ) ,.JUMPADDR(XLXN 519 [ 2 5 : 0 ] ) , . J OP FAST(XLXN 658 [ 1 : 0 ] ) ,.RS(XLXN 363 [ 4 : 0 ] ) , .RT(XLXN 364 [ 4 : 0 ] ) , .SHAMT() ) ;

CRegsMEMWB RegsMEMWB ( . bubble (memwb bubble ) , .RDDATA IN(RD DATA MEM3[ 3 1 : 0 ] ) ,.REGDST IN(REGDST MEM2[ 4 : 0 ] ) , . r e gw r i t e i n ( ) ,.RDDATA(RD DATA WR[ 3 1 : 0 ] ) , .REGDST(REGDST WR[ 4 : 0 ] ) ,. r e gwr i t e ( r egwr i t e wr ) , . r e gwr i t e t r an spa r en t ( ) ) ;

CRegsX1X2 RegsX1X2 ( .ALUOUT IN(DMEMADDR[ 3 1 : 0 ] ) , . c l k ( c l k ) ,. memforwardex2 in (XLXN 219) , . memforwardmem2 in (XLXN 624) ,. memread in ( memread ex1 ) , . memtoreg in (XLXN 222) ,. memwrite in ( memwrite ex1 ) , .REGDST IN(REGDST EX1 [ 4 : 0 ] ) ,. r e gw r i t e i n ( r e gwr i t e ex1 ) , . r s t ( r s t ) , . s h i f t e r i n ( s h i f t e r e x 1 ) ,. s t a l l ( x 1 x 2 s t a l l ) , .TDATA IN(XLXN 330 [ 3 1 : 0 ] ) ,.ALUOUT(XLXN 450 [ 3 1 : 0 ] ) , . memforwardex2 (XLXN 335) ,. memforwardmem2(XLXN 626) , . memread( memread ex2 ) ,. memtoreg ( memtoreg ex2 ) , . memwrite ( memwrite ex2 ) ,.REGDST(REGDST EX2 [ 4 : 0 ] ) , . r e gwr i t e ( r e gwr i t e ex2 ) ,. s h i f t e r ( s h i f t e r e x 2 ) , .TDATA(XLXN 328 [ 3 1 : 0 ] ) ) ;

CRegsX2MEM RegsX2MEM ( .ALUOUT IN(RD DATA EX2 [ 3 1 : 0 ] ) , . c l k ( c l k ) ,. memforwardmem2 in (XLXN 626) , . memread in ( memread ex2 ) ,. memtoreg in ( memtoreg ex2 ) , .REGDST IN(REGDST EX2 [ 4 : 0 ] ) ,. r e gw r i t e i n ( r e gwr i t e ex2 ) , . r s t ( r s t ) , . RT DATA IN(XLXN 613 [ 3 1 : 0 ] ) ,. s t a l l ( x2mem stal l ) , .ALUOUT(RD DATA MEM2[ 3 1 : 0 ] ) ,. memforwardmem2(XLXN 611) , . memread(memread mem2) ,. memtoreg (mem to reg mem2 ) , .REGDST(REGDST MEM2[ 4 : 0 ] ) ,. r e gwr i t e ( regwrite mem2 ) , .RT DATA OUT(XLXN 612 [ 3 1 : 0 ] ) ) ;

S t a l l L o g i c S t a l l L o g i c ( . b ranch in fo rward (XLXN 557) ,. b ranch mispred i c t ( branch miss ) , . dcache miss ( dcache miss ) ,. g l o b a l s t a l l ( g l o b a l s t a l l ) , . h a z a r d s t a l l (XLXN 469) ,. i c a che m i s s ( i c a che m i s s ) , . e x 1 e x 2 s t a l l ( x 1 x 2 s t a l l ) ,. ex2mem2 stal l ( x2mem stal l ) , . fwex1 bubble ( fwx1 bubble ) ,. f w e x 1 s t a l l ( f w x 1 s t a l l ) , . f r e g s t a l l (XLXN 556) ,. id fw bubble ( id fw bubble ) , . i d f w s t a l l ( i d f w s t a l l ) ,. i f i d b ubb l e ( i f i d b ubb l e ) , . i f i d s t a l l ( i f i d s t a l l ) ,. p i p e l i n e s t a l l ( p i p e l i n e s t a l l ) ) ;

FastComparator XLXI 14 ( . RS(XLXN 205 [ 3 1 : 0 ] ) , .RT(XLXN 225 [ 3 1 : 0 ] ) ,. eq (XLXN 482) , . l t z (XLXN 483) ) ;

or2 XLXI 36 ( . I1 (XLXN 127) , . I2 (XLXN 126) , .O(XLXN 125) ) ;or2 XLXI 56 ( . I1 ( memwrite ex1 ) , . I2 ( memread ex1 ) , .O( memenable ex1 ) ) ;and2 XLXI 57 ( . I1 ( memwrite ex1 ) , . I2 ( memread ex1 ) , .O( f l u s h ) ) ;m32x2 XLXI 63 ( .A(XLXN 551 [ 3 1 : 0 ] ) , .B(RD DATA MEM OUT[ 3 1 : 0 ] ) ,

. SEL(mem to reg mem3 ) , .DOUT(XLXN 622 [ 3 1 : 0 ] ) ) ;CRegsX2MEM XLXI 64 ( .ALUOUT IN(RD DATA MEM2[ 3 1 : 0 ] ) , . c l k ( c l k ) ,

24

. memforwardmem2 in ( ) , . memread in (memread mem2) ,

. memtoreg in (mem to reg mem2 ) , .REGDST IN(REGDST MEM2[ 4 : 0 ] ) ,

. r e gw r i t e i n ( regwrite mem2 ) , . r s t ( r s t ) , . RT DATA IN( ) ,

. s t a l l ( x2mem stal l ) , .ALUOUT(XLXN 581 [ 3 1 : 0 ] ) , . memforwardmem2 ( ) ,

. memread(memread mem3) , . memtoreg (mem to reg mem3 ) ,

.REGDST(REGDST MEM3[ 4 : 0 ] ) , . r e gwr i t e ( regwrite mem3 ) , .RT DATA OUT() ) ;m32x5 XLXI 68 ( .A(XLXN 414 [ 3 1 : 0 ] ) , .B(XLXN 444 [ 3 1 : 0 ] ) , .C(XLXN 598 [ 3 1 : 0 ] ) ,

.D(XLXN 622 [ 3 1 : 0 ] ) , .E(XLXN 623 [ 3 1 : 0 ] ) , . SEL(XLXN 620 [ 2 : 0 ] ) ,

.DOUT(XLXN 416 [ 3 1 : 0 ] ) ) ;m32x5 XLXI 70 ( .A(XLXN 417 [ 3 1 : 0 ] ) , .B(XLXN 444 [ 3 1 : 0 ] ) , .C(XLXN 598 [ 3 1 : 0 ] ) ,

.D(XLXN 622 [ 3 1 : 0 ] ) , .E(XLXN 623 [ 3 1 : 0 ] ) , . SEL(XLXN 621 [ 2 : 0 ] ) ,

.DOUT(XLXN 420 [ 3 1 : 0 ] ) ) ;m32x2 XLXI 71 ( .A(XLXN 612 [ 3 1 : 0 ] ) , .B(RD DATA MEM3[ 3 1 : 0 ] ) , . SEL(XLXN 611) ,

.DOUT(DMEM DIN[ 3 1 : 0 ] ) ) ;fa s t jbDecode XLXI 72 ( . INSTRUCTION(XLXN 518 [ 3 1 : 0 ] ) , . JB TYPE(XLXN 659 [ 1 : 0 ] ) ) ;

endmodule

A.3 Reg File

//$Header : U:\\CVSLab3\\CVSLab3/ lab6b /regArray . v , v 1 .1 . 1 . 1 2004/05/16 04 :25 :45 cs152−a j Exp$

‘ t ime s ca l e 1 ns /10 ps

module regArray ( c lk , r s t , RS , RT, RD, DOUTS, DOUTT, DIN , w en ) ;input c lk , r s t ;input w en ;input [ 4 : 0 ] RS , RT, RD;

output [ 3 1 : 0 ] DOUTS, DOUTT;input [ 3 1 : 0 ] DIN ;

pseudoreg RSS(.A(RD) ,.CLK( c l k ) ,.D(DIN) ,.WE( ( r s t | (RD == 0) ) ? 1 ’ b0 : w en ) ,.DPRA(RS) ,.DPO(DOUTS) ,.SPO( ) ) ;

pseudoreg RTT(.A(RD) ,.CLK( c l k ) ,.D(DIN) ,.WE( ( r s t | (RD == 0) ) ? 1 ’ b0 : w en ) ,.DPRA(RT) ,.DPO(DOUTT) ,.SPO( ) ) ;

/∗always@ ( posedge c l k )

i f ( r s t )beg in

mem[0] <= 32 ’ b0 ;mem[1] <= 32 ’ b0 ;mem[2] <= 32 ’ b0 ;mem[3] <= 32 ’ b0 ;mem[4] <= 32 ’ b0 ;mem[5] <= 32 ’ b0 ;mem[6] <= 32 ’ b0 ;mem[7] <= 32 ’ b0 ;mem[8] <= 32 ’ b0 ;mem[9] <= 32 ’ b0 ;mem[10] <= 32 ’ b0 ;mem[11] <= 32 ’ b0 ;mem[12] <= 32 ’ b0 ;mem[13] <= 32 ’ b0 ;

25

mem[14] <= 32 ’ b0 ;mem[15] <= 32 ’ b0 ;mem[16] <= 32 ’ b0 ;mem[17] <= 32 ’ b0 ;mem[18] <= 32 ’ b0 ;mem[19] <= 32 ’ b0 ;mem[20] <= 32 ’ b0 ;mem[21] <= 32 ’ b0 ;mem[22] <= 32 ’ b0 ;mem[23] <= 32 ’ b0 ;mem[24] <= 32 ’ b0 ;mem[25] <= 32 ’ b0 ;mem[26] <= 32 ’ b0 ;mem[27] <= 32 ’ b0 ;mem[28] <= 32 ’ b0 ;mem[29] <= 32 ’ b0 ;mem[30] <= 32 ’ b0 ;mem[31] <= 32 ’ b0 ;

ende l s e i f ( w en && RD != 5 ’ b0 )mem[RD] <= DIN;

∗/endmodule

A.4 ALU

// $Header : v :\\CVSLab3/ lab6 / a lu . v , v 1 .2 2004/05/07 01 :38 :23 cs152−ah Exp $// $Author : cs152−ah $// $Date

‘ t ime s ca l e 1 ns /10 ps

‘ include ”ALUEncoding . v”

module a lu ( c lk , A, B, ALUOP, ALU OUT, ALU REG OUT) ;input c l k ;

input [ 3 1 : 0 ] A,B;input [ 5 : 0 ] ALUOP;

output [ 3 1 : 0 ] ALU OUT;output [ 3 1 : 0 ] ALU REG OUT;

wire [ 3 1 : 0 ] asuOut ;wire cout , neg , ovf ;

wire [ 3 1 : 0 ] s l tOut ;wire [ 3 1 : 0 ] andOut ;wire [ 3 1 : 0 ] orOut ;wire [ 3 1 : 0 ] xorOut ;

//Decode ALUOPwire s l t = ALUOP[ 5 ] ;wire add = ALUOP[ 4 ] ;wire bypass = ALUOP[ 3 ] ;wire [ 2 : 0 ] muxsel = ALUOP[ 2 : 0 ] ;

//asuOut == A−B or A+B or Baddsubunit asu ( .A(A) , .B(B) ,

.BYPASS( bypass ) , .ADD(add ) ,

.C OUT( cout ) ,

. S ( asuOut ) ) ;

// s l tOu t == signed A<B or unsigned A<Bassign s l tOut = {31 ’ b0 , ( s l t && (A[ 3 1 ] ˆ B[ 3 1 ] ) ) ? cout : ˜ cout } ;

// l o g i c a l opera t ionsassign andOut = A&B;

26

assign orOut = A |B;assign xorOut = AˆB;

mux32 5 se lOut ( .MA( asuOut ) ,.MB( s l tOut ) ,.MC(andOut ) ,.MD( orOut ) ,.ME( xorOut ) ,. S ( muxsel ) , // binary s e l e c t i o n.O(ALU OUT) , //un−r e g i s t e r e d output.Q(ALU REG OUT) , // r e g i s t e r e d output.CLK( c l k ) ) ;

endmodule

//$Header : v :\\CVSLab3/ lab6 / s h i f t e r . v , v 1 .4 2004/05/09 21 :55 :45 cs152−a i Exp $

‘ t ime s ca l e 1 ns /10 ps

‘ include ”ALUENCODING. v”

module s h i f t e r ( c lk , DIN , DOUT, SMNT, SHIFT OP) ;input c l k ;input [ 3 1 : 0 ] DIN ;output [ 3 1 : 0 ] DOUT;

input [ 4 : 0 ] SMNT;input [ 1 : 0 ] SHIFT OP ;

reg [ 1 : 0 ] pSHIFT OP , pSMNT;reg [ 3 1 : 0 ] pSRA, pSRL , pSLL ;always@ (posedge c l k )

beginpSRA <= $s igned (DIN) >>> {SMNT[ 4 : 2 ] , 2 ’ b0 } ;pSRL <= DIN >> {SMNT[ 4 : 2 ] , 2 ’ b0 } ;pSLL <= DIN << {SMNT[ 4 : 2 ] , 2 ’ b0 } ;pSHIFT OP <= SHIFT OP ;pSMNT <= SMNT[ 1 : 0 ] ;

end

reg [ 3 1 : 0 ] DOUT;always@ (∗ )

case (pSHIFT OP)‘ALU SRA : DOUT = $s igned (pSRA) >>> pSMNT;‘ALU SRL : DOUT = pSRL >> pSMNT;‘ALU SLL : DOUT = pSLL << pSMNT;default : DOUT = 32 ’hXXXX XXXX;

endcaseendmodule

A.5 Controller

//ALU SRCB Encoding

‘ d e f i n e ASB REG B OUT 3 ’ b000‘ d e f i n e ASB EXT OUT 3 ’ b001‘ d e f i n e ASB PC 8 3 ’ b010‘ d e f i n e ASB HI 3 ’ b011‘ d e f i n e ASB LO 3 ’ b100

//Operation Encodings f o r a lu module and s h i f t e r

// s h i f t opera t ion‘ d e f i n e ALU SLL 2 ’ b00‘ d e f i n e ALU SRL 2 ’ b10‘ d e f i n e ALU SRA 2 ’ b01

// a lu operat ion {SLT or SLTU, ADD? , BYPASS ? , ALUOUT MUX SEL}

27

‘ d e f i n e ALU ADD 6 ’ bx 11 000‘ d e f i n e ALU SUB 6 ’ bx 01 000‘ d e f i n e ALU SELB 6 ’ bx 00 000‘ d e f i n e ALU SLT 6 ’ b1 01 001‘ d e f i n e ALU SLTU 6 ’ b0 01 001‘ d e f i n e ALU AND 6 ’ bx 00 010‘ d e f i n e ALU OR 6 ’ bx 00 011‘ d e f i n e ALU XOR 6 ’ bx 00 100

// $Header : v :\\CVSLab3/ lab6 /opcodes . v , v 1 .3 2004/05/10 00 :31 :23 cs152−a j Exp $// $Author : cs152−a j $// $Date : 2004/05/10 00 :31 :23 $‘ include ”ALUEncoding . v”‘ include ”JBEncoding . v”‘ include ”ALUSRCEncoding . v”

//OPCODES‘ d e f i n e RTYPE 6 ’ b000000‘ d e f i n e BSPECIAL 6 ’ b000001‘ d e f i n e BEQ 6 ’ b000100‘ d e f i n e BNE 6 ’ d5‘ d e f i n e J 6 ’ d2‘ d e f i n e JAL 6 ’ d3‘ d e f i n e LW 6 ’ b100011‘ d e f i n e SW 6 ’ b101011‘ d e f i n e LUI 6 ’ b001111‘ d e f i n e ADDIU 6 ’ b001001‘ d e f i n e ORI 6 ’ d13‘ d e f i n e ANDI 6 ’ d12‘ d e f i n e XORI 6 ’ d14‘ d e f i n e SLTI 6 ’ d10‘ d e f i n e SLTUI 6 ’ d11‘ d e f i n e FLUSH 6 ’ d20

//FUNCTS ( fo r R−Type In s t r u c t i on s )‘ d e f i n e ADDU 6 ’ b100001‘ d e f i n e SUBU 6 ’ b100011‘ d e f i n e SLL 6 ’ b000000‘ d e f i n e SRL 6 ’ b000010‘ d e f i n e SRA 6 ’ b000011‘ d e f i n e JR 6 ’ b001000‘ d e f i n e SLT 6 ’ b101010‘ d e f i n e SLTU 6 ’ d43‘ d e f i n e MULTU 6 ’ d25‘ d e f i n e DIVU 6 ’ d27‘ d e f i n e AND 6 ’ d36‘ d e f i n e OR 6 ’ d37‘ d e f i n e XOR 6 ’ d38‘ d e f i n e MFHI 6 ’ d16‘ d e f i n e MFLO 6 ’ d18‘ d e f i n e BREAK 6 ’ d13

//RT Encodings f o r b l t z and bgez‘ d e f i n e BLTZ 5 ’ b00000‘ d e f i n e BGEZ 5 ’ b00001

//EXPECTED CONTROLLER OUTPUT BIT PATTERNS//Ordering : {ALU OP, SHIFT OP , JB TYPE, ALU SRCB,// ext op , mem write , mem read , mem to reg , r eg wr i t e , use rs , u se r t , mfhi lo ,

mu l t s t a r t , d i v s t a r t , s h i f t }//Total : 2 9 b i t s// REG DST[ 4 : 0 ] not inc luded s ince i t i s p o s s i b l y dependent on RD, RT f i e l d va lue s from

in s t r u c t i on

‘ d e f i n e ADDU C { ‘ALU ADD, 2 ’bx , ‘JB NO , ‘ASB REG B OUT, 11 ’ bx0001110000}

28

‘ d e f i n e ADDIU C { ‘ALU ADD, 2 ’bx , ‘JB NO , ‘ASB EXT OUT, 11 ’ b10001100000}

‘ d e f i n e SUBU C { ‘ALU SUB, 2 ’bx , ‘JB NO , ‘ASB REG B OUT, 11 ’ bx0001110000}

‘ d e f i n e OR C { ‘ALU OR, 2 ’bx , ‘JB NO , ‘ASB REG B OUT, 11 ’ bx0001110000}

‘ d e f i n e ORI C { ‘ALU OR, 2 ’bx , ‘JB NO , ‘ASB EXT OUT, 11 ’ b00001100000}

‘ d e f i n e AND C { ‘ALU AND, 2 ’bx , ‘JB NO , ‘ASB REG B OUT, 11 ’ bx0001110000}

‘ d e f i n e ANDI C { ‘ALU AND, 2 ’bx , ‘JB NO , ‘ASB EXT OUT, 11 ’ b00001100000}

‘ d e f i n e XOR C { ‘ALU XOR, 2 ’bx , ‘JB NO , ‘ASB REG B OUT, 11 ’ bx0001110000}

‘ d e f i n e XORI C { ‘ALU XOR, 2 ’bx , ‘JB NO , ‘ASB EXT OUT, 11 ’ b00001100000}

‘ d e f i n e LUI C {6 ’ bxxxxx , ‘ALU SLL , ‘JB NO , ‘ASB EXT OUT, 11 ’ b00001000001}

‘ d e f i n e LW C { ‘ALU ADD, 2 ’bx , ‘JB NO , ‘ASB EXT OUT, 11 ’ b10111 10 0000 }

‘ d e f i n e SW C { ‘ALU ADD, 2 ’bx , ‘JB NO , ‘ASB EXT OUT, 11 ’ b110x0 10 0000 }

‘ d e f i n e FLUSH C { ‘ALU ADD, 2 ’bx , ‘JB NO, ‘ASB EXT OUT, 11 ’ b111x0 10 0000 }

‘ d e f i n e SLL C {6 ’ bxxxxx , ‘ALU SLL , ‘JB NO , ‘ASB REG B OUT, 11 ’ bx0001010001}

‘ d e f i n e SRL C {6 ’ bxxxxx , ‘ALU SRL, ‘JB NO , ‘ASB REG B OUT, 11 ’ bx0001010001}

‘ d e f i n e SRA C {6 ’ bxxxxx , ‘ALU SRA, ‘JB NO , ‘ASB REG B OUT, 11 ’ bx0001010001}

‘ d e f i n e SLT C { ‘ALU SLT , 2 ’bx , ‘JB NO , ‘ASB REG B OUT, 11 ’ bx0001110000}

‘ d e f i n e SLTI C { ‘ALU SLT , 2 ’bx , ‘JB NO , ‘ASB EXT OUT, 11 ’ b10001100000}

‘ d e f i n e SLTU C { ‘ALU SLTU, 2 ’bx , ‘JB NO , ‘ASB REG B OUT, 11 ’ bx0001110000}

‘ d e f i n e SLTUI C { ‘ALU SLTU, 2 ’bx , ‘JB NO , ‘ASB EXT OUT, 11 ’ b10001100000}

‘ d e f i n e BEQ C {6 ’ bxxxxx , 2 ’bx , ‘JB BEQ , 3 ’ bxxx ,11 ’ bx00x0110000}

‘ d e f i n e BNE C {6 ’ bxxxxx , 2 ’bx , ‘JB BNE , 3 ’ bxxx ,11 ’ bx00x0110000}

‘ d e f i n e BGEZ C {6 ’ bxxxxx , 2 ’bx , ‘JB BGEZ , 3 ’ bxxx ,11 ’ bx00x0100000}

‘ d e f i n e BLTZ C {6 ’ bxxxxx , 2 ’bx , ‘JB BLTZ , 3 ’ bxxx ,11 ’ bx00x0100000}

‘ d e f i n e J C {6 ’ bxxxxx , 2 ’bx , ‘ JB J , 3 ’ bxxx ,11 ’ bx00x0000000}

‘ d e f i n e JR C {6 ’ bxxxxx , 2 ’bx , ‘ JB JR , 3 ’ bxxx ,11 ’ bx00x0100000}

‘ d e f i n e JAL C { ‘ALU SELB , 2 ’bx , ‘JB JAL , ‘ASB PC 8 ,11 ’ bx0001000000}

‘ d e f i n e MULTU C {6 ’ bxxxxx , 2 ’bx , ‘JB NO , 3 ’ bxxx ,11 ’ bx00x0110100}

‘ d e f i n e DIVU C {6 ’ bxxxxx , 2 ’bx , ‘JB NO , 3 ’ bxxx ,11 ’ bx00x0110010}

‘ d e f i n e MFHI C { ‘ALU SELB , 2 ’bx , ‘JB NO , ‘ASB HI ,11 ’ bx0001001000}

‘ d e f i n e MFLO C { ‘ALU SELB , 2 ’bx , ‘JB NO , ‘ASB LO ,11 ’ bx0001001000}

‘ d e f i n e BREAK C {6 ’ bxxxxx , 2 ’bx , ‘JB NO , 3 ’ bxxx ,11 ’ bx00x0000000}

// $Header : v :\\CVSLab3/ lab6 / c on t r o l l e r . v , v 1 .3 2004/05/10 00 :30 :05 cs152−a j Exp $// $Author : cs152−a j $// $Date : 2004/05/10 00 :30 :05 $

‘ t ime s ca l e 1 ns /10 ps

29

‘ include ” opcodes . v”

module c o n t r o l l e r ( c lk , r s t , INSTRUCTION, ALU OP, REG DST, JB TYPE ,ALU SRCB,

ext op , mem write , mem read , mem to reg , r eg wr i t e , u s e r s , u s e r t ,mfhi lo ,

mul t s ta r t , d i v s t a r t , SHIFT OP , s h i f t , SMNT OUT) ;input c lk , r s t ;input [ 3 1 : 0 ] INSTRUCTION;

output [ 5 : 0 ] ALU OP;output [ 4 : 0 ] REG DST;output [ 2 : 0 ] JB TYPE;output [ 2 : 0 ] ALU SRCB;output [ 4 : 0 ] SMNT OUT;reg [ 4 : 0 ] SMNT OUT;output ext op , mem write , mem read , mem to reg , r eg wr i t e , u s e r s , u s e r t , mfhi lo ,

mul t s ta r t , d i v s t a r t ;

output s h i f t ;output [ 1 : 0 ] SHIFT OP ;

reg [ 4 : 0 ] REG DST;reg [ 2 4 : 0 ] CONTROLLER OUTPUT BITS;wire [ 5 : 0 ] OP, FUNCT;wire [ 4 : 0 ] RT, RS , RD, SMNT;

assign OP = INSTRUCTION[ 3 1 : 2 6 ] ;assign RS = INSTRUCTION[ 2 5 : 2 1 ] ;assign RT = INSTRUCTION[ 2 0 : 1 6 ] ;assign RD = INSTRUCTION[ 1 5 : 1 1 ] ;assign FUNCT = INSTRUCTION [ 5 : 0 ] ;assign SMNT = INSTRUCTION [ 1 0 : 6 ] ;wire r e g w r i t e i ;

assign r e g w r i t e = ( r e g w r i t e i ) & (REG DST != 5 ’ b0 ) ;assign {ALU OP, SHIFT OP , JB TYPE , ALU SRCB, ext op , mem write , mem read , mem to reg ,

r e g w r i t e i , u s e r s , u s e r t , mfhi lo , mul t s ta r t , d i v s t a r t , s h i f t }= CONTROLLER OUTPUT BITS;

always @(∗ ) beginREG DST = RT;SMNT OUT = 5 ’bx ;case (OP)

‘RTYPE: beginREG DST = RD;case (FUNCT)

‘ADDU: CONTROLLER OUTPUT BITS = ‘ADDU C;‘SUBU: CONTROLLER OUTPUT BITS = ‘SUBU C;‘SRL : begin CONTROLLER OUTPUT BITS = ‘SRL C ;

SMNT OUT = SMNT;end

‘SLL : begin CONTROLLER OUTPUT BITS = ‘SLL C ;SMNT OUT = SMNT;end

‘SRA: begin CONTROLLER OUTPUT BITS = ‘SRA C;SMNT OUT = SMNT;end

‘JR : begin CONTROLLER OUTPUT BITS = ‘JR C ;REG DST = 5 ’ bxxxxx ;end

‘SLT : CONTROLLER OUTPUT BITS = ‘SLT C ;‘SLTU : CONTROLLER OUTPUT BITS = ‘SLTU C;‘MULTU: begin CONTROLLER OUTPUT BITS = ‘MULTU C;

REG DST = 5 ’ bxxxxx ;end

30

‘DIVU: begin CONTROLLER OUTPUT BITS = ‘DIVU C;REG DST = 5 ’ bxxxxx ;end

‘AND: CONTROLLER OUTPUT BITS = ‘AND C;‘OR: CONTROLLER OUTPUT BITS = ‘OR C;‘XOR: CONTROLLER OUTPUT BITS = ‘XOR C;‘MFHI : CONTROLLER OUTPUT BITS = ‘MFHI C ;‘MFLO: CONTROLLER OUTPUT BITS = ‘MFLO C;‘BREAK: begin CONTROLLER OUTPUT BITS = ‘BREAK C;

REG DST = 5 ’ bxxxxx ;end

default : CONTROLLER OUTPUT BITS = 25 ’ bxxxxxxxxxxxxxxxxxxxx ;endcaseend

‘BSPECIAL : beginREG DST = 5 ’ bxxxxx ;case (RT)

‘BLTZ : CONTROLLER OUTPUT BITS = ‘BLTZ C;‘BGEZ: CONTROLLER OUTPUT BITS = ‘BGEZ C;default : CONTROLLER OUTPUT BITS = 25 ’ bxxxxxxxxxxxxxxxxxxxx ;

endcaseend

‘BEQ: begin CONTROLLER OUTPUT BITS = ‘BEQ C;REG DST = 5 ’ bxxxxx ;end

‘BNE: begin CONTROLLER OUTPUT BITS = ‘BNE C;REG DST = 5 ’ bxxxxx ;end

‘ J : begin CONTROLLER OUTPUT BITS = ‘ J C ;REG DST = 5 ’ bxxxxx ;end

‘JAL : begin CONTROLLER OUTPUT BITS = ‘JAL C ;REG DST = 5 ’ d31 ;end

‘LUI : begin CONTROLLER OUTPUT BITS = ‘LUI C ;SMNT OUT = 5 ’ d16 ;end

‘ADDIU: CONTROLLER OUTPUT BITS = ‘ADDIU C;‘ORI : CONTROLLER OUTPUT BITS = ‘ORI C ;‘ANDI : CONTROLLER OUTPUT BITS = ‘ANDI C ;‘XORI : CONTROLLER OUTPUT BITS = ‘XORI C ;‘SLTI : CONTROLLER OUTPUT BITS = ‘SLTI C ;‘SLTUI : CONTROLLER OUTPUT BITS = ‘SLTUI C ;‘LW: CONTROLLER OUTPUT BITS = ‘LW C;‘SW: begin CONTROLLER OUTPUT BITS = ‘SW C;

REG DST = 5 ’ bxxxxx ;end

‘FLUSH: beginCONTROLLER OUTPUT BITS = ‘FLUSH C;REG DST = 5 ’ bxxxxx ;end

default : CONTROLLER OUTPUT BITS = 25 ’ bxxxxxxxxxxxxxxxxxxx ;endcase

end

endmodule

A.6 Branch Predictor

‘ d e f i n e h width 7

module branch pred i c t o r ( c lk , r s t , i PC , i branch taken , i branch , o take branch , s t a l l ,i d fw s t a l l , id fw bubble ) ; // i OLD PC , i b ranch mispred i c t , i OLD COUNT, o COUNT,i OLD HISTORY , o HISTORY) ;

input c lk , r s t , i b ranch taken , i b ranch ; // i b ranch mi sp r ed i c t ;input [ 2 9 : 0 ] i PC ; // , i OLD PC ;input s t a l l , i d fw s t a l l , id fw bubble ;

31

// input [ 1 : 0 ] i OLD COUNT;// input [ h width : 0 ] i OLD HISTORY;// output [ h width : 0 ] o HISTORY;// output [ 1 : 0 ] o COUNT;

output o take branch ;

reg [ ‘ h width : 0 ] h i s t o r y ;

always @ ( posedge c l k )i f ( i b ranch && ˜ i d f w s t a l l ) begin

h i s t o r y [ ‘ h width −1:0] <= h i s t o r y [ ‘ h width : 1 ] ;i f ( i b ranch taken )

h i s t o r y [ ‘ h width ] <= 1 ’b1 ;else

h i s t o r y [ ‘ h width ] <= 1 ’b0 ;end

wire [ 1 0 : 0 ] s e l e c t o r ;

assign s e l e c t o r = { i PC [10:10 − ‘ h width ] ˆ h i s to ry , i PC [10− ‘ h width −1 : 0 ]} ;

wire [ 1 0 : 0 ] wr i t e addr ;

reg [ 1 0 : 0 ] s e l e c t o r i f , s e l e c t o r i d , s e l e c t o r fw , s e l e c t o r e x 1 ;

wire [ 1 : 0 ] c o un t i f ;

reg [ 1 : 0 ] count id , count fw , count ex1 ;

always @ ( posedge c l k )i f (˜ s t a l l ) begin

count id <= coun t i f ;count fw <= count id ;count ex1 <= count fw ;

end else i f (˜ i d f w s t a l l )count ex1 <= count fw ;

always @ ( posedge c l k )i f (˜ s t a l l ) begin

s e l e c t o r i f <= s e l e c t o r ;s e l e c t o r i d <= s e l e c t o r i f ;s e l e c t o r fw <= s e l e c t o r i d ;s e l e c t o r e x 1 <= s e l e c t o r fw ;

end else i f (˜ i d f w s t a l l )s e l e c t o r e x 1 <= s e l e c t o r fw ;

‘ i f n d e f s yn th e s i si n i t i a l

h i s t o r y = 0 ;‘ e nd i f

wire [ 1 : 0 ] newCount ;sa t adder count adder ( . i IN ( count ex1 ) , . i up ( i b ranch taken ) , . o OUT(newCount ) ) ;wire [ 1 : 0 ] count raw ;ram 2 2 bank1 (. addra ( s e l e c t o r e x 1 ) ,. addrb ( s e l e c t o r ) ,. c l ka ( c l k ) ,. c lkb ( c l k ) ,. dina (newCount ) ,. doutb ( count raw ) ,. wea ( i b ranch ) ) ;

reg c o l l i s i o n r ;

32

always @ ( posedge c l k )c o l l i s i o n r <= ( s e l e c t o r e x 1 == s e l e c t o r ) && i branch ;

assign c o un t i f = c o l l i s i o n r ? newCount : count raw ;

// reg o take branch ;assign o take branch = count id [ 1 ] ;

endmodule

module sa t adder ( i IN , i up , o OUT) ;input [ 1 : 0 ] i IN ;input i up ;output [ 1 : 0 ] o OUT;reg [ 1 : 0 ] o OUT;

always @ ( i IN or i up ) begini f ( i up && ( i IN != 2 ’ b11 ) )

o OUT = i IN + 1 ’ b1 ;else i f (˜ i up && ( i IN != 2 ’ b00 ) )

o OUT = i IN − 1 ’ b1 ;else

o OUT = i IN ;end

endmodule

// $Header : v :\\CVSLab3/ lab5 / fas tcomparator . v , v 1 .1 2004/04/07 08 :37 :07 cs152−ah Exp $// $Author : cs152−ah $// $Date : 2004/04/07 08 :37 :07 $

‘ t ime s ca l e 1 ns /10 ps

module FastComparator (RS , RT, eq , l t z ) ;input [ 3 1 : 0 ] RS , RT;output eq , l t z ;

assign eq = (RS == RT) ;assign l t z = (RS[31 ] == 1) ;

endmodule/∗module FastComparator Test ( ) ;

reg [ 3 1 : 0 ] RS, RT;wire eq , l t z ;

FastComparator f c (RS, RT, eq , l t z ) ;

a lways beg inRS = $random ;RT = $random ;#50;i f ( eq != (RS == RT) )

$d i s p l a y (”%d Error on e q u a l i t y check %h == %h” , $time , RS, RT) ;i f ( l t z != (RS[31] == 1) )

$d i s p l a y (”%d Error on l t z check %h < 0” , $time , RS) ;end

endmodule∗/

‘ d e f i n e NOJB 2 ’ b00‘ d e f i n e JUMP 2 ’ b01‘ d e f i n e BRANCH 2 ’ b10

module f a s t jbDecode (INSTRUCTION, JB TYPE) ;

input [ 3 1 : 0 ] INSTRUCTION;

33

output [ 1 : 0 ] JB TYPE;reg [ 1 : 0 ] JB TYPE;always @(∗ ) begin

case (INSTRUCTION[ 3 1 : 2 6 ] )1 :JB TYPE = ‘BRANCH;2 :JB TYPE = ‘JUMP;3 :JB TYPE = ‘JUMP;4 :JB TYPE = ‘BRANCH;5 :JB TYPE = ‘BRANCH;default : JB TYPE = ‘NOJB;endcase

end

endmodule

A.7 Forwarding Module and Hazard Detection

// $Header : v :\\CVSLab3/ lab6 /ForwardingModule2 . v , v 1 .2 2004/05/10 00 :30 :03 cs152−a j Exp $// $Author : cs152−a j $// $Date : 2004/05/10 00 :30 :03 $

‘ t ime s ca l e 1 ns /10 ps

‘ d e f i n e FW NO 3 ’ b00‘ d e f i n e FW EX2 3 ’ b001‘ d e f i n e FWMEM2 3 ’ b010‘ d e f i n e FWMEM3 3 ’ b011‘ d e f i n e FWWR 3 ’ b100

module ForwardingModule2 ( s t a l l , u s e r s , u s e r t ,read mem from ex2 , read mem from mem2 , read mem from mem3 , mem forward mem2 ,RS , FW OP RS,RT, FW OP RT,

write mem ,wr from ex1 , RD FROM EX1,wr from ex2 , RD FROM EX2,wr from mem2 ,RD FROM MEM2,wr from mem3 , RD FROM MEM3,wr from wr , RD FROM WR,mem2 forward ex2 , mem2 forward ex1 ,mult done , mfhi lo ,s h i f t e x 2 ) ;

output s t a l l , mem2 forward ex2 , mem2 forward ex1 , mem forward mem2 ;

input mult done , mfh i lo ;

input s h i f t e x 2 ;

input use r s , u s e r t , read mem from ex2 , read mem from mem2 , read mem from mem3 , write mem ,wr from ex1 , wr from ex2 , wr from mem2 , wr from wr , wr from mem3 ;

input [ 4 : 0 ] RS , RT, RD FROM EX1, RD FROM EX2, RD FROM MEM2, RD FROM MEM3, RD FROM WR;

output [ 2 : 0 ] FW OP RS, FW OP RT;reg [ 2 : 0 ] FW OP RS, FW OP RT;reg s t a l l ;

always @ ( ∗ ) begins t a l l = 0 ;i f (˜ mult done && mfhi lo )

s t a l l = 1 ;else i f ( wr from ex1 && (((RD FROM EX1 == RS) && us e r s ) | | ( ( RD FROM EX1 == RT) &&

us e r t ) ) )s t a l l = 1 ;

else i f ( wr from ex2 && ( s h i f t e x 2 | | read mem from ex2 ) && (((RD FROM EX2 == RS) &&

34

u s e r s ) | | ( ( RD FROM EX2 == RT) && us e r t ) ) )s t a l l = 1 ;

else i f ( read mem from mem2 && (((RD FROM MEM2 == RS) && us e r s ) | | ( (RD FROM MEM2== RT) && us e r t ) ) )

s t a l l = 1 ;end

assign mem forward mem2 = ( wr from ex1 && write mem && (RD FROM EX1 == RT) ) ;

assign mem2 forward ex2 = ( wr from ex2 && write mem && (RD FROM EX2 == RT) ) ;

assign mem2 forward ex1 = ( wr from mem2 && write mem && (RD FROM MEM2 == RT) ) ;

always @ ( ∗ ) begini f (RD FROM EX2 == RS && wr from ex2 ) begin

FW OP RS = ‘FW EX2;endelse i f (RD FROM MEM2 == RS && wr from mem2 ) begin

FW OP RS = ‘FWMEM2;endelse i f (RD FROM MEM3 == RS && wr from mem3 ) begin

FW OP RS = ‘FWMEM3;endelse i f (RDFROM WR == RS && wr from wr ) begin

FW OP RS = ‘FWWR;endelse begin

FW OP RS = ‘FW NO;end

i f (RD FROM EX2 == RT && wr from ex2 ) beginFW OP RT = ‘FW EX2;

endelse i f (RD FROM MEM2 == RT && wr from mem2 ) begin

FW OP RT = ‘FWMEM2;endelse i f (RD FROM MEM3 == RT && wr from mem3 ) begin

FW OP RT = ‘FWMEM3;endelse i f (RDFROM WR == RT && wr from wr ) begin

FW OP RT = ‘FWWR;endelse begin

FW OP RT = ‘FW NO;end

end

endmodule

module fowardreg ( c lk , r s t ,i RD DATA EX1 , i RD DATA EX2 , i RD DATA MEM2,o RD DATA EX2 , o RD DATA MEM2, o RD DATA WR, f r e g s t a l l , i RD DATA MEM3, o RD DATA MEM3) ;

input c lk , r s t , f r e g s t a l l ;input [ 3 1 : 0 ] i RD DATA EX1 , i RD DATA EX2 , i RD DATA MEM2;input [ 3 1 : 0 ] i RD DATA MEM3;output [ 3 1 : 0 ] o RD DATA EX2 , o RD DATA MEM2, o RD DATA WR, o RD DATA MEM3;reg [ 3 1 : 0 ] o RD DATA EX2 , o RD DATA MEM2, o RD DATA WR, o RD DATA MEM3;

always @ ( posedge c l k ) begini f (˜ f r e g s t a l l ) begin

o RD DATA EX2 <= i RD DATA EX1 ;o RD DATA MEM2 <= i RD DATA EX2 ;o RD DATA MEM3 <= i RD DATA MEM2;o RD DATA WR <= i RD DATA MEM3;

35

endend

endmodule

A.8 Stalling Logic

// $Header : v :\\CVSLab3/ lab6 / S t a l l L o g i c . v , v 1 .3 2004/05/09 23 :33 :00 cs152−a i Exp $// $Author : cs152−a i $// $Date : 2004/05/09 23 :33 :00 $

‘ t ime s ca l e 1 ns / 1 ps

module S t a l l L o g i c ( g l o b a l s t a l l , h a z a rd s t a l l ,i cache mi s s , dcache miss ,branch mispred ict ,i f i d s t a l l , i f i d bubb l e ,fw ex1 s t a l l , fwex1 bubble ,i d fw s t a l l , id fw bubble ,e x 1 ex2 s t a l l ,ex2mem2 stal l ,f r e g s t a l l , branch in forward , p i p e l i n e s t a l l) ;

input g l o b a l s t a l l ;input ha z a r d s t a l l ;input i c a che m i s s ;input dcache miss ;input branch mispred i c t ;

input branch in fo rward ;

output i f i d s t a l l ;output i f i d b ubb l e ;output i d f w s t a l l ;output id fw bubble ;output f w e x 1 s t a l l ;output e x 1 e x 2 s t a l l ;output ex2mem2 stal l ;output f r e g s t a l l ;

output fwex1 bubble ;output p i p e l i n e s t a l l ;

reg fwex1 bubble ;reg i f i d s t a l l ;reg i f i d b ubb l e p r e ;reg i d f w s t a l l ;reg i d fw bubb l e pre ;reg f w e x 1 s t a l l ;reg e x 1 e x 2 s t a l l ;reg ex2mem2 stal l ;reg f r e g s t a l l ;

assign i f i d b ubb l e = ( i f i d b ubb l e p r e | branch mispred i c t ) ;assign id fw bubble = ( id fw bubb l e pre | branch mispred i c t ) ;

assign p i p e l i n e s t a l l = ( g l o b a l s t a l l | ha z a r d s t a l l | dcache miss ) ;

always @ ( g l o b a l s t a l l or ha z a r d s t a l l or i c a che m i s s or dcache miss orbranch in fo rward ) begin

i f ( dcache miss ) begini f i d s t a l l = 1 ;i f i d b ubb l e p r e = 0 ;i d f w s t a l l = 1 ;id fw bubb l e pre = 0 ;fw e x 1 s t a l l = 1 ;e x 1 e x 2 s t a l l = 1 ;ex2mem2 stal l = 1 ;f r e g s t a l l = 1 ;

36

fwex1 bubble = 0 ;end else i f ( i c a che m i s s | g l o b a l s t a l l | ha z a r d s t a l l ) begin

i f ( branch in fo rward ) begini f i d s t a l l = 1 ;i f i d b ubb l e p r e = 0 ;i d f w s t a l l = 1 ;id fw bubb l e pre = 0 ;fw e x 1 s t a l l = 0 ;fwex1 bubble = 1 ;e x 1 e x 2 s t a l l = 0 ;ex2mem2 stal l = 0 ;f r e g s t a l l = 1 ;

end else begini f i d s t a l l = 1 ;i f i d b ubb l e p r e = 0 ;i d f w s t a l l = 0 ;id fw bubb l e pre = 1 ;fw e x 1 s t a l l = 0 ;fwex1 bubble = 0 ;e x 1 e x 2 s t a l l = 0 ;ex2mem2 stal l = 0 ;f r e g s t a l l = 1 ;

endend else begin

i f i d s t a l l = 0 ;i f i d b ubb l e p r e = 0 ;i d f w s t a l l = 0 ;id fw bubb l e pre = 0 ;fw e x 1 s t a l l = 0 ;e x 1 e x 2 s t a l l = 0 ;ex2mem2 stal l = 0 ;f r e g s t a l l = 0 ;fwex1 bubble = 0 ;

end

end

endmodule

A.9 Data Memory

// $Header : v :\\CVSLab3/ lab6 /dmem. v , v 1 .5 2004/05/14 02 :24 :19 cs152−a f Exp $// $Author : cs152−a f $// $Date : 2004/05/14 02 :24 :19 $

‘ t ime s ca l e 1 ns /10 ps

module dmem( clk , r s t ,ADDRESS, DIN , DOUT, write , enable ,dcache miss , dcache f lu sh ,DRAM DIN, DRAMDOUT, DRAMADDR,dram read , dram write , dram ready ,BOOT0 DATA, BOOT0 ADDR, boot0write ,SWITCH, DP0 , DP1 , ASCII REG , POINT REG, CYCLE COUNT) ;

input c lk , r s t ;

//Data Memory Proper In t e r f a c einput write , enable ;input [ 3 1 : 0 ] ADDRESS, DIN ;output [ 3 1 : 0 ] DOUT;reg [ 3 1 : 0 ] DOUT;

input dcache f l u sh ;output dcache miss ;

//Lines to /from SDRAM in the TopLeveloutput [ 3 1 : 0 ] DRAMADDR;input [ 2 5 5 : 0 ] DRAM DIN;

37

output [ 2 5 5 : 0 ] DRAMDOUT;output dram read , dram write ;input dram ready ;

//Boot0 Data Source Lined to /from TopLevelinput [ 3 1 : 0 ] BOOT0 DATA;output [ 1 0 : 0 ] BOOT0 ADDR;output boot0wr i te ;assign boot0wr i te = 1 ’ b0 ;

reg [ 1 0 : 0 ] BOOT0 ADDR;reg [ 1 0 : 0 ] BOOT0 ADDR R;

input [ 3 1 : 0 ] SWITCH;output [ 3 1 : 0 ] DP0 , DP1;

//IO Lines to /from TopLeveloutput [ 6 3 : 0 ] ASCII REG ;output [ 7 : 0 ] POINT REG;output [ 3 1 : 0 ] CYCLE COUNT;

wire [ 1 : 0 ] se lType = ADDRESS[ 3 1 : 3 0 ] ;

wire enableSRAM = selType [ 1 ] ? 1 ’ b0 : enable ;wire enableMMIO = ( selType == 2 ’b11 ) ? enable : 1 ’ b0 ;

wire writeSRAM = selType [ 1 ] ? 1 ’ b0 : wr i t e ;wire writeMMIO = ( selType == 2 ’b11 ) ? wr i t e : 1 ’ b0 ;

wire [ 3 1 : 0 ] DOUT sram , DOUT mmio;

wire [ 1 0 : 0 ] CACHE ADDR;

wire cache enab l e proc , cache enable mem , cache wr i t e p roc , cache write mem ;wire [ 7 : 0 ] CACHE ADDR WIDE;

d c a ch e c on t r o l l e r c o n t r o l l e r ( . c l k ( c l k ) , . r s t ( r s t ) , .ADDR IN(ADDRESS) , . enable ( enableSRAM) , .wr i t e (writeSRAM) , . f l u s h ( dcache f l u sh ) , . mem ready ( dram ready ) ,

. cache miss ( dcache miss ) , . mem read ( dram read ) , . mem write (dram write ) , .ADDR OUT(DRAMADDR) , .CACHE ADDR OUT(CACHE ADDR) ,

. c a che enab l e p roc ( cache enab l e p roc ) , . cache enable mem ( cache enable mem ), . c a che wr i t e p ro c ( c a che wr i t e p ro c ) , . cache write mem ( cache write mem) , .CACHE ADDR OUT WIDE(CACHE ADDR WIDE) ) ;

d cache cache (. addra (CACHE ADDR) ,. addrb (CACHE ADDR WIDE) , //CACHE ADDR[ 1 0 : 3 ] ) ,. c l ka ( c l k ) ,. c lkb ( c l k ) ,. dina (DIN) ,. dinb (DRAM DIN) ,. douta (DOUT sram) ,. doutb (DRAMDOUT) ,. ena ( cache enab l e p roc ) ,. enb ( cache enable mem ) ,. wea ( ca che wr i t e p ro c ) ,. web( cache write mem ) ) ;

always@ (posedge c l k )i f (˜ dcache miss ) begin

BOOT0 ADDR R <= ADDRESS[ 1 2 : 2 ] ;BOOT0 ADDR <= ADDRESS[ 1 2 : 2 ] ; //BOOT0 ADDR R;

end

‘ i f n d e f s yn th e s i s

wire debug = 1 ;

38

reg [ 1 0 : 0 ] CACHE ADDR R;

always @ ( posedge c l k )CACHE ADDR R <= CACHE ADDR;

always @ ( posedge c l k )i f ( debug )

i f ( c a che wr i t e p ro c )$d i sp l ay ( ”Writing %x to address %x in cache ” , DIN , CACHE ADDR[ 9 : 0 ] ) ;

else i f ( cache enab l e p roc ) begin#5; $d i sp l ay ( ”Reading %x from address %x in cache ” , DOUT sram ,

CACHE ADDR R[ 9 : 0 ] ) ;end

‘ e nd i f

ioMod mmio ( . c l k ( c l k ) ,. r s t ( r s t ) ,.ADDRESS(ADDRESS) ,.DIN(DIN) ,.DOUT(DOUT mmio) ,. en (1 ’ b1 ) ,. we(writeMMIO) ,.SWITCH (SWITCH) ,.DP0(DP0) ,.DP1(DP1) ,. ASCII REG(ASCII REG) ,.POINT REG(POINT REG) ,.CYCLE COUNT(CYCLE COUNT)

) ;

reg [ 3 1 : 0 ] DOUT mmio r , BOOT0 DATA r ;

always @ ( posedge c l k )i f (˜ dcache miss ) beginDOUT mmio r <= DOUT mmio;BOOT0 DATA r <= BOOT0 DATA;

end

reg [ 1 : 0 ] selType CLK 0 ;

always @ ( posedge c l k )i f (˜ dcache miss )

selType CLK 0 <= selType ;

reg [ 1 : 0 ] selType CLKED , selType CLKED2 ;

always@ (posedge c l k )i f (˜ dcache miss )

selType CLKED <= selType CLK 0 ;

always @ ( posedge c l k )i f (˜ dcache miss )

selType CLKED2 <= selType CLKED ;

always@ (∗ )case ( selType CLKED2)2 ’ b10 : DOUT = BOOT0 DATA r ;2 ’ b11 : DOUT = DOUT mmio r ;default : DOUT = DOUT sram ;endcase

endmodule

// $Header : v :\\CVSLab3/ lab6 /cache . v , v 1 .3 2004/05/11 03 :28 :57 cs152−a f Exp $// $Author : cs152−a f $// $Date : 2004/05/11 03 :28 :57 $

39

‘ t ime s ca l e 1 ns / 1 ps‘ d e f i n e IDLE 3 ’ d0‘ d e f i n e READY 3 ’ d1‘ d e f i n e WRITEMEM 3 ’ d2‘ d e f i n e READMEM 3 ’ d3‘ d e f i n e FINISH MISS 3 ’ d4

module d c a ch e c on t r o l l e r ( c lk , r s t , ADDR IN, enable , write , f l u sh , mem ready ,cache miss , mem read , mem write , ADDR OUT, CACHE ADDR OUT,cache enab l e proc , cache enable mem , cache wr i t e p roc ,

cache write mem , CACHE ADDR OUT WIDE) ;

input c lk , r s t , enable , wr ite , f l u sh , mem ready ;input [ 3 1 : 0 ] ADDR IN;

output cache miss , mem read , mem write , cache enab l e proc , cache enable mem ,cache wr i t e p roc , cache write mem ;

output [ 3 1 : 0 ] ADDR OUT;output [ 1 0 : 0 ] CACHE ADDR OUT;output [ 7 : 0 ] CACHE ADDR OUT WIDE;reg cache miss , mem read , mem write , cache enab l e proc , cache enable mem , cache wr i t e p roc ,

cache write mem , update , e n l a t c h i npu t s ;reg [ 3 1 : 0 ] ADDR OUT;reg [ 1 : 0 ] TAG IN TYPE;

reg r enab l e , r wr i t e , r f l u s h , r2 enab le , r 2 wr i t e , r 2 f l u s h , u enable , u wr i te , u f l u s h ;reg [ 3 1 : 0 ] R ADDR, R2 ADDR, U ADDR;

wire [ 3 1 : 0 ] TAG ADDR IN;

wire [ 3 1 : 0 ] T DIRTY ADDR OUT;wire t ready , t bank , t i n ca che , t d i r t y ;

reg [ 3 1 : 0 ] DIRTY ADDR OUT;reg ready , bank , in cache , d i r t y ;

wire debug ;assign debug = 1 ’ b0 ;

reg [ 2 : 0 ] STATE, NS;

assign CACHE ADDR OUT = {bank , R2 ADDR[ 1 1 : 2 ] } ;assign CACHE ADDR OUT WIDE = { t bank , R2 ADDR[ 1 1 : 5 ] } ;

// Tag F i l ecache tag t ( .ADDR(U ADDR) , . c l k ( c l k ) , . r s t ( r s t ) , . ready ( t r eady ) , . bank ( t bank ) , . i n cache (

t i n c a ch e ) , . d i r t y ( t d i r t y ) , .ADDR OUT(T DIRTY ADDR OUT) , . wr i t e ( u wr i t e & ˜ u f l u s h ) , .update ( update ) , . enable ( u enab le ) ) ;

always @(posedge c l k ) begin

i f ( r s t ) STATE <= ‘IDLE ;else STATE <= NS;

// s yn t h e s i s t r a n s l a t e o f fi f ( (STATE != NS) ) $d i sp l ay ( $time , ” Cache Cont r o l l e r Trans i t i on from %x to %x” ,

STATE, NS) ;// s yn t h e s i s t r an s l a t e on

endreg z e r o f l u s h ;reg r e g d i r t y ;always @ ( ∗ )

DIRTY ADDR OUT = T DIRTY ADDR OUT;always @(posedge c l k ) begin

40

bank <= t bank ;ready <= t ready ;i n cache <= t i n c a ch e ;i f ( r e g d i r t y ) begin

d i r t y <= t d i r t y ;

end// DIRTY ADDR OUT <= T DIRTY ADDR OUT;

i f ( r s t ) beginr enab l e <= 0;r w r i t e <= 0;r f l u s h <= 0;

endelse i f ( e n l a t c h i npu t s ) begin

r enab l e <= enable ;r w r i t e <= wr i t e ;r f l u s h <= f l u s h ;

end

i f ( e n l a t c h i npu t s ) beginR ADDR <= ADDR IN;R2 ADDR <= R ADDR;

end

endalways @ ( posedge c l k )

i f ( r s t | | z e r o f l u s h ) beginr 2 f l u s h <= 0;r 2 w r i t e <= 0;r2 enab l e <= 0;

endelse i f ( e n l a t c h i npu t s ) begin

r 2 f l u s h <= r f l u s h ;r 2 w r i t e <= r wr i t e ;r 2 enab l e <= r enab l e ;

end

// TAGMEM INPUT SELECTIONalways @(∗ ) begin

case (TAG IN TYPE)2 ’ d0 : begin

u enab le = enable ;u wr i t e = wr i t e ;u f l u s h = f l u s h ;U ADDR = ADDR IN;

end2 ’ d1 : begin

u enab le = r enab l e ;u wr i t e = r w r i t e ;u f l u s h = r f l u s h ;U ADDR = R ADDR;

end2 ’ d2 : begin

u enab le = r2 enab l e ;u wr i t e = r2 wr i t e ;u f l u s h = r 2 f l u s h ;U ADDR = R2 ADDR;

enddefault : begin

u enab le = enable ;u wr i t e = wr i t e ;u f l u s h = f l u s h ;U ADDR = ADDR IN;

endendcase

end

41

//STATE Trans i t ionsalways @(∗ ) begin

case (STATE)‘IDLE :begin

i f ( ready ) NS = ‘READY;else NS = ‘IDLE ;

end‘READY:begin

i f ( (˜ in cache && r2 enab l e ) | | ( i n cache && r 2 f l u s h ) ) NS = ‘WRITEMEM;

else NS = ‘READY;end‘WRITEMEM:begin

i f ( r 2 f l u s h && (mem ready | | ˜ d i r t y ) ) NS = ‘READY;else i f ( ˜ d i r t y | | mem ready ) NS = ‘READMEM;else NS = ‘WRITEMEM;// s yn t h e s i s t r a n s l a t e o f fi f ( debug && (˜ d i r t y ) ) $d i sp l ay ( $time , ” WriteBack can c e l l e d because

d i r t y remained low in i n i t i a l WRITEMEM stage ” ) ;// s yn t h e s i s t r an s l a t e on

end‘READMEM:begin

i f ( mem ready ) NS = ‘READY;else NS = ‘READMEM;

end‘ FINISH MISS : NS = ‘READY;default : NS = ‘IDLE ;

endcaseend

// reg cache miss , mem read , mem write , cache enab le proc , cache enable mem ,cache wr i t e proc , cache write mem ;

// reg [ 3 1 : 0 ] ADDR OUT;

//STATE t r i g g e r e d outputsalways @(∗ ) begin

cache enab l e p roc = 0 ;cache enable mem = 0;ca che wr i t e p ro c = 0 ;cache write mem = 0;cache miss = 0 ;TAG IN TYPE = 0;en l a t c h i npu t s = 0 ;update = 0 ;mem write = 0 ;mem read = 0 ;z e r o f l u s h = 0 ;r e g d i r t y = 0 ;ADDR OUT = 32 ’ bx ;case (STATE)

‘IDLE :begin

cache miss = 1 ;

end‘READY:begin

i f ( i n cache && r2 enab l e && ˜ r 2 f l u s h ) begin // cache h i tcache enab l e p roc = r2 enab l e ;c a che wr i t e p ro c = r2 wr i t e ;e n l a t c h i npu t s = 1 ;

endelse i f ( ( ˜ in cache && r2 enab l e ) | | ( r 2 f l u s h && in cache ) ) begin

42

cache miss = 1 ;TAG IN TYPE = 2;r e g d i r t y = 1 ;

endelse en l a t c h i npu t s = 1 ;

end‘WRITEMEM:begin

ADDR OUT = DIRTY ADDR OUT; // Write the to be rep laced cache l i n e tomemory

cache miss = 1 ;cache enable mem = 1;TAG IN TYPE = 2;i f ( ( r 2 f l u s h && ˜ d i r t y ) | | ( r 2 f l u s h && mem ready ) ) TAG IN TYPE

= 1;

i f ( r 2 f l u s h && (mem ready | | ˜ d i r t y ) ) beginz e r o f l u s h = 1 ;

endi f ( ˜ mem ready && d i r t y )

mem write = 1 ;else i f (˜ r 2 f l u s h )

update = 1 ;

end‘READMEM:begin

ADDR OUT = {R2 ADDR[ 3 1 : 5 ] , 5 ’ b000 } ; // Burstread the memory l i n e conta in ing the de s i r ed entry and wr i t e in tocache

mem read = 1 ;cache miss = 1 ;TAG IN TYPE = 2;i f ( mem ready ) begin

// mem ready high i n d i c a t e s read frommemory has f i n i s h e d and r e s u l t i s s t a b l e in DIN MEMORY

//

in

which

case

enab le

wr i t e

to

cache

TAG IN TYPE = 1;cache enable mem = 1;cache write mem = 1;mem read = 0 ;

endend‘ FINISH MISS :begin

cache miss = 1 ;TAG IN TYPE = 1;

enddefault :begin

update = 0 ;TAG IN TYPE = 0;ADDR OUT = 32 ’bX;

43

cache enable mem = 0;cache write mem = 0;cache enab l e p roc = 0 ;c a che wr i t e p ro c = 0 ;cache miss = 0 ;mem read = 0 ;mem write = 0 ;e n l a t c h i npu t s = 0 ;

endendcase

end

‘ i f n d e f s yn th e s i salways @ ( negedge c l k ) begin

i f ( debug ) begini f (STATE == ‘READY) begin

i f ( ˜ in cache && r enab l e ) begini f ( r w r i t e )

$d i sp l ay ( $time , ” Cache miss on wr i t e r eque s t !Address : %x” , R ADDR) ;

else$d i sp l ay ( $time , ” Cache miss on read r eque s e t !

Address : %x” , R ADDR) ;end

i f ( i n cache && r enab l e ) $d i sp l ay ( $time , ” Cache h i t ! ” ) ;endend

end

‘ e nd i f

endmodule

// $Header : v :\\CVSLab3/ lab6 /pipel ined memory/ cache tag . v , v 1 .3 2004/05/07 23 :30 :54 cs152−a iExp $

// $Author : cs152−a i $// $Date : 2004/05/07 23 :30 :54 $

‘ t ime s ca l e 1 ns / 1 ps

module cache tag (ADDR, clk , r s t , ready , bank , in cache , d i r ty , ADDR OUT, write , update ,enable ) ;

input c lk , r s t ;input [ 3 1 : 0 ] ADDR;output [ 3 1 : 0 ] ADDR OUT;input write , update ;input enable ;output ready , bank , in cache , d i r t y ;

wire [ 1 4 : 0 ] Tag1 , Tag2 ;wire [ 1 3 : 0 ] myTag ;

assign myTag = ADDR[ 2 5 : 1 2 ] ;

wire va l id1 , va l i d2 ;

wire [ 6 : 0 ] myLine ;assign myLine = ADDR[ 1 1 : 5 ] ;

wire write bank ;wire [ 3 1 : 0 ] ADDROUTRAW;reg [ 3 1 : 0 ] ADDR OUT;// always @ ( posedge c l k )// ADDR OUT <= ADDROUTRAW;

44

always @ ( ∗ )ADDR OUT = ADDROUTRAW;

// tag mem c my tag mem ( . ready ( ready ) , . r s t ( r s t ) , .ADDR(ADDR) , . c l k ( c l k ) , .TAG1(Tag1), .TAG2(Tag2) ,

// . v a l i d 1 ( va l i d 1 ) , . v a l i d 2 ( v a l i d 2 ) , . update ( update ) , . update bank ( wr i t e bank ) , .ADDR OUT(ADDR OUT) , . en ( enab le ) ) ;

tag mem c my tag mem ( . ready ( ready ) , . r s t ( r s t ) , .ADDR(ADDR) , . c l k ( c l k ) , .TAG1(Tag1 ), .TAG2(Tag2 ) ,

. va l i d1 ( va l i d1 ) , . va l i d2 ( va l i d2 ) , . update ( update ) , . update bank ( bank ) , .ADDR OUT(ADDROUTRAW) , . en ( enable ) ) ;

wire isBank1 , isBank2 ;

reg [ 1 3 : 0 ] MyTagReg ;always @ ( posedge c l k )

MyTagReg <= myTag ;

assign isBank1 = ({1 ’ b1 , MyTagReg} == Tag1 ) ;assign isBank2 = ({1 ’ b1 , MyTagReg} == Tag2 ) ;

assign i n cache = isBank1 | | isBank2 ;

assign bank = in cache ? isBank2 : wr i te bank ;

reg [ 6 : 0 ] myLineReg ;reg inCacheReg , isBank2Reg , writeReg , updateReg , val id1Reg , val id2Reg ;reg enab l e r ;always @ ( posedge c l k )

begin// inCacheReg <= in cache ;// isBank2Reg <= bank ;// isBank2 ;writeReg <= wr i t e ;//updateReg <= update ;// va l id1Reg <= va l i d 1 ;// va l id2Reg <= va l i d 2 ;myLineReg <= myLine ;enab l e r <= enable ;

end

always @ ( ∗ ) begin/∗

i f ( r s t ) beg inupdateReg = 0;

ende l s e

∗/// beg in

inCacheReg = in cache ;isBank2Reg = bank ; // isBank2 ;//writeReg = wr i t e ;updateReg = update ;val id1Reg = va l i d1 ;val id2Reg = va l i d2 ;

//endend

stat mem my stat mem ( . LINE(myLineReg ) , . c l k ( c l k ) , . i n cache ( inCacheReg ) , . bank (isBank2Reg ) ,

. wr i t e ( writeReg ) , . wr i te bank ( wr ite bank ) , . bank d i r ty ( d i r t y ) , . update ( updateReg ) , .va l i d1 ( val id1Reg ) , . va l i d2 ( val id2Reg ) , . en ( enab l e r ) ) ;

endmodule

module stat mem (LINE , c lk , in cache , bank , write , write bank , bank dirty , update , va l id1 ,va l id2 , en ) ;

45

input [ 6 : 0 ] LINE ;input c lk , bank , write , update , va l id1 , va l id2 , i n cache ;input en ;output write bank , bank d i r ty ;wire wr1 , wr2 ;assign wr1 = (˜ write bank & update ) | | ( wr i t e & in cache & ˜bank ) ;assign wr2 = ( write bank & update ) | | ( wr i t e & in cache & bank ) ;

wire ram din ;

assign ram din = ( update ? wr i t e : 1 ) ;// ‘ i f n d e f s yn t h e s i s// RAMB4 S1 S1 neg edge ram ( .DOA( d i r t y 1 ) , .DOB( d i r t y 2 ) , .ADDRA({4 ’ b0 , 1 ’ b0 ,

LINE}) , .ADDRB({4 ’ b0 , 1 ’ b1 , LINE}) ,// .CLKA( c l k ) , .CLKB( c l k ) , .DIA( ram din ) , .DIB( ram din ) , .ENA(1 ’ b1 ) , .ENB(1 ’ b1

) , .RSTA(1 ’ b0 ) , .RSTB(1 ’ b0 ) , .WEA(wr1) , .WEB(wr2) ) ;

// ‘ e l s edirty mem dmem(. addra ({1 ’ b0 , LINE}) ,. addrb ({1 ’ b1 , LINE}) ,. c l ka ( c l k ) ,. c lkb ( c l k ) ,. dina ( ram din ) ,. dinb ( ram din ) ,. douta ( d i r ty1 ) ,. doutb ( d i r ty2 ) ,. wea (wr1 ) ,. web(wr2 ) , . ena ( en ) , . enb ( en ) ) ;

// ‘ end i f

reg write bank ;reg t o g g l e r e g ;reg bank r ;reg v a l i d 1 r ;reg v a l i d 2 r ;always @ ( posedge c l k ) begin

bank r <= bank ;v a l i d 1 r <= va l i d1 ;v a l i d 2 r <= va l i d2 ;

end

assign bank d i r ty = ( bank r ? ( d i r t y2 & va l i d 2 r ) : ( d i r t y1 & va l i d 1 r ) ) ;

‘ i f n d e f s yn th e s i si n i t i a l t o g g l e r e g = 0 ;

‘ e nd i f

always @ ( posedge c l k )i f ( i n cache )

t o g g l e r e g <= ˜ t o g g l e r e g ;

always @ ( ∗ )i f (˜ va l i d1 )

wr i te bank = 1 ’ b0 ;else i f (˜ va l i d2 )

wr i te bank = 1 ’ b1 ;else

write bank = t o g g l e r e g ;endmodule

module tag mem c (ADDR, clk , TAG1, TAG2, va l id1 , va l id2 , update , update bank , ready , r s t ,ADDR OUT, en ) ;

input [ 3 1 : 0 ] ADDR;input c lk , update , update bank , r s t ;input en ;

46

output [ 1 4 : 0 ] TAG1, TAG2;output va l id1 , va l id2 , ready ;output [ 3 1 : 0 ] ADDR OUT;

//wire [ 2 0 : 0 ] RAM OUT1, RAM OUT2;wire [ 1 5 : 0 ] RAM OUT1, RAM OUT2;wire blanking ;reg [ 7 : 0 ] count ;wire [ 6 : 0 ] LINE = blanking ? count [ 6 : 0 ] : ADDR[ 1 1 : 5 ] ;

wire [ 1 3 : 0 ] TAG = ADDR[ 2 5 : 1 2 ] ;

wire wr1 , wr2 ;

assign ADDR OUT = {6 ’ b0 , update bank ? TAG2 [ 1 3 : 0 ] : TAG1[ 1 3 : 0 ] , LINE , 5 ’ b0 } ;

assign wr1 = (˜ update bank & update ) | | blanking ;

assign wr2 = ( update bank & update ) | | blanking ;

assign TAG1 = {RAM OUT1[ 1 5 : 1 ] } ; ////////////

assign TAG2 = {RAM OUT2[ 1 5 : 1 ] } ; ////////////

assign va l i d1 = RAM OUT1[ 1 5 ] ; ///////////assign va l i d2 = RAM OUT2[ 1 5 ] ; ///////////////

wire [ 1 5 : 0 ] TAG IN ;

// wire [ 2 0 : 0 ] TAG IN;

assign TAG IN = { blanking ? 0 : 1 , TAG, 1 ’ b0 } ;

assign ready = ˜ blanking ;

// ‘ i f n d e f s yn t h e s i s// RAMB4 S16 S16 block ram ( .DOA(RAM OUT1) , .DOB(RAM OUT2) , .ADDRA({1 ’ b0 , LINE})

, .ADDRB({1 ’ b1 , LINE}) ,// .CLKA( c l k ) , .CLKB( c l k ) , .DIA(TAG IN) , .DIB(TAG IN) , .ENA(1 ’ b1 ) , .ENB(1 ’ b1 )

, .RSTA(1 ’ b0 ) , .RSTB(1 ’ b0 ) , .WEA(wr1) , .WEB(wr2 ) ) ;// ‘ e l s e/∗

tag mem tagmem(. addra ({1 ’ b0 , LINE}) ,. addrb ({1 ’ b1 , LINE}) ,. c l k a ( c l k ) ,. c l k b ( c l k ) ,. dina (TAG IN) ,. dinb (TAG IN) ,. douta (RAM OUT1) ,. doutb (RAM OUT2) ,. wea(wr1 ) ,. web (wr2 ) ,. en ( en ) ) ;

∗//∗

tag mem bank1 (. addr (LINE) ,. c l k ( c l k ) ,. din (TAG IN) ,. dout (RAM OUT1) ,. we(wr1 ) , . en ( en | ˜ ready ) ) ;

tag mem bank2 (. addr (LINE) ,. c l k ( c l k ) ,. din (TAG IN) ,. dout (RAM OUT2) ,

47

. we(wr2 ) , . en ( en | ˜ ready ) ) ;∗/

tag mem 2 tagmem(. addra ({1 ’ b0 , LINE}) ,. addrb ({1 ’ b1 , LINE}) ,. c l ka ( c l k ) ,. c lkb ( c l k ) ,. dina (TAG IN) ,. dinb (TAG IN) ,. douta (RAM OUT1) ,. doutb (RAM OUT2) ,. ena ( en | ˜ ready ) ,. enb ( en | ˜ ready ) ,. wea (wr1 ) ,. web(wr2 ) ) ;

// ‘ end i f

‘ i f n d e f s yn th e s i salways @ ( posedge c l k ) begin

i f ( update )i f ( ( va l i d1 && ˜update bank ) | | ( va l i d2 && update bank ) )

$d i sp l ay ( ”Time: %d Replac ing va l i d entry at addr : %xwith addr : %x in l i n e : %x , bank: %d” , $time ,

ADDR OUT, ADDR, LINE , update bank ) ;else

$d i sp l ay ( ”Time: %d Bringing in addr : %x to l i n e : %x, bank: %d” , $time , ADDR, LINE , update bank ) ;

end‘ e nd i f

always @ ( posedge c l k )i f ( r s t )

count <= 0;else i f ( b lanking )

count <= count + 1 ;

assign blanking = ( count != 128) ;

endmodule

‘ t ime s ca l e 1 ns / 1 ps

/∗ ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ This f i l e i s owned and con t r o l l e d by Xi l inx and must be used ∗∗ s o l e l y f o r design , s imulat ion , implementation and crea t i on o f ∗∗ des ign f i l e s l im i t e d to Xi l inx dev i c e s or t e c hno l o g i e s . Use ∗∗ with non−Xi l inx dev i c e s or t e c hno l o g i e s i s e x p r e s s l y p r oh i b i t e d ∗∗ and immediate ly terminates your l i c e n s e . ∗∗ ∗∗ XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ”AS IS ” ∗∗ SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR ∗∗ XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION ∗∗ AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION ∗∗ OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS ∗∗ IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ∗∗ AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ∗∗ FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ∗∗ WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ∗∗ IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ∗∗ REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ∗∗ INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ∗∗ FOR A PARTICULAR PURPOSE. ∗∗ ∗

48

∗ Xi l inx products are not intended fo r use in l i f e support ∗∗ app l iances , dev ices , or systems . Use in such app l i c a t i o n s are ∗∗ e x p r e s s l y p r oh i b i t e d . ∗∗ ∗∗ ( c ) Copyright 1995−2003 Xi l inx , Inc . ∗∗ Al l r i g h t s re served . ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ∗/// The synopsys d i r e c t i v e s ” t r a n s l a t e o f f / t r an s l a t e on ” s p e c i f i e d// below are supported by XST, FPGA Compiler II , Mentor Graphics and Synp l i c i t y// s yn t h e s i s t o o l s . Ensure they are cor r ec t f o r your s yn t h e s i s t o o l ( s ) .

// You must compile the wrapper f i l e dirty mem . v when s imu la t ing// the core , dirty mem . When compi l ing the wrapper f i l e , be sure to// re f e r ence the Xi l inxCoreLib Ver i l og s imu la t ion l i b r a r y . For d e t a i l e d// in s t ru c t i on s , p l ea s e r e f e r to the ”CORE Generator Guide ” .

module dirty mem (addra ,addrb ,c lka ,clkb ,dina ,dinb ,douta ,doutb ,ena ,enb ,wea ,web) ; // s yn t h e s i s b l a c k box

input [ 7 : 0 ] addra ;input [ 7 : 0 ] addrb ;input c lka ;input c lkb ;input [ 0 : 0 ] dina ;input [ 0 : 0 ] dinb ;output [ 0 : 0 ] douta ;output [ 0 : 0 ] doutb ;input ena ;input enb ;input wea ;input web ;

// synopsys t r a n s l a t e o f f

BLKMEMDP V5 0 #(8 , // c addra wid th8 , // c addrb wid th”0” , // c d e f a u l t d a t a256 , // c dep th a256 , // c dep th b0 , // c e n a b l e r l o c s1 , // c h a s d e f a u l t d a t a1 , // c has d ina1 , // c has d inb1 , // c has douta1 , // c has dou tb1 , // c has ena1 , // c has enb0 , // c h a s l im i t d a t a p i t c h0 , // c has nda0 , // c has ndb0 , // c has rdya0 , // c has rdyb0 , // c ha s r f da0 , // c ha s r f d b0 , // c h a s s i n i t a0 , // c h a s s i n i t b

49

1 , // c has wea1 , // c has web18 , // c l im i t d a t a p i t c h” m i f f i l e 1 6 1 ” , // c mem in i t f i l e0 , // c p i p e s t a g e s a0 , // c p i p e s t a g e s b0 , // c r e g i npu t s a0 , // c r e g i npu t s b”0” , // c s i n i t a v a l u e”0” , // c s i n i t b v a l u e1 , // c wid th a1 , // c w id th b0 , // c write modea0 , // c wri te modeb”0” , // c ybot tom addr1 , // c y c l k a i s r i s i n g1 , // c y c l k b i s r i s i n g1 , // c y ena i s h i g h1 , // c y en b i s h i g h” h i e ra rchy1 ” , // c yh i e rarchy0 , // c ymake bmm”4kx1” , // c y p r im i t i v e t y p e1 , // c y s i n i t a i s h i g h1 , // c y s i n i t b i s h i g h”1024” , // c y top addr0 , // c y u s e s i n g l e p r im i t i v e1 , // c ywea i s h i g h1) // c yweb i s h i g h

i n s t (.ADDRA( addra ) ,.ADDRB( addrb ) ,.CLKA( c lka ) ,.CLKB( c lkb ) ,.DINA( dina ) ,.DINB( dinb ) ,.DOUTA( douta ) ,.DOUTB( doutb ) ,.ENA( ena ) ,.ENB( enb ) ,.WEA(wea ) ,.WEB(web) ,.NDA( ) ,.NDB( ) ,.RFDA( ) ,.RFDB( ) ,.RDYA() ,.RDYB( ) ,. SINITA( ) ,. SINITB ( ) ) ;

// synopsys t r an s l a t e on

endmodule

A.10 Instruction Memory

// $Header : v :\\CVSLab3/ lab6 /imem. v , v 1 .1 2004/05/02 05 :54 :39 cs152−ah Exp $// $Author : cs152−ah $// $Date : 2004/05/02 05 :54 :39 $‘ d e f i n e WAIT 3 ’ b00‘ d e f i n e READY 3 ’ b01‘ d e f i n e HANDLE MISS 3 ’ b10‘ d e f i n e REDO READ 3 ’ b11‘ d e f i n e PUSH ID 3 ’ b100

‘ t ime s ca l e 1 ns /1ps

50

module imem( clk , r s t ,ADDRESS, DOUT,

i cache mis s ,DRAM DIN, DRAMADDR,dram read , dram ready , p i p e l i n e s t a l l , branch mispred ict , l a t c h i d ) ;

input c lk , r s t ;input p i p e l i n e s t a l l , b ranch mispred i c t ;

// In s t r u c t i on Memory Proper In t e r f a c einput [ 3 1 : 0 ] ADDRESS;output [ 3 1 : 0 ] DOUT;

output i c a che m i s s ;

output l a t c h i d ;

//Lines to /from SDRAM in the TopLeveloutput [ 3 1 : 0 ] DRAMADDR;

input [ 2 5 5 : 0 ] DRAM DIN;output dram read ;input dram ready ;

reg mis s i d ;

reg [ 3 1 : 0 ] ACTUAL ADDR; //Actual address in to cachesassign DRAMADDR = ACTUAL ADDR;

reg [ 2 : 0 ] STATE, NS;reg [ 3 1 : 0 ] ADDRESS R, ADDRESS ID ;

reg l a t c h i d ;reg dram read ;reg i c a che m i s s ;

wire [ 3 1 : 0 ] DOUT sram , DOUT boot0 ;

boot0rom boot0 ( . c l k ( c l k ) , . addr ({2 ’ b0 , ACTUAL ADDR[ 7 : 2 ] } ) , . dout (DOUT boot0) ) ;

wire i c a che mi s s raw ;

wire i c a che r eady ;

i ca che i c ( . c l k ( c l k ) , . r s t ( r s t ) , . en (˜ACTUAL ADDR[ 3 1 ] ) , .PC(ACTUAL ADDR), . INSTRUCTION(DOUT sram) , . cache miss ( i cache mi s s raw ) ,.DIN MEM(DRAM DIN) , . ready mem( dram ready ) , . i c a che r eady ( i ca che r eady ) ) ;

reg selBoot0 CLKED ;

always @ ( posedge c l k )selBoot0 CLKED <= ACTUAL ADDR[ 3 1 ] ;

assign DOUT = selBoot0 CLKED ? DOUT boot0 : DOUT sram ;

// Sta te Logicalways @ ( posedge c l k )

i f ( r s t )STATE <= ‘WAIT;

elseSTATE <= NS;

//Delayed cache miss s i g n a lalways @ ( posedge c l k )

51

i f ( r s t | | branch mispred i c t | | dram ready )mi s s i d <= 1’b0 ;

else i f (˜ p i p e l i n e s t a l l )m i s s i d <= icache mi s s raw ;

//Address p i p e l i n ealways @ ( posedge c l k )

i f (˜ i c a che m i s s && ˜ p i p e l i n e s t a l l ) beginADDRESS R <= ADDRESS;ADDRESS ID <= ADDRESS R;

end//Next s t a t e l o g i calways @ ( ∗ )

case (STATE)‘WAIT: begin

i f ( i c a che r eady )NS = ‘READY;

elseNS = ‘WAIT;

end‘READY: begin

i f ( m i s s i d && ˜ branch mispred i c t ) // i f branch mispred ic t ion ,i n s t r u c t i on in ID zero ’ d anyways

NS = ‘HANDLE MISS;else

NS = ‘READY;end‘HANDLE MISS : begin

i f ( dram ready )NS = ‘REDO READ;

elseNS = ‘HANDLE MISS;

end‘REDO READ: begin

NS = ‘PUSH ID ;end‘PUSH ID : begin

NS = ‘READY;enddefault : begin

NS = ‘READY;endendcase

//Output l o g i calways @ ( ∗ ) begin

i c a che m i s s = 0 ;dram read = 0 ;l a t c h i d = 0 ;ACTUAL ADDR = ADDRESS;case (STATE)‘WAIT: begin

i c a che m i s s = 1 ;end‘READY:

i f ( m i s s i d && ˜ branch mispred i c t ) begini c a che m i s s = 1 ;dram read = 1 ;ACTUAL ADDR = ADDRESS ID ;

end elseACTUAL ADDR = ADDRESS;

‘HANDLE MISS : begini f ( dram ready ) begin

i c a che m i s s = 1 ;ACTUAL ADDR = ADDRESS ID ;

end else begini c a che m i s s = 1 ;

52

dram read = 1 ;ACTUAL ADDR = ADDRESS ID ;

endend‘REDO READ: begin

ACTUAL ADDR = ADDRESS ID ;i c a che m i s s = 1 ;

end‘PUSH ID : begin

i c a che m i s s = 1 ;ACTUAL ADDR = ADDRESS;l a t c h i d = 1 ;

endendcase

end

endmodule

// $Header : v :\\CVSLab3/ lab6 / icache . v , v 1 .2 2004/05/08 00 :42 :52 cs152−ah Exp $// $Author : cs152−ah $// $Date : 2004/05/08 00 :42 :52 $

‘ t ime s ca l e 1 ns / 10 ps

‘ d e f i n e RESETTING 1 ’ b0‘ d e f i n e IDLE 1 ’ b1

module i c a che ( c lk , r s t , en , PC, INSTRUCTION, cache miss , DIN MEM, ready mem , i cache r eady ) ;input c lk , r s t , en ;

input [ 3 1 : 0 ] PC;

wire [ 1 8 : 0 ] PC TAG = PC[ 3 1 : 1 3 ] ;wire [ 7 : 0 ] PC INDEX = PC[ 1 2 : 5 ] ;wire [ 2 : 0 ] PC BLOCK OFFSET = PC[ 4 : 2 ] ;

// p i p e l i n e d enab le and tagreg en ;

always@ (posedge c l k ) en <= en ;reg [ 1 8 : 0 ] t ag ;

always@ (posedge c l k ) tag <= PC TAG;

// datapath <−> cache i n t e r f a c e

output [ 3 1 : 0 ] INSTRUCTION;output cache miss ;

output i c a che r eady ;

//memory <−> cache i n t e r f a c einput [ 2 5 5 : 0 ] DIN MEM;input ready mem ;

wire va l i d ;wire [ 1 8 : 0 ] tag ;

assign cache miss = en && !( va l i d && ( tag == tag ) ) ;

//when we are w r i t t i n g to the cache tag memory , we e i t h e r wr i t e v a l i d 0 ( r e s e t t i n g ) orv a l i d 1 ( cache f i l l )

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wire wr i t e t a g v a l i d ;wire wr i t e t a g ;wire [ 7 : 0 ] rstAddr ;wire [ 7 : 0 ] tagAddr = wr i t e t a g v a l i d ? PC INDEX : rstAddr ;

wire doneRst ;

// cache l i n e sicache mem l i n e s ( . addra ({PC INDEX, PC BLOCK OFFSET}) , . addrb (PC INDEX) ,

. c l ka ( c l k ) , . c lkb ( c l k ) ,

. dinb (DIN MEM) , . web( ready mem) ,. douta (INSTRUCTION) , . ena (˜ ready mem) ) ;

// cache tag si c a c h e t a g s tags ( . addr ( tagAddr ) , . c l k ( c l k ) ,

. din ({ wr i t e t a g va l i d , PC TAG}) , . we( wr i t e t a g ) ,

. dout ({ va l id , tag }) ) ;

// cache r e s e t t e ri c a c h e t a g r s t c n t r r s t c n t ( .Q( rstAddr ) , .CLK( c l k ) ,

.LOAD( r s t ) , . L(8 ’ b0 ) ,.Q THRESH1( doneRst ) ) ;

reg cont ro lS ta t e , nextState ;

always@ (posedge c l k )c on t r o l S t a t e <= r s t ? ‘RESETTING : nextState ;

// next s t a t e l o g i calways@ (∗ )

case ( c on t r o l S t a t e )‘RESETTING: nextState = doneRst ? ‘ IDLE : ‘RESETTING;‘IDLE : nextState = ‘IDLE ;endcase

// output l o g i cassign wr i t e t a g v a l i d = con t r o l S t a t e != ‘RESETTING;assign i c a che r eady = wr i t e t a g v a l i d ;assign wr i t e t a g = ( con t r o l S t a t e == ‘RESETTING) | | ready mem ;

endmodule

A.11 SDRAM Control

//The ID of a command to the SDRAM i s i t s {CS, RAS, CAS, WE} s i g n a l s e t‘ d e f i n e NOP 4 ’ b1000‘ d e f i n e PRECHARGE 4 ’ b0010‘ d e f i n e AUTOREFRESH 4 ’ b0001‘ d e f i n e LMR 4 ’ b0000‘ d e f i n e ACTIVE 4 ’ b0011‘ d e f i n e WRITE 4 ’ b0100‘ d e f i n e READ 4 ’ b0101

//We e i t h e r are wr i t ing , reading , r e f r e sh ing , i n i n i t i a l z i n g , or sending nops to SDRAM‘ d e f i n e SDRAM WRITE 4 ’ b1000‘ d e f i n e SDRAM READ 4 ’ b0100‘ d e f i n e SDRAM INIT 4 ’ b0010‘ d e f i n e SDRAM REFRESH 4 ’ b0001‘ d e f i n e SDRAM NOPS 4 ’ b0000

//Mode Reg i s t e r : reserved , burs t , standard , CAS=2 , s e q u en t i a l burs t , bu r s t l en g t h=8‘ d e f i n e MODE REGISTER 13 ’ b000 0 00 010 0 011

‘ d e f i n e CYCLES TO REFRESH 400

// Con t ro l l e r S ta t e s‘ d e f i n e STATE START 3 ’ b000

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‘ d e f i n e STATE IDLE 3 ’ b001‘ d e f i n e STATE INIT 3 ’ b010‘ d e f i n e STATE READ 3 ’ b011‘ d e f i n e STATE WRITE 3 ’ b100‘ d e f i n e STATE REFRESH 3 ’ b101‘ d e f i n e STATE RW DONE 3 ’ b110

//Cycles For Sequencers‘ d e f i n e INIT TIME 4 ’ d12‘ d e f i n e WRITE TIME 4 ’ d11‘ d e f i n e READ TIME 4 ’ d10‘ d e f i n e REFRESH TIME 4 ’ d5

//uPC Of f s e t s‘ d e f i n e IDLE BASE 13‘ d e f i n e REFRESH BASE 14‘ d e f i n e READ BASE 20‘ d e f i n e WRITE BASE 32

//RAM Addressing‘ d e f i n e RAMA PRE 2 ’ b00‘ d e f i n e RAMALMR 2 ’ b01‘ d e f i n e RAMAROW 2 ’ b10‘ d e f i n e RAMA COL 2 ’ b11

//Constants‘ d e f i n e DO DISPATCH 1 ’ b1‘ d e f i n e RET IDLE 1 ’ b1‘ d e f i n e RST REFRESH CNT 1 ’ b1‘ d e f i n e SHIFT 1 ’ b1‘ d e f i n e WAIT ACK 1 ’ b1‘ d e f i n e LOAD SHIFTER 1 ’ b1

//uRAM Macros‘ d e f i n e uROM NOP {1 ’b0 , ‘NOP, 9 ’ b0}‘ d e f i n e uROMPRECHARGE {1 ’b0 , ‘PRECHARGE, 2 ’ b00 , 7 ’ b0}‘ d e f i n e uROM AUTOREFRESH {1 ’b0 , ‘AUTOREFRESH, 9 ’ b0}‘ d e f i n e uROM LMR {1 ’b0 , ‘LMR, ‘RAMALMR, 7 ’ b0}‘ d e f i n e uROM DISPATCH {1 ’b0 , ‘NOP, 8 ’ b0 , ‘DO DISPATCH}‘ d e f i n e uROM DONE REFRESH {1 ’b0 , ‘NOP, 4 ’ b0 , ‘RST REFRESH CNT, 2 ’ b0 , ‘ RET IDLE

, 1 ’ b0}

‘ d e f i n e uROM ACTIVE READ {1 ’b0 , ‘ACTIVE, ‘RAMAROW, 7 ’ b0}‘ d e f i n e uROM READ CMD {1 ’b0 , ‘READ, ‘RAMA COL, 7 ’ b0}‘ d e f i n e uROM NOP READ SHIFT {1 ’b0 , ‘NOP, 3 ’ b0 , ‘ SHIFT , 5 ’ b0}‘ d e f i n e uROM WAIT ACK {1 ’b0 , ‘NOP, 6 ’ b0 , ‘WAIT ACK, 2 ’ b0}

‘ d e f i n e uROM ACTIVE WRITE {1 ’b1 , ‘ACTIVE, ‘RAMAROW, 3 ’ b0 , ‘ LOAD SHIFTER, 3 ’ b0}‘ d e f i n e uROM WRITE CMD {1 ’b1 , ‘WRITE, ‘RAMA COL, ‘ SHIFT , 6 ’ b0}‘ d e f i n e uROM NOP WRITE SHIFT {1 ’ b1 , ‘NOP, 2 ’ b0 , ‘ SHIFT , 6 ’ b0}‘ d e f i n e uROM NOP WRITE {1 ’b1 , ‘NOP, 9 ’ b0}

//For Test ing Purposes‘ d e f i n e SDRAM REFRESH ENABLE‘ d e f i n e SDRAMDEBUG

// $Header : v :\\CVSLab3/ lab6 /sdramControl . v , v 1 .1 2004/05/07 01 :38 :24 cs152−ah Exp $// $Author : cs152−ah $// $Date : 2004/05/07 01 :38 :24 $

‘ t ime s ca l e 1 ns / 1 ps

‘ include ”sdramCommandDef . v”

module sdramContro l l e r ( sdrcClk , r s t ,

RAM DQ ,

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RAM CLK ,RAM CLKE ,RAM DQMH ,RAM DQML ,RAM CS ,RAM RAS ,RAM CAS ,RAM WE ,RAM BA ,RAM A ,

ADDRESS,write , read , ack ,ready ,

DIN , DOUT) ;

input sdrcClk , r s t ;

inout [ 3 1 : 0 ] RAM DQ ;output RAM CLK ;output RAM CLKE ;output RAM DQMH ;output RAM DQML ;output RAM CS ;output RAM RAS ;output RAM CAS ;output RAM WE ;output [ 1 : 0 ] RAM BA ;output [ 1 2 : 0 ] RAM A ;reg [ 1 2 : 0 ] RAM A ;

input [ 3 1 : 0 ] ADDRESS;

input write , read , ack ;output ready ; reg ready ;

input [ 2 5 5 : 0 ] DIN ;output [ 2 5 5 : 0 ] DOUT;

// crea t e SDRAM c lockassign RAM CLK = ˜ sdrcClk ;assign RAM CLKE = 1 ’ b1 ;

// t r i s t a t e f o r RAM DQwire [ 3 1 : 0 ] OUT TO SDR;wire ou t t o sd r en ; //∗Set by c o n t r o l l e r

t r i S t a t e t s ( . triOUT(RAM DQ ) , . t r i IN (OUT TO SDR) , . enOUT( ou t t o sd r en ) ) ;

// d f f f o r IN FROM SDRreg [ 3 1 : 0 ] IN FROM SDR;

always@ (posedge RAM CLK )i f ( r s t )

IN FROM SDR <= 32 ’b0 ;else

IN FROM SDR <= RAM DQ ;

// constant SDRAM DQMassign RAM DQML = 1 ’ b0 ;assign RAM DQMH = 1 ’ b0 ;

//Writing to Memory S h i f t e rreg [ 2 5 5 : 0 ] toMemShifter ;wire l o adSh i f t e r , shi ftToMemShifter ;

always@ (posedge sdrcClk )

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i f ( r s t )toMemShifter <= 256 ’b0 ;

else i f ( l o a dSh i f t e r )toMemShifter <= DIN ;

else i f ( shi ftToMemShifter )toMemShifter <= { toMemShifter [ 2 2 3 : 0 ] , 3 2 ’ b0 } ;

assign OUT TO SDR = toMemShifter [ 2 5 5 : 2 2 4 ] ;

//Reading from Memory S h i f t e rreg [ 2 5 5 : 0 ] fromMemShifter ;assign DOUT = fromMemShifter ;wire shiftFromMemShifter ;

always@ (posedge sdrcClk )i f ( r s t )

fromMemShifter <= 256 ’b0 ;else i f ( shiftFromMemShifter )

fromMemShifter <= { fromMemShifter [ 2 2 3 : 0 ] , IN FROM SDR} ;

// address ingassign RAM BA = ADDRESS[ 2 5 : 2 4 ] ;wire [ 1 2 : 0 ] SDR ROW = ADDRESS[ 2 3 : 1 1 ] ;wire [ 8 : 0 ] SDR COLUMN = {ADDRESS[ 1 0 : 5 ] , 3 ’ b0 } ; //Aligned on a 8 word boundary

wire [ 1 : 0 ] ramCommand ;

always@ (ramCommand or SDR ROW or SDR COLUMN)case (ramCommand)‘RAMA PRE: RAM A = 13 ’ b0010000000000 ;‘RAMALMR: RAM A = ‘MODE REGISTER;‘RAMAROW: RAM A = SDR ROW;‘RAMA COL: RAM A = {4 ’ b0010 , SDR COLUMN} ; // wr i t e with auto prechargeendcase

// r e f r e s h counter‘ i f d e f SDRAM REFRESH ENABLEreg doRefresh ;wire [ 8 : 0 ] t imeTi l lNextRe f re sh ;wire needRefresh ;

wire doneRefresh ;

sd ram re f cn t t tn r ( .Q( t imeTi l lNextRe f re sh ) , .CLK( sdrcClk ) , .Q THRESH0( needRefresh ) , .SINIT ( r s t | needRefresh ) ) ;

always@ (posedge sdrcClk )i f ( r s t )

doRefresh <= 4’b0 ;else

case ({ needRefresh , doneRefresh })2 ’ b00 : begin

doRefresh <= doRefresh ;end

2 ’ b01 : begindoRefresh <= 1’b0 ; //missedRefreshes − 1;

// s yn t h e s i s t r a n s l a t e o f f‘ i f d e f SDRAMDEBUG#1 $d i sp l ay ( $time , ” SDRAM Refreshed , mis sedRef re shes = %d” , doRefresh ) ;‘ e nd i f// s yn t h e s i s t r an s l a t e on

end2 ’ b10 : begin

doRefresh <= 1’b1 ; //missedRefreshes + 1;

// s yn t h e s i s t r a n s l a t e o f f‘ i f d e f SDRAMDEBUG#1 $d i sp l ay ( $time , ” SDRAM Refresh Missed , mis sedRef re shes = %d” ,

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doRefresh ) ;‘ e nd i f// s yn t h e s i s t r an s l a t e on

end2 ’ b11 : begin

doRefresh <= 1’b1 ; //missedRefreshes ;

// s yn t h e s i s t r a n s l a t e o f f‘ i f d e f SDRAMDEBUG#1 $d i sp l ay ( $time , ” SDRAM Refreshed , mis sedRef re shes = %d” , doRefresh ) ;‘ e nd i f// s yn t h e s i s t r an s l a t e on

endendcase

‘ elsewire doRefresh = 1 ’ b0 ;‘ e nd i f

// synchron i za t ion o f r eque s t s i g n a l sreg read0 , write0 , ack0 ;reg sread , swr i te , sack ;always@ (posedge sdrcClk )

beginwr i te0 <= wr i t e ;read0 <= read ;ack0 <= ack ;

swr i t e <= wri te0 ;s read <= read0 ;sack <= ack0 ;

end

wire sready ; //∗Set by c o n t r o l l e r// synchron i za t ion o f ready s i g n a lalways@ (posedge sdrcClk )

ready <= sready ;

//main c o n t r o l l e r// con t ro l l i n e muxesreg [ 5 : 0 ] uPC;reg [ 5 : 0 ] next uPC ;

always@ (posedge sdrcClk )i f ( r s t )

uPC <= 6’b0 ;else

uPC <= next uPC ;

wire [ 1 3 : 0 ] c o n t r o l S i g s ;

wire waitAck ; assign sready = waitAck ;wire r e t I d l e ;wire d i spatch ;

always@ (∗ )casex ({waitAck , r e t I d l e , d ispatch , doRefresh , sread , swr i t e })6 ’ b1xxxxx : next uPC = sack ? ‘ IDLE BASE : uPC;6 ’ b01xxxx : next uPC = ‘IDLE BASE ;6 ’ b0011xx : next uPC = ‘REFRESH BASE;6 ’ b00101x : next uPC = ‘READ BASE;6 ’ b001001 : next uPC = ‘WRITE BASE;6 ’ b001000 : next uPC = uPC;default : next uPC = uPC + 1;endcase

assign ou t t o sd r en = con t r o l S i g s [ 1 3 ] ;assign {RAM CS , RAM RAS , RAM CAS , RAM WE } = con t r o l S i g s [ 1 2 : 9 ] ;

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assign ramCommand = con t r o l S i g s [ 8 : 7 ] ;assign shi ftToMemShifter = con t r o l S i g s [ 6 ] ;assign shiftFromMemShifter = con t r o l S i g s [ 5 ] ;assign doneRefresh = con t r o l S i g s [ 4 ] ;assign l o a dSh i f t e r = con t r o l S i g s [ 3 ] ;assign {waitAck , r e t I d l e , d i spatch } = con t r o l S i g s [ 2 : 0 ] ;

uROM ur (uPC, c on t r o l S i g s ) ;endmodule

module t r i S t a t e ( triOUT , tr i IN , enOUT) ;output [ 3 1 : 0 ] triOUT ;input [ 3 1 : 0 ] t r i IN ;input enOUT;

reg [ 3 1 : 0 ] triOUT ;

always@ (enOUT or t r i IN )i f (enOUT)

triOUT = tr i IN ;else

triOUT = 32 ’bZ ;endmodulemodule uROM(uPC, c on t r o l S i g s ) ;

input [ 5 : 0 ] uPC;output [ 1 3 : 0 ] c o n t r o l S i g s ;reg [ 1 3 : 0 ] c o n t r o l S i g s ;

always@ (uPC)case (uPC)

6 ’ d0 : c on t r o l S i g s = ‘uROM NOP;

// I n i t i a l i z e and Load Mode Reg i s t e r S ta t e s6 ’ d1 : c on t r o l S i g s = ‘uROMPRECHARGE;6 ’ d2 : c on t r o l S i g s = ‘uROM AUTOREFRESH;6 ’ d6 : c on t r o l S i g s = ‘uROM AUTOREFRESH;6 ’ d10 : c on t r o l S i g s = ‘uROM LMR;

//Dispatch/IDLE Sta t e s6 ’ d13 : c on t r o l S i g s = ‘uROM DISPATCH;

//AutoRefresh S ta t e s6 ’ d14 : c on t r o l S i g s = ‘uROMPRECHARGE;6 ’ d15 : c on t r o l S i g s = ‘uROM AUTOREFRESH;6 ’ d19 : c on t r o l S i g s = ‘uROM DONE REFRESH;

//Read S ta t e s6 ’ d20 : c on t r o l S i g s = ‘uROM ACTIVE READ;6 ’ d21 : c on t r o l S i g s = ‘uROM READ CMD;6 ’ d23 : c on t r o l S i g s = ‘uROM NOP READ SHIFT;6 ’ d24 : c on t r o l S i g s = ‘uROM NOP READ SHIFT;6 ’ d25 : c on t r o l S i g s = ‘uROM NOP READ SHIFT;6 ’ d26 : c on t r o l S i g s = ‘uROM NOP READ SHIFT;6 ’ d27 : c on t r o l S i g s = ‘uROM NOP READ SHIFT;6 ’ d28 : c on t r o l S i g s = ‘uROM NOP READ SHIFT;6 ’ d29 : c on t r o l S i g s = ‘uROM NOP READ SHIFT;6 ’ d30 : c on t r o l S i g s = ‘uROM NOP READ SHIFT;6 ’ d31 : c on t r o l S i g s = ‘uROM WAIT ACK;

//Write S ta t e s6 ’ d32 : c on t r o l S i g s = ‘uROM ACTIVE WRITE;6 ’ d33 : c on t r o l S i g s = ‘uROM WRITE CMD;6 ’ d34 : c on t r o l S i g s = ‘uROM NOP WRITE SHIFT;6 ’ d35 : c on t r o l S i g s = ‘uROM NOP WRITE SHIFT;6 ’ d36 : c on t r o l S i g s = ‘uROM NOP WRITE SHIFT;6 ’ d37 : c on t r o l S i g s = ‘uROM NOP WRITE SHIFT;6 ’ d38 : c on t r o l S i g s = ‘uROM NOP WRITE SHIFT;6 ’ d39 : c on t r o l S i g s = ‘uROM NOP WRITE SHIFT;

59

6 ’ d40 : c on t r o l S i g s = ‘uROM NOP WRITE SHIFT;6 ’ d41 : c on t r o l S i g s = ‘uROM NOP WRITE;6 ’ d42 : c on t r o l S i g s = ‘uROM NOP WRITE;6 ’ d43 : c on t r o l S i g s = ‘uROM NOP WRITE;6 ’ d44 : c on t r o l S i g s = ‘uROM WAIT ACK;

6 ’ d45 : c on t r o l S i g s = ‘uROM NOP;6 ’ d46 : c on t r o l S i g s = ‘uROM NOP;6 ’ d47 : c on t r o l S i g s = ‘uROM NOP;6 ’ d48 : c on t r o l S i g s = ‘uROM NOP;6 ’ d49 : c on t r o l S i g s = ‘uROM NOP;6 ’ d50 : c on t r o l S i g s = ‘uROM NOP;6 ’ d51 : c on t r o l S i g s = ‘uROM NOP;6 ’ d52 : c on t r o l S i g s = ‘uROM NOP;6 ’ d53 : c on t r o l S i g s = ‘uROM NOP;6 ’ d54 : c on t r o l S i g s = ‘uROM NOP;6 ’ d55 : c on t r o l S i g s = ‘uROM NOP;6 ’ d56 : c on t r o l S i g s = ‘uROM NOP;6 ’ d57 : c on t r o l S i g s = ‘uROM NOP;6 ’ d58 : c on t r o l S i g s = ‘uROM NOP;6 ’ d59 : c on t r o l S i g s = ‘uROM NOP;6 ’ d60 : c on t r o l S i g s = ‘uROM NOP;6 ’ d61 : c on t r o l S i g s = ‘uROM NOP;6 ’ d62 : c on t r o l S i g s = ‘uROM NOP;6 ’ d63 : c on t r o l S i g s = ‘uROM NOP;

default : c o n t r o l S i g s = ‘uROM NOP;endcase

endmodule

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