Cs2100 8 Sequential Logic

CS2100 Computer Organisation

Sequential Logic

2011 Sem 1 Sequential Logic 2

SEQUENTIAL LOGIC

➤ Memory Elements➤ Latches: S-R Latch, D Latch➤ Flip-flops: S-R flip-flop, D flip-flop, J-K flip-flops, T flip-flops➤ Asynchronous Inputs➤ Finite State Machines➤ Memory➤ Memory Unit➤ Read/Write Operations➤ Memory Arrays


INTRODUCTION (1/2)

➤ Two classes of logic circuits– Combinational– Sequential

➤ Combinational Circuit– Each output depends entirely

on the immediate (present) inputs.

CombinationalLogic: :inputs outputs: :

➤ Sequential Circuit– Each output depends on both

present inputs and state.

Memory

CombinationalLogic: :inputs outputs: :


INTRODUCTION (2/2)

➤ Two types of sequential circuits:– Synchronous: outputs change only at specific time– Asynchronous: outputs change at any time

➤ Multivibrator: a class of sequential circuits– Bistable (2 stable states)– Monostable or one-shot (1 stable state)– Astable (no stable state)

➤ Bistable logic devices– Latches and flip-flops.– They differ in the methods used for changing their state.


MEMORY ELEMENTS (1/3)

➤ Memory element: a device which can remember value indefinitely, or change value on command from its inputs.

command Memory element stored value

Q

➤ Characteristic table:

Command(at time t)

Q(t) Q(t+1)

Set X 1

Reset X 0

0 0Memorise /No Change 1 1

Q(t) or Q: current state

Q(t+1) or Q+: next state



➤ Memory element with clock.

➤ Clock is usually a square wave.


Q

clock

Positive edges Negative edges

Positive pulses Clock period

If clock period is x seconds, then the clock frequency (or rate) is 1/x Hz. For example, a 2 GHz PC has a clock period of 0.5 nanosecond.



➤ Memory element with clock.

➤ Clock is usually a square wave.


Q

clock


Positive pulses Clock period

The speed of light in vacuum is about 3 x 108 metres per second. In half a nanosecond, light travels 15 cm.



➤ Two types of triggering/activation– Pulse-triggered– Edge-triggered

➤ Pulse-triggered– Latches– ON = 1, OFF = 0

➤ Edge-triggered– Flip-flops– Positive edge-triggered (ON = from 0 to 1; OFF = other time)– Negative edge-triggered (ON = from 1 to 0; OFF = other time)


Positive pulses


FINITE STATE MACHINES

➤ Built with combinational logic and memory (stores the state)

➤ Next state depends on current state and inputs➤ Many computations can be specified as FSMs➤ Example: counter

ELEMENTS OF A FSM

➤ A finite set of states– One of the state is a special “START” state– Zero or more of the states are “FINAL” state– States are related to one another by state

transitions

➤ A finite set of inputs➤ A finite set of outputs


EXAMPLE


B E W P

D

Born Education Work Play

R

Retire

Death

Heart attack

Bored

BoredA

ge =

= 65

Age == 6 GraduateLeave == 0

Vacation over

Start State

Final State

State

State Transition

Input

12

A: X = current_mouse_position();

B: X = current_mouse_position();Draw line from X to Y;

C: Act on line input;

FSM control for rubber banding

Press / A

Move / B

Release / C


USE CASE EXAMPLE

➤ Two output signals:– NSlite: When this signal is asserted, the light on the north-south road is

green; when this signal is deasserted the light on the north-south road is red.

– EWlite: When this signal is asserted, the light on the east-west road is green; when this signal is deasserted the light on the east-west road is red.

➤ Two inputs: NScar and EWcar.– NScar: Indicates that a car is over the detector placed in the roadbed in

front of the light on the north-south road (going north or south).– EWcar: Indicates that a car is over the detector placed in the roadbed in

front of the light on the east-west road (going east or west).➤ The traffic light should change from one direction to the other only if

a car is waiting to go in the other direction; otherwise, the light should continue to show green in the same direction as the last car that crossed the intersection.


STATE DIAGRAM

Two states:

• NSgreen: The traffic light is green in the north-south direction

• EWgreen: The traffic light is green in the east-west direction

Memory elements



S-R LATCH (1/3)

➤ Two inputs: S and R.➤ Two complementary outputs: Q and Q'.

– When Q = HIGH, we say latch is in SET state.– When Q = LOW, we say latch is in RESET state.

➤ For active-high input S-R latch (also known as NOR gate latch)– R = HIGH and S = LOW Q becomes LOW (RESET state)– S = HIGH and R = LOW Q becomes HIGH (SET state)– Both R and S are LOW No change in output Q – Both R and S are HIGH Outputs Q and Q' are both LOW

(invalid!)

➤ Drawback: invalid condition exists and must be avoided.


S-R LATCH (2/3)

➤ Active-high input S-R latch:

R

S

Q

Q'

S R Q Q'1 0 1 0 initial0 0 1 0 (afer S=1, R=0)0 1 0 10 0 0 1 (after S=0, R=1)1 1 0 0 invalid!

1

0

0

1

1

0

0

0

0

1

1

0

0

1

0

0

1

1

0

0

S

R

Q

Q'

➤ Block diagram:


S-R LATCH (3/3)

➤ Characteristic table for active-high input S-R latch:

S R Q Q'

0 0 NC NC No change. Latchremained in present state.

1 0 1 0 Latch SET.

0 1 0 1 Latch RESET.

1 1 0 0 Invalid condition.

S

R

Q

Q'

S R Q(t+1)

0 0 Q(t) No change

0 1 0 Reset

1 0 1 Set

1 1 indeterminate

Q(t+1) = S + R'Q

SR = 0


GATED S-R LATCH

➤ S-R latch + enable input (EN) and 2 NAND gates a gated S-R latch.

S

R

Q

Q'

EN

S

EN

R

Q

Q'

➤ Outputs change (if necessary) only when EN is high.


GATED D LATCH (1/2)

➤ Make input R equal to S' gated D latch.

➤ D latch eliminates the undesirable condition of invalid state in the S-R latch.

D

EN

Q

Q'

DQ

Q'

EN


GATED D LATCH (2/2)

➤ When EN is high,– D = HIGH latch is SET– D = LOW latch is RESET

➤ Hence when EN is high, Q “follows” the D (data) input.


When EN=1, Q(t+1) = D


FLIP-FLOPS (1/2)

➤ Flip-flops are synchronous (clocked) bistable (two state) devices.

➤ Output changes state at a specified point on a triggering input called the clock.

➤ Change state either at the positive (rising) edge, or at the negative (falling) edge of the clock signal.


Clock signal


FLIP-FLOPS (2/2)

➤ S-R flip-flop, D flip-flop, and J-K flip-flop.

➤ Note the “>” symbol at the clock input.

S

C

R

Q

Q'

D

C

Q

Q'

J

C

K

Q

Q'

Positive edge-triggered flip-flops

S

C

R

Q

Q'

D

C

Q

Q'

J

C

K

Q

Q'

Negative edge-triggered flip-flops


S-R FLIP-FLOP

➤ S-R flip-flop: On the triggering edge of the clock pulse,– R = HIGH and S = LOW Q becomes LOW (RESET state)– S = HIGH and R = LOW Q becomes HIGH (SET state)– Both R and S are LOW No change in output Q – Both R and S are HIGH Invalid!

➤ Characteristic table of positive edge-triggered S-R flip-flop:

X = irrelevant (“don’t care”)

= clock transition LOW to HIGH

S R CLK Q(t+1) Comments

0 0 X Q(t) No change

0 1 0 Reset

1 0 1 Set

1 1 ? Invalid

S

C

R

Q

Q'


S-R FLIP-FLOP

CLK

SET

RESET

Q


D FLIP-FLOP

➤ D flip-flop: Single input D (data). On the triggering edge of the clock pulse,– D = HIGH Q becomes HIGH (SET state)– D = LOW Q becomes LOW (RESET state)

➤ Hence, Q “follows” D at the clock edge.

➤ Convert S-R flip-flop into a D flip-flop: add an inverter.

A positive edge-triggered D flip-flop formed with an S-R flip-flop.

S

C

R

Q

Q'

CLK

DD CLK Q(t+1) Comments

1 1 Set

0 0 Reset

= clock transition LOW to HIGH


D FLIP-FLOP

CLK

D

Q


D FLIP-FLOP vs D LATCH

D

CLK for FFConnect to EN for latch

Q forD-latch

Q forD-flip-flop

Enabled!


D FLIP-FLOP

➤ Application: Parallel data transfer.– To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and

Q3 for storage.

* After occurrence of negative-going transition

Q1 = X*D

CLK

Q

Q'

Q2 = Y*D

CLK

Q

Q'

Q3 = Z*D

CLK

Q

Q'

Combinational logic circuit

Transfer

X

Y

Z


J-K FLIP-FLOP (1/2)

➤ J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND gates.

➤ No invalid state.

➤ Include a toggle state– J = HIGH and K = LOW Q becomes HIGH (SET state)– K = HIGH and J = LOW Q becomes LOW (RESET state)– Both J and K are LOW No change in output Q – Both J and K are HIGH Toggle


J-K FLIP-FLOP (2/2)

➤ J-K flip-flop circuit:

JQ

Q'

CLK

Pulse transition detector

K


J K CLK Q(t+1) Comments

0 0 Q(t) No change

0 1 0 Reset

1 0 1 Set

1 1 Q(t)' Toggle

Q J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0Q(t+1) = JQ' + K'Q


Pulse detection circuit

Positive edge detection

Propagation delay of the NOT gate


Pulse detection circuit

Positive edge detection Negative edge detection

Propagation delay of one NOT gate


T FLIP-FLOP

➤ T flip-flop: Single input version of the J-K flip-flop, formed by tying both inputs together.


TQ

Q'

CLK


J

C

K

Q

Q'

CLK

T

T CLK Q(t+1) Comments

0 Q(t) No change

1 Q(t)' Toggle

Q T Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0Q(t+1) = TQ' + T'Q


Frequency Divider

QCLK

CLK

Q

Frequency = f

Frequency = f / 2


Frequency Divider

➤ What does this do?


A 4 bit counterA B C D

CLK

• CLK is at frequency f: 1010101010101010101010101010101010

• D is at frequency f/2: 110011001100110011001100110011001111

• C is at frequency f/4: 111100001111000011110000111100001111

• B is at frequency f/8: 1111111100000000111111110000000011111111

• A is at frequency f/16: 11111111111111110000000000000000

• Recall our truth table! Count down…


Counter from scratchABCD0000000100100011010001010110011110001001101010111100110111101111

• Bit D changes every clock cycle

• Easy – just use a JK flip flop

D



• Bit C toggles when D is 1 in the previous cycle

• It does not change when D is 0 in the previous cycle

D C



• Bit B toggles when C and D are both 1 in the previous cycle

• It does not change otherwise

D C B



• Bit A toggles when B and C and D are all 1 in the previous cycle

• It does not change otherwise

D C BA


Decimal counterABCD0000000100100011010001010110011110001001000000010010001101000111

• Bit A toggles when B and C and D are all 1 in the previous cycle

• Both bit A and C to be set to 0 when A and D are both 1 in the previous cycle

• When A is 1, disallow any toggling of C (use D’)

ABCD


Frequency Divider (Odd)

CLK

A

B

CLK

Frequency = f

A

B

Frequency = f / 3

Design methodology for sequential logic

The Moore Machine

➤ Output depends only on the current state

➤ Synchronous counters


Example: 3-bit binary counter

Present State Next State

A B C A B C

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0


Step 1: Formulate the problem either as a truth table or a finite state machine

Step 2: Assign flip-flops

➤ Will use one flip-flop for each of the current state bits– 3 JK flip-flops for A, B, and C, respectively


Step 3: Draw truth table for flip-flop inputs


A B C A B C JA KA JB KB JC KC

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 0 1 1 0 X X 0 1 X

0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 1 1 0 X 0 1 X X 1

1 1 0 1 1 1 X 0 X 1 1 X

1 1 1 0 0 0 X 1 X 0 X 1


Q J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

Step 3: K-map

00 01 11 10

0 0 0 1 0

1 X X X X


ABC

JA = BC

00 01 11 10

0 X X X X

1 0 0 1 0

ABC

KA = BC

00 01 11 10

0 0 1 X X

1 0 1 X X

ABC

JB = C

00 01 11 10

0 X X 1 0

1 X X 1 0

ABC

KB = C

Step 3: K-map cont’d

00 01 11 10

0 1 X X 1

1 1 X X 1


ABC

JC = 1

00 01 11 10

0 X 1 1 X

1 X 1 1 X

ABC

KC = 1

Step 4: Circuit Implementation


USING T-FLIP-FLOPS INSTEAD


A B C A B C TA TB TC

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 1

0 1 0 0 1 1 0 0 1

0 1 1 1 0 0 1 1 1

1 0 0 1 0 1 0 0 1

1 0 1 1 1 0 0 1 1

1 1 0 1 1 1 0 1 1

1 1 1 0 0 0 1 1 1


Q T Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

K-MAPS FOR T-FLIP-FLOPS


00 01 11 10

0 0 0 1 0

1 0 0 1 0

ABC

TA = BC

00 01 11 10

0 0 1 1 0

1 0 1 1 0

ABC

TB = C

00 01 11 10

0 1 1 1 1

1 1 1 1 1

ABC

TC = 1

Sychronous 3-bit counter using T-flip-flops


T

CLK

QT

CLK

QT

CLK

Q

A B C

CLK

1

THE MEALY MACHINE

➤ Output is both a function of an input and the current state

➤ Most finite state machines


EXAMPLE OF A MEALY FSM


0

1

3

2

0

0

1

0 0

1

1

1

Use 2 JK flip-flops for the 4 states

Truth table for flip-flop inputs

Present State

Input Next State

A B X A B JA KA JB KB

0 0 0 0 1 0 0 1 0

0 0 1 0 0 0 0 0 1

0 1 0 1 1 1 1 1 0

0 1 1 1 0 1 0 0 1

1 0 0 1 1 0 0 1 1

1 0 1 1 0 0 0 0 0

1 1 0 0 0 1 1 1 1

1 1 1 1 1 1 0 0 0


Q J K Q(t+1)

0 0 0 0

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 1

1 1 1 0

Step 3: K-map

00 01 11 10

0 0 0 1 1

1 0 0 1 1


ABX

JA = B

00 01 11 10

0 0 0 0 1

1 0 0 0 1

ABX

KA = BX

00 01 11 10

0 1 0 0 1

1 1 0 0 1

ABX

JB = X’

00 01 11 10

0 0 1 1 0

1 1 0 0 1

ABX

KB = AX’ + A’X = A ⊕ X

IMPLEMENTATION OF FSM


J

K

CLK

Q A

J

K

CLK

Q B

CLK

X


ASYNCHRONOUS INPUTS (1/2)

➤ S-R, D and J-K inputs are synchronous inputs, as data on these inputs are transferred to the flip-flop’s output only on the triggered edge of the clock pulse.

➤ Asynchronous inputs affect the state of the flip-flop independent of the clock; example: preset (PRE) and clear (CLR) [or direct set (SD) and direct reset (RD)].

➤ When PRE=HIGH, Q is immediately set to HIGH.

➤ When CLR=HIGH, Q is immediately cleared to LOW.

➤ Flip-flop in normal operation mode when both PRE and CLR are LOW.


ASYNCHRONOUS INPUTS (2/2)➤ A J-K flip-flop with active-low PRESET and CLEAR

asynchronous inputs.

JQ

Q'

CLK


K

PRE

CLR

J

C

K

Q

Q'

PRE

CLR

PRE

CLR

CLK

QPreset Toggle ClearJ = K = HIGH


METASTABILITY (1/3)

CLOCK

DATA

OUTPUT

ts th

tco

ts – setup timeth – hold timetco – clock to output time (propagation delay)

In reality, nothing is instantaneous. Critical timing parameters must be observed.


METASTABILITY (2/3)

➤ If setup and hold times are violated, flip-flop may oscillate in an indeterminate state between 0 and 1

➤ This is called metastability➤ Introduces error in the circuit’s operation➤ Cannot be absolutely avoided in practice

– Make sure clock period is long enough– Use flip-flop chain


METASTABILITY (3/3)

➤ The probability of metastability gets closer and closer to zero (but never zero) as the number of flip-flops

connected in series is increased.

D Q D Q

CLK

Input Output


TRI-STATE MULTIPLEXERS

➤ “Tri-state” = high, low, high-impedance– High-impedance means the circuit

is “not connected”

➤ A tri-state buffer:– When enabled, connects input to

output– When disabled disconnects input

from output by entering a high-impedance state


MEMORY HIERARCHY (1/2)

➤ Memory stores programs and data.

➤ Definitions:– 1 byte = 8 bits– 1 word: in multiple of bytes, a unit of transfer between main

memory and registers, usually size of register.

– 1 KB (kilo-bytes) = 210 bytes; 1 MB (mega-bytes) = 220 bytes;1 GB (giga-bytes) = 230 bytes; 1 TB (tera-bytes) = 240 bytes.

➤ Desirable properties: fast access, large capacity, economincal cost, non-volatile.

➤ However, most memory devices do not possess all these properties.


MEMORY HIERARCHY (2/2)

registers

main memory

disk storage

magnetic tapes

Fast, expensive (small numbers), volatile

Slow, cheap (large numbers), non-volatile

➤ Memory hierarchy


REGISTER FILE (1/2)

➤ A register is an array of D-flip-flops➤ A register file is a circuit with several registers, and

selection lines to choose on which register to operate next

➤ Operations: read and writeFeatures: - Fast - Simple addressing - Multiported (multiple reads and writes concurrently)


REGISTER FILE (2/2)

D Q

CLK

D Q

CLK

D Q

CLK

D Q

CLK

WR

DecoderRegisterNumber

Read data

Write data

4-bit register


MEMORY (1/2)

➤ Data transferAddress

k-bit address bus

012345

Processor

MAR

MDR

Memory

:

n-bit data bus

Control lines(R/W, etc.)

Up to 2k addressable

locations.


MEMORY (2/2)

A memory unit stores binary information in groups of bits called words.

The data consists of n lines (for n-bit words). Data input lines provide the information to be stored (written) into the memory, while data output lines carry the information out (read) from the memory.

The address consists of k lines which specify which word (among the 2k words available) to be selected for reading or writing.

The control lines Read and Write (usually combined into a single control line Read/Write) specifies the direction of transfer of the data.


MEMORY UNIT

➤ Block diagram of a memory unit:

Memory unit2k words

n bits per word

k address linesk

Read/Write

n

n

n data input lines

n data output lines


READ/WRITE OPERATIONS

➤ Write operation:– Transfers the address of the desired word to the address lines.– Transfers the data bits (the word) to be stored in memory to the

data input lines.– Activates the Write control line (set Read/Write to 0).

➤ Read operation:– Transfers the address of the desired word to the address lines.– Activates the Read control line (set Read/Write to 1).

Memory Enable Read/Write Memory Operation

0 X None1 0 Write to selected word1 1 Read from selected word


MEMORY CELL➤ Two types of RAM

– Static RAMs use flip-flops as the memory cells.– Dynamic RAMs use capacitor charges to represent data. Though simpler in

circuitry, they have to be constantly refreshed.

➤ A single memory cell of the static RAM has the following logic and block diagrams:

R

S QInput

Select

Output

Read/Write

BC OutputInput

Select

Read/Write

Logic diagram Block diagram


MEMORY ARRAYS (1/4)

➤ Logic construction of a 43 RAM (with decoder and OR gates):


MEMORY ARRAYS (2/4)

➤ An array of RAM chips: memory chips are combined to form larger memory.

➤ A 1K 8-bit RAM chip:

Block diagram of a 1K x 8 RAM chip

RAM 1K x 8

DATA (8)ADRS (10)CSRW

Input dataAddress

Chip selectRead/write

(8) Output data8 810


MEMORY ARRAYS (3/4)

➤ 4K 8 RAM.

1K x 8


Read/write

(8)

Output data

1K x 8


(8)

1K x 8


(8)

1K x 8


(8)

0–1023

1024 – 2047

2048 – 3071

3072 – 4095

Input data8 lines

0123

2x4 decoder

Lines Lines0 – 911 10

S0

S1

Address


MEMORY ARRAYS (4/4)

➤ 2M 32 memory module– Using 512K 8 memory chips.Chip select

512K x 8 memory chip

19-bitaddress

8-bit datainput/output

19-bit internal chip address

2-bitdecoder

addresses21-bit

A 0A 1

A19

512k X 8memory chip

A20

D31-24 D7-0D23-16 D 15-8


END

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Cs2100 8 Sequential Logic