Cs5460A No Proteguido

Preliminary Product Information This document contains information for a new product.Cirrus Logic reserves the right to modify this product without notice.

1

Copyright Cirrus Logic, Inc. 2000(All Rights Reserved)P.O. Box 17847, Austin, Texas 78760

(512) 445 7222 FAX: (512) 445 7581http://www.cirrus.com

CS5460A

Single Phase Bi-Directional Power/Energy ICFeatures

lEnergy Data Linearity: 0.1% of Reading over 1000:1 Dynamic Range

lOn-Chip Functions: Energy, I ∗ V,IRMS and VRMS, Energy to Pulse-Rate Conversion

lSmart “Auto-Boot” Mode from Serial EEPROM with no microcontroller.

lAC or DC System CalibrationlMechanical Counter/Stepper Motor DriverlMeets Accuracy Spec for IEC 687/1036, JISlPower Consumption <12 mWl Interface Optimized for Shunt SensorlPhase CompensationlGround-Referenced Signals with Single

SupplylOn-chip 2.5 V Reference (MAX 60 ppm/°C

drift)lSimple Three-Wire Serial InterfacelWatch Dog TimerlPower Supply MonitorlPower Supply Configurations

VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 VVA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V

DescriptionThe CS5460A is a highly integrated ∆Σ Analog-to-DigitalConverter (ADC) which combines two ∆Σ ADCs, highspeed power calculation functions, and a serial interfaceon a single chip. It is designed to accurately measureand calculate: Energy, Instantaneous Power, IRMS, andVRMS for single phase 2- or 3-wire power metering appli-cations. The CS5460A interfaces to a low cost shunt ortransformer to measure current, and resistive divider ortransformer to measure voltage. The CS5460A featuresa bi-directional serial interface for communication with amicro-controller and a programmable frequency outputthat is proportional to energy. CS5460A has on-chipfunctionality to facilitate AC or DC system-levelcalibration.

The “Auto-Boot” feature allows the CS5460A to function“stand-alone” and to initialize itself on system power up.In Auto-Boot Mode, the CS5460A reads the calibrationdata and start-up instructions from an external EE-PROM. In this mode, the CS5460A can work without theneed for a microprocessor, for low-cost meteringapplications.

ORDERING INFORMATION:CS5460A-BS -40°C to +85°C 24-pin SSOPCS5460A-KS 0°C to +70°C 24-pin SOIC

PGAx10,x50

VA+ VD+

IIN+

IIN-

VIN+

VIN-

VREFIN

VREFOUT

VA- XIN XOUT CPUCLK DGND

CS

SDO

SDI

SCLK

INT

EOUT

DigitalFilter

High PassFilter

VoltageReference

SystemClock

/K ClockGenerator

SerialInterface

PowerCalculation

Engine(Energy

I * VI ,V )RMS RMS

E-to-F

PowerMonitor

PFMON

x1

x10

4 Order∆Σ

Modulator

th

RESET

DigitalFilter

CalibrationSRAM

EDIR

High PassFilter

2 Order∆Σ

Modulator

nd

Watch DogTimer

MODE

JUL ‘00DS284PP2

CS5460A

2 DS284PP2

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 5ANALOG CHARACTERISTICS ............................................................................................... 55 V DIGITAL CHARACTERISTICS .......................................................................................... 73 V DIGITAL CHARACTERISTICS .......................................................................................... 8ABSOLUTE MAXIMUM RATINGS .......................................................................................... 8SWITCHING CHARACTERISTICS ......................................................................................... 9

2. GENERAL DESCRIPTION ...................................................................................................... 122.1 Theory of Operation ......................................................................................................... 122.2 Performing Measurements............................................................................................... 13

2.2.1 Single Computation Cycle (C = 0) .......................................................................... 142.2.2 Multiple Computation Cycles (C = 1)...................................................................... 14

2.3 High Rate Digital Filters ................................................................................................... 152.4 High-Pass Filters.............................................................................................................. 15

3. SERIAL PORT OVERVIEW..................................................................................................... 153.1 Commands (Write Only) .................................................................................................. 16

3.1.1 Start Conversions................................................................................................... 163.1.2 SYNC0 Command.................................................................................................. 163.1.3 SYNC1 Command.................................................................................................. 163.1.4 Power-Up/Halt ........................................................................................................ 163.1.5 Power-Down........................................................................................................... 173.1.6 Calibration .............................................................................................................. 173.1.7 Register Read/Write ............................................................................................... 18

3.2 Serial Port Interface Pins ................................................................................................. 193.3 Serial Read and Write...................................................................................................... 19

3.3.1 Register Write......................................................................................................... 193.3.2 Register Read ........................................................................................................ 19

3.4 Serial Port Initialization .................................................................................................... 213.5 System Initialization ......................................................................................................... 21

4. FUNCTIONAL DESCRIPTION ................................................................................................ 224.1 Pulse-Rate Output ........................................................................................................... 224.2 Multi-Phase Option for Pulse Output ............................................................................... 234.3 Pulse Output for Normal Mode, Stepper Motor Mode and Mechanical

Counter Mode................................................................................................................... 254.3.1 Normal Mode.......................................................................................................... 254.3.2 Mechanical Counter Mode ..................................................................................... 254.3.3 Stepper Motor Mode............................................................................................... 25

Contacting Cirrus Logic SupportFor a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:http://www.cirrus.com/corporate/contacts/Microwire is a trademark of National Semiconductor Corporation.

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the informationcontained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty ofany kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rightsof third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part ofthis publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, orotherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, nopart of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication may be used as a basis for manufactureor sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearingin this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-marks and service marks can be found at http://www.cirrus.com.

CS5460A

DS284PP2 3

4.4 Auto-Boot Mode Using EEPROM.................................................................................... 254.5 Interrupt and Watchdog Timer......................................................................................... 28

4.5.1 Interrupt.................................................................................................................. 284.5.1.1 Clearing the Status Register......................................................................... 284.5.1.2 Typical use of the INT pin............................................................................. 284.5.1.3 INT Active State............................................................................................ 284.5.1.4 Exceptions .................................................................................................... 28

4.5.2 Watch Dog Timer ................................................................................................... 284.6 Oscillator Characteristics................................................................................................. 294.7 Analog Inputs................................................................................................................... 294.8 Voltage Reference........................................................................................................... 294.9 Calibration ....................................................................................................................... 29

4.9.1 Overview of Calibration Process ............................................................................ 294.9.2 The Calibration Registers....................................................................................... 304.9.3 Calibration Sequence............................................................................................. 304.9.4 Duration of Calibration Sequence .......................................................................... 314.9.5 Description of Calibration Algorithms ..................................................................... 314.9.6 Is Calibration Required?......................................................................................... 324.9.7 Calibration Tips ...................................................................................................... 33

4.10 Phase Compensation .................................................................................................... 334.11 Time-Base Calibration Register..................................................................................... 334.12 Power Offset Register ................................................................................................... 344.13 Input Protection and Filtering......................................................................................... 344.14 PCB Layout ................................................................................................................... 35

5. REGISTER DESCRIPTION ..................................................................................................... 365.1 Configuration Register..................................................................................................... 365.2 DC Current Offset Register and DC Voltage Offset Register .......................................... 385.3 AC/DC Current Gain Register and AC/DC Voltage Gain Register .................................. 385.4 Cycle Count Register....................................................................................................... 385.5 Pulse-Rate Register ........................................................................................................ 395.6 I,V,P,E Signed Output Register Results .......................................................................... 395.7 IRMS, VRMS Unsigned Output Register Results............................................................ 395.8 Timebase Calibration Register ........................................................................................ 395.9 Power Offset Register ..................................................................................................... 405.10 AC Current Offset Register and AC Voltage Offset Register ........................................ 405.11 Status Register and Mask Register ............................................................................... 405.12 Control Register............................................................................................................. 42

6. PIN DESCRIPTION.................................................................................................................. 43

7. PACKAGE DIMENSIONS ....................................................................................................... 45

CS5460A

4 DS284PP2

LIST OF FIGURESFigure 1. SDI Write Timing (Not to Scale) ..................................................................................... 10Figure 2. SDO Read Timing (Not to Scale) ................................................................................... 10Figure 3. CS5460A Auto-Boot Sequence Timing.......................................................................... 11Figure 4. Typical Connection Diagram (One-Phase 2-Wire)......................................................... 12Figure 5. Typical Connection Diagram (One-Phase 3-Wire)......................................................... 13Figure 6. Data Flow ....................................................................................................................... 14Figure 7. Voltage Input Filter Characteristics ................................................................................ 15Figure 8. Current Input Filter Characteristics ................................................................................ 15Figure 9. Command and Data Word Timing.................................................................................. 20Figure 11. Option for wire and configuration of EOUT and EDIR pins for multi-phase metering .. 24Figure 10. Multi-Phase System (Normal Mode only)..................................................................... 24Figure 12. Mechanical Counter Mode on EOUT and EDIR........................................................... 25Figure 13. Stepper Motor Mode on EOUT and EDIR.................................................................... 25Figure 14. Typical Interface of EEPROM to CS5460A.................................................................. 26Figure 15. Timing Diagram for Auto-Boot Sequence .................................................................... 27Figure 16. Oscillator Connection ................................................................................................... 29Figure 17. System Calibration of Gain. ......................................................................................... 31Figure 18. System Calibration of Offset. ....................................................................................... 31Figure 19. Calibration Data Flow................................................................................................... 32Figure 20. CS5460A Register Diagram......................................................................................... 36

LIST OF TABLESTable 1. Output Linearity after Calibration with MCLK = 4.096 MHz, K = 1, N = 4000.................. 14Table 2. Internal Registers Default Value...................................................................................... 21

CS5460A

DS284PP2 5

1. CHARACTERISTICS AND SPECIFICATIONS

ANALOG CHARACTERISTICS (TA = -40° C to +85° C; VA+, VD+ = +5 V ±10%; VREFIN = 2.5 V; VA- = AGND; MCLK = 4.096 MHz, K = 1; N = 4000, OWR = 4.0 kHz.)(See Notes 1, 2, and 3)

Notes: 1. Applies after system calibration

2. Specifications guaranteed by design, characterization, and/or test.

3. Analog signals are relative to VA- and digital signals to DGND unless otherwise noted.

4. Effective Input Impedance (EII) is determined by clock frequency (DCLK) and Input Capacitance (IC).EII = 1/(IC*DCLK/4)

Parameter Symbol Min Typ Max Unit

Accuracy (Both Channels)Total Harmonic Distortion THD 74 - - dB

Common Mode Rejection (DC, 50, 60 Hz) CMRR 80 - - dB

Offset Drift (Without the High Pass Filter) - 5 - nV/°C

Analog Inputs (Current Channel)Differential Input Voltage Range (IIN+) - (IIN-) (Gain = 10)

(Gain = 50)IIN 0

0--

±250±50

mV(dc)mV(dc)

Common Mode + Signal on IIN+ or IIN- (Gain = 10 or 50) -0.25 - VA+ V

Crosstalk with Voltage Channel at Full Scale (50, 60 Hz) - - -115 dB

Input Capacitance (Gain = 10)(Gain = 50)

IC --

2525

--

pFpF

Effective Input Impedance (Note 4)(Gain = 10)

(Gain = 50)

EII3030

--

--

kΩkΩ

Noise (Referred to Input) (Gain = 10)(Gain = 50)

--

--

204

µVrmsµVrms

Accuracy (Current Channel)Bipolar Offset Error (Note 1) VOS - - ±0.001 %F.S.

Full-Scale Error (Note 1) FSE - - ±0.001 %F.S.

Analog Inputs (Voltage Channel)Differential Input Voltage Range (VIN+) - (VIN-) VIN 0 - ±250 mV(dc)

Common Mode + Signal on VIN+ or VIN- -0.25 - VA+ V

Crosstalk with Current Channel at Full Scale (50, 60 Hz) - - -70 dB

Input Capacitance IC - 0.2 - pF

Effective Input Impedance (Note 4) EII 5 - - MΩNoise (Referred to Input) - - 250 µVrms

Accuracy (Voltage Channel)Bipolar Offset Error (Note 1) VOS - - ±0.01 %F.S.

Full-Scale Error (Note 1) FSE - - ±0.01 %F.S.

CS5460A

6 DS284PP2

ANALOG CHARACTERISTICS (Continued)

Notes: 5. The minimum FSCR is limited by the maximum allowed gain register value.6. All outputs unloaded. All inputs CMOS level.


Dynamic CharacteristicsPhase Compensation Range (Voltage Channel, 60 Hz) -2.4 - +2.5 °

High Rate Filter Output Word Rate (Both Channels) OWR - DCLK/1024 - Hz

Input Sampling Rate DCLK = MCLK/K - DCLK/4 - Hz

Full Scale DC Calibration Range (Note 5) FSCR 25 - 100 %F.S.

Channel-to-Channel Phase Error (60 Hz)(when PC[6:0] bits are set to “0000000”)

0.02 Deg

High Pass Filter Pole Frequency -3 dB - 0.5 - Hz

Reference OutputOutput Voltage REFOUT 2.4 - 2.6 V

Temperature Coefficient - 25 60 ppm/°C

Load Regulation (Output Current 1 µA Source or Sink) ∆VR - 6 10 mV

Output Noise Voltage (0.1 Hz to 512 kHz) eN - 100 - µVrms

Reference InputInput Voltage Range VREFIN 2.4 2.5 2.6 V

Input Capacitance - 4 - pF

Input CVF Current - 25 - nA

Power SuppliesPower Supply Currents (Normal Mode) IA+

ID+ (VD+ = 5 V)ID+ (VD+ = 3 V)

PSCAPSCDPSCD

---

1.32.91.7

---

mAmAmA

Power Consumption Normal Mode (VD+ = 5 V)(Note 6) Normal Mode (VD+ = 3 V)

StandbySleep

PC ----

2111.66.7510

25---

mWmWmWµW

Power Supply Rejection (50, 60 Hz)(Gain = 10)(Gain = 50)

PSRRPSRR

5670

- -dBdB

Power Monitor Hysteresis Thresholds PM 2.3 2.7 V

CS5460A

DS284PP2 7

5 V DIGITAL CHARACTERISTICS (TA = -40° C to +85° C; VA+, VD+ = 5 V ±10% VA-, DGND = 0 V) (See Notes 2 and 7)


High-Level Input VoltageAll Pins Except XIN and SCLK and /RESET

XINSCLK and /RESET

VIH0.6 VD+

(VD+) - 0.50.8 VD+

---

---

VVV

Low-Level Input VoltageAll Pins Except XIN and SCLK and /RESET

XINSCLK and /RESET

VIL---

---

0.81.5

0.2 VD+

VVV

High-Level Output Voltage Iout = +5 mA VOH (VD+) - 1.0 - - V

Low-Level Output Voltage Iout = -5 mA VOL - - 0.4 V

Input Leakage Current Iin - ±1 ±10 µA

3-State Leakage Current IOZ - - ±10 µA

Digital Output Pin Capacitance Cout - 5 - pF

CS5460A

8 DS284PP2

3 V DIGITAL CHARACTERISTICS (TA = -40° C to +85° C; VA+ = 5 V ±10%, VD+ = 3 V ±10%; VA-, DGND = 0 V) (See Notes 2 and 7)

Notes: 7. All measurements performed under static conditions.

ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 8)

Notes: 8. All voltages with respect to ground.

9. VA+ and VA- must satisfy (VA+) - (VA-) ≤ +6.0 V.

10. VD+ and VA- must satisfy (VD+) - (VA-) ≤ +6.0 V.

11. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins.

12. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.

13. Total power dissipation, including all input currents and output currents.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.


High-Level Input VoltageAll Pins Except XIN and SCLK and /RESET

XINSCLK and /RESET

VIH0.6 VD+

(VD+) - 0.50.8 VD+

---

---

VVV

Low-Level Input VoltageAll Pins Except XIN and SCLK and /RESET

XINSCLK and /RESET

VIL---

---

0.480.3

0.2 VD+

VVV

High-Level Output Voltage Iout = +5 mA VOH (VD+) - 1.0 - - V

Low-Level Output Voltage Iout = -5 mA VOL - - 0.4 V

Input Leakage Current Iin - ±1 ±10 µA

3-State Leakage Current IOZ - - ±10 µA

Digital Output Pin Capacitance Cout - 5 - pF


DC Power Supplies (Notes 9 and 10)Positive Digital

Positive AnalogNegative Analog

VD+VA+VA-

-0.3-0.3+0.3

---

+6.0+6.0-6.0

VVV

Input Current, Any Pin Except Supplies (Note 11 and 12) IIN - - ±10 mA

Output Current IOUT - - ±25 mA

Power Dissipation (Note 13) PDN - - 500 mW

Analog Input Voltage All Analog Pins VINA - 0.3 - (VA+) + 0.3 V

Digital Input Voltage All Digital Pins VIND -0.3 - (VD+) + 0.3 V

Ambient Operating Temperature TA -40 - 85 °C

Storage Temperature Tstg -65 - 150 °C

CS5460A

DS284PP2 9

SWITCHING CHARACTERISTICS (TA = -40° C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50 pF))

Notes: 14. Device parameters are specified with a 4.096 MHz clock, however, clocks between 3 MHz to 20 MHz can be used.

15. If external MCLK is used, then its duty cycle must be between 45% and 55% to maintain this spec.

16. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.

17. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.

Parameter Symbol Min Typ Max UnitMaster Clock Frequency Internal Gate Oscillator (Note 14) MCLK 2.5 4.096 20 MHzMaster Clock Duty Cycle 40 - 60 %CPUCLK Duty Cycle (Note 15) 40 60 %Rise Times Any Digital Input Except SCLK (Note 16)

SCLKAny Digital Output

trise ---

--

50

1.0100

-

µsµsns

Fall Times Any Digital Input Except SCLK (Note 16)SCLK

Any Digital Output

tfall ---

--

50

1.0100

-

µsµsns

Start-upOscillator Start-up Time XTAL = 4.096 MHz (Note 17) tost - 60 - ms

Serial Port TimingSerial Clock Frequency SCLK - - 2 MHzSerial Clock Pulse Width High

Pulse Width Lowt1t2

200200

--

--

nsns

SDI Write TimingCS Enable to Valid Latch Clock t3 50 - - ns

Data Set-up Time Prior to SCLK Rising t4 50 - - ns

Data Hold Time After SCLK Rising t5 100 - - ns

SCLK Falling Prior to CS Disable t6 100 - - ns

SDO Read TimingCS Enable to Valid Latch Clock t7 - - 150 ns

SCLK Falling to New Data Bit t8 - - 150 ns

CS Rising to SDO Hi-Z t9 - - 150 ns

Auto-Boot TimingMODE setup time to /RESET rising t10 50 ns

/RESET rising to /CS falling t11 48 MCLK

/CS falling to SCLK rising t12 100 ns

SDO out from SCLK falling hold time t13 0 20 50 ns

SDI input to SCLK rising setup time t14 50 ns

SDI input from SCLK rising hold time t15 50 ns

SCLK falling to /CS rising t16 100 ns

/CS rising to driving MODE low (to end auto-boot sequence). t17 50 ns

CS5460A

10 DS284PP2

CS

SDI

SCLK

MSB MSB - 1 LSB

t6t2t1t5t4t3

Figure 1. SDI Write Timing (Not to Scale)

CS

SDO

SCLK

MSB MSB - 1 LSB

t9

t2t1t8

t7

Figure 2. SDO Read Timing (Not to Scale)

CS

5460A

DS

284PP

211

RES

SDI

SCLK

t13

t 12

t 11

t2

t 1

SDO

CS

t15

t14

Data from EEPROM

(Output)

(Output)

(Output)

(Input)

(Input from EEPROM)

MODE(Input)

t 10

t 16

t 17

STOPBIT

LAST 8 BITS

Figure 3. CS5460A Auto-Boot Sequence Timing

CS5460A

12 DS284PP2

2. GENERAL DESCRIPTION

The CS5460A is a CMOS monolithic power mea-surement device with an energy computation en-gine. The CS5460A combines a programmablegain amplifier, two ∆Σ modulators, two high ratefilters, system calibration, and power calculationfunctions to compute Energy, VRMS, IRMS, and In-stantaneous Power.

The CS5460A is designed for power measurementapplications and is optimized to interface to a shuntor current transformer to measure current, and a re-sistive divider or transformer to measure voltage.To accommodate various input voltage levels, thecurrent channel includes a programmable gain am-plifier (PGA) which provides either 150 mVRMS or30 mVRMS as the full-scale input level.

The CS5460A includes two high-rate digital filterswhich output data at a (MCLK/K)/1024 output wordrate (OWR).

To facilitate communication to a microcontroller,the CS5460A includes a simple three-wire serialinterface which is SPI™ and Microwire™ compat-ible. The serial port has a Schmitt Trigger input onits serial clock (SCLK) to allow for slow rise timesignals.

2.1 Theory of Operation

The CS5460A is designed to operate from a single+5 V supply or dual ±2.5 V supplies. It provides a30 mVRMS or 150 mVRMS range for the currentchannel and to provide a 150mVRMS range for thevoltage channel. With single +5 V supply onVA+/-, the CS5460A accommodates commonmode signals between -0.25 V and VA+.

Figure 4 shows the CS5460A connected to a ser-vice to measure power in a single-phase 2-wire sys-tem while operating in a single supplyconfiguration. Figure 5 shows the CS5460A con-figured to measure power in a single-phase 3-wiresystem.

VA+ VD+

CS5460

0.1 µF100 µF

500 Ω

470 nF

500 ΩN

R1R2

10 Ω

14

VIN+9

VIN-

IIN-

10

15

16 IIN+

PFMON

CPUCLK

XOUT

XINOptional

ClockSource

SerialData

Interface

RESET

17

2

1

24

19

CS7

SDI 23

SDO 6

SCLK 5

INT 20

EDIR 22

EOUT 21

0.1 µF

VREFIN12

VREFOUT11

VA- DGND

13 4

3

To Service

2.5 MHz to20 MHz

0.1 µF

CP

10 kΩ5 kΩ

L

RS

V

CPI

RPI

*

*

*

* Refer to Input Protection

N L

M:1

N L

RB

Alternate Sensor Options

N:1

RPI *

RPV*

RPV*

VoltageTransformer

CurrentTransformer

A

Figure 4. Typical Connection Diagram (One-Phase 2-Wire)

- Section 4.13

CS5460A

DS284PP2 13

2.2 Performing Measurements

The CS5460A performs measurements of instanta-neous current, instantaneous voltage, instantaneouspower, energy, RMS current, and RMS voltage.These measurements are output as 24-bit signedand unsigned data formats as a percentage of fullscale. This means that the 24-bit data words in theCS5460A output registers represent values be-tween 0 and 1 (for unsigned output registers) or be-tween -1 and +1 (for signed output registers). Aregister value of 1 represents the maximum possi-ble value. Note that a value of 1.0 is never actuallyobtained in the registers of the CS5460A. As an il-lustration, in any of the signed output registers, themaximum register value is [(2^23 - 1) / (2^23)] =0.999999880791. The flow of data to perform thesecalculations is shown in Figure 6. After each A/Dconversion, the CRDY bit will be asserted in theStatus Register, and the INT pin will also becomeactive if the CRDY bit is unmasked. This assertionof CRDY bit indicates that new instantaneous volt-

age, current samples have been collected, and theyare multiplied together to provide a correspondinginstantaneous power sample.

The VRMS, IRMS, and energy calculations are up-dated every N conversions (which is known as 1“computation cycle”) where N is the content of theCycle Count register. At the end of each computa-tion cycle, the DRDY bit in the Status and Maskregister will be set, and the INT pin will become ac-tive if the DRDY bit is unmasked.

DRDY is set only after each computation cycle hascompleted, whereas the CRDY bit is asserted aftereach individual A/D conversion. When these bitsare asserted, they must be cleared by the user be-fore they can be asserted again. If the Cycle CountRegister value (N) is set to 1, all output calculationsare instantaneous, and DRDY will indicate wheninstantaneous calculations are finished, just like theCRDY bit. For the RMS results to be valid, the Cy-cle-Count Register must be set to a value greaterthan 10.

VA+ VD+

CS5460

0.1 µF100 µF

500 Ω

470 nF

500 ΩN

R1 R2

RS

10 Ω

14

VIN+9

VIN-

IIN-

10

16

15

IIN+

PFMON

CPUCLK

XOUT

XINOptional

ClockSource

SerialData

Interface

RESET

17

2

1

24

19

CS7

SDI 23

SDO 6

SCLK 5

INT20

EDIR 22

EOUT 21

0.1 µF

VREFIN12

VREFOUT11

DGND13 4

3

To Service

2.5 MHz to20 MHz

0.1 µF

L 1 L 2

10 kΩ5 kΩ

VA-

RPI

CPI

CPV

* Refer to Input Protection

*

*

*

CPI*

RPI *

CPV

*R 1R2

To Service

A

Figure 5. Typical Connection Diagram (One-Phase 3-Wire)

- Section 4.13

CS5460A

14 DS284PP2

Table 1 provides an example detailing the outputlinearity. A computation cycle is derived from themaster clock and its frequency is(MCLK/K)/(1024*N). Under default conditionswith a 4.096 Mhz clock at XIN, instantaneous A/Dconversions for voltage, current, and power areperformed at a 4000 Hz rate, whereas IRMS, VRMS,and energy calculations are performed at a 1 Hzrate.

2.2.1 Single Computation Cycle (C = 0)

Based on the information provided in the CycleCount register, a single computation cycle is per-formed after the user transmits the single conver-sion cycle command. After the computations arecomplete, DRDY is set. Thirty-two SCLKs arethen needed to acquire a calculation result from one

of several result registers. The first 8 SCLKs areused to clock in the command to determine whichregister is to be read. The last 24 SCLKs are usedto read the desired register. After reading the data,the serial port returns to the command mode, whereit waits for a new command to be issued.

2.2.2 Multiple Computation Cycles (C = 1)

Based on the information provided in the CycleCount register, computation cycles are repeatedlyperformed on the voltage and current channels (af-ter every N conversions). Computation cycles can-not be started/stopped on a per channel basis. Aftereach computation cycle is completed, DRDY is set.Thirty-two SCLKs are then needed to read a regis-ter. The first 8 SCLKs are used to clock in the com-mand to determine which results register is to beread. The last 24 SCLKs are used to read the calcu-lation result. While in this mode, the user maychoose to acquire only the calculations required forthe application as DRDY rises and falls to indicatethe availability of a new data.

The RMS calculations undergo a Sinc2 operationprior to their square root operation. Therefore, thefirst output for each channel will be invalid (i.e. allRMS calculations are invalid in the single compu-

VOLTAGE ∆Σ SINC2 + x

V *gn

x

V*

CURRENT SINC4 + x

I *gn

x x

TBC *

DELAYREG

DELAYREG FIR HPF

APF

Configuration Register *PC[6:0] Bits

x I *RMS

N V *RMS

NΣ ÷4096

E to F

E *

E

Eout

dirPULSE-RATE*

* DENOTES REGISTER NAME

∆Σ HPF

APF

FIR

SINC2

I *

P *

NSINC2-

-

IACoff*IDCoff*

VACoff*VDCoff*

+

Poff*

Figure 6. Data Flow.

Energy Vrms Irms

Range 1000:1 2:1 500:1

Max Input See Analog Characteristics

Linearity(After

Calibration)

0.1% of reading

0.1% of reading

0.1% of reading

Output word 24-bits

Table 1. Output Linearity after Calibration with MCLK = 4.096 MHz, K = 1, N = 4000

CS5460A

DS284PP2 15

tation cycle routine and the first RMS calculationswill be invalid in the continuous computation cy-cle). All energy calculations will be valid since en-ergy calculations do not require this Sinc2

operation.

2.3 High Rate Digital Filters

Referring to Figure 6, the high rate filter on thevoltage channel is implemented as a fixed Sinc2 fil-ter, compensated by a short length FIR. When theconverter is driven with a 4.096 MHz clock (K=1),the filter has a magnitude response as shown inFigure 7. Note that the filter’s response scales withMCLK frequency and K.

The current channel contains a Sinc4 filter, com-pensated by a short length FIR. When the converteris driven with a 4.096 MHz clock (K=1) the com-posite filter response is given in Figure 8.

2.4 High-Pass Filters

A digital high-pass filter in both channels can be en-abled to remove the DC content from the input sig-nal before the energy calculations are made. Thesefilters are activated by enabling certain bits in theconfiguration register. If the user wants to use thehigh-pass filters on just one of the two channels, thenthe user should apply the all-pass filter option to theother channel. For example, if high-pass filter isneeded for voltage channel, but not the current chan-

nel, then the all-pass filter can be used in the voltagechannel to match the phase delay that is naturally in-troduced by the high-pass filter.

3. SERIAL PORT OVERVIEW

The CS5460A's serial port incorporates a state ma-chine with transmit/receive buffers. The state ma-chine interprets 8 bit command words on the risingedge of SCLK. Upon decoding of the commandword the state machine performs the requestedcommand or prepares for a data transfer of the ad-dressed register. Request for a read requires an in-ternal register transfer to the transmit buffer, whilea write waits until the completion of 24 SCLKs be-fore performing a transfer. The internal registersare used to control the ADC's functions. All regis-ters are 24-bits in length. Figure 20 summarizes theinternal registers available to the user.

The CS5460A is initialized and fully operationalupon power-on. After a power-on, serial port ini-tialization, or reset, the serial port state machine isinitialized into command mode where it waits to re-ceive a valid command (the first 8-bits clocked intothe serial port). Upon receiving and decoding a val-id command word, the state machine instructs theconverter to either perform a system operation, ortransfer data to or from an internal register. Theuser should refer to the “Commands” section to de-code all valid commands.

-2.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

Frequency (Hertz)

Gai

n (

dB

)

0 200 400 600 800 1000 1200 1400 1600 1800 2000

Figure 7. Voltage Input Filter Characteristics

-2.5

-2

-1.5

-1

-0.5

0

0.5

0 200 400 600 800 1000 1200 1400 1600 1800 2000

Gai

n (d

B)

Frequency (Hertz)

Figure 8. Current Input Filter Characteristics

CS5460A

16 DS284PP2

3.1 Commands (Write Only)All command words are 1 byte in length. Commands that write to a register must be followed by 1, 2, or 3 bytes of register data. Commands that read from registers initiate 3 bytes of register data. Commands that read data can be chained with other commands (e.g., while reading data, a new command can be sent to SDI which can execute be-fore the original read is completed). This allows for “chaining” commands.

3.1.1 Start Conversions

This command indicates to the state machine to begin acquiring measurements and calculating results. The device has two modes of acquisition.

C = Modes of measurement0 = Perform a single computation cycle1 = Perform continuous computation cycles

3.1.2 SYNC0 Command

This command is the end of the serial port re-initialization sequence. The command can also be used as a NOP command. The serial port is resynchronized to byte boundaries by sending three or more consecutive SYNC1 com-mands followed by a SYNC0 command.

3.1.3 SYNC1 Command

This command is part of the serial port re-initialization sequence. The command can also serve as a NOP command.

3.1.4 Power-Up/Halt

If the device is powered-down, this command will power-up the device. When powered-on, no computations will be running. If the part is already powered-on, all computations will be halted.

B7 B6 B5 B4 B3 B2 B1 B01 1 1 0 C 0 0 0

B7 B6 B5 B4 B3 B2 B1 B01 1 1 1 1 1 1 0

B7 B6 B5 B4 B3 B2 B1 B01 1 1 1 1 1 1 1

B7 B6 B5 B4 B3 B2 B1 B01 0 1 0 0 0 0 0

CS5460A

DS284PP2 17

3.1.5 Power-Down

The device has two power-down modes to conserve power. If the chip is put in stand-by mode all circuitry except the clock generator is turned off.

S1,S0 Power-down mode00 = Reserved01 = Halt and enter stand-by power saving mode. This mode allows quick power-on time10 = Halt and enter sleep power saving mode. This mode requires a slow power-on time11 = Reserved

3.1.6 Calibration

The device has the capability of performing a system AC offset calibration, DC offset calibration, AC gain calibration, and DC gain calibration. The user can calibrate the voltage channel, the current channel, or both channels at the same time. Offset and gain calibrations should NOT be performed at the same time (must do one after the other). For a given application, if DC gain calibrations are performed, then AC gain calibration should not be performed (and vice-versa). The user must supply the proper inputs to the device before initiating calibration.

V,I Designates calibration channel00 = Not allowed01 = Calibrate the current channel10 = Calibrate the voltage channel11 = Calibrate voltage and current channel simultaneously

R Specifies AC calibration (R=1) or DC calibration (R=0)

G Designates gain calibration0 = Normal operation1 = Perform gain calibration

O Designates offset calibration0 = Normal operation1 = Perform offset calibration

B7 B6 B5 B4 B3 B2 B1 B01 0 0 S1 S0 0 0 0

B7 B6 B5 B4 B3 B2 B1 B01 1 0 V I R G O

CS5460A

18 DS284PP2

3.1.7 Register Read/Write

This command informs the state machine that a register access is required. On reads the addressed register is load-ed into the output buffer and clocked out by SCLK. On writes the data is clocked into the input buffer and transferred to the addressed register on the 24th SCLK.

W/R Write/Read control0 = Read register1 = Write register

RA[4:0] Register address bits. Binary encoded 0 to 31. All registers are 24 bits in length.

Address Name Description 00000 Config Configuration Register00001 Ioff Current offset calibration00010 Ign Current gain calibration00011 Voff Voltage offset calibration00100 Vgn Voltage gain calibration00101 Cycle Count Number of conversions to integrate over (N)00110 Pulse-Rate Used to calibrate/scale the energy to frequency output00111 I Last current value01000 V Last voltage value01001 P Last Power value01010 E Total energy value of last cycle01011 IRMS RMS current value of last cycle01100 VRMS RMS voltage value of last cycle01101 TBC Timebase Calibration01110 Poff Power Offset Register01111 Status Status Register10000 IACoff AC Current Offset Register10001 VACoff AC Voltage Offset Register10010 Res Reserved † . .10111 Res Reserved †11000 Res Reserved †11001 Test Reserved †11010 Mask Mask Register11011 Res Reserved †11100 Ctrl Control Register11101 Res Reserved † . .11111 Res Reserved †

† These Registers are for Internal Use only and should not be written to.

B7 B6 B5 B4 B3 B2 B1 B00 W/R RA4 RA3 RA2 RA1 RA0 0

CS5460A

DS284PP2 19

3.2 Serial Port Interface Pins

The CS5460A’s serial interface consists of fourcontrol lines: CS, SDI, SDO, and SCLK.

CS, Chip Select, is the control line which enablesaccess to the serial port. If the CS pin is tied to logic0, the port can function as a three wire interface.SDI, Serial Data In, is the data signal used to trans-fer data to the converters.

SDO, Serial Data Out, is the data signal used totransfer output data from the converters. The SDOoutput will be held at high impedance any time CSis at logic 1.

SCLK, Serial Clock, is the serial bit-clock whichcontrols the shifting of data to or from the ADC’sserial port. The CS pin must be held at logic 0 be-fore SCLK transitions can be recognized by theport logic. To accommodate opto-isolators SCLKis designed with a Schmitt-trigger input to allow anopto-isolator with slower rise and fall times to di-rectly drive the pin. Additionally, SDO is capableof sinking or sourcing up to 5 mA to directly drivean opto-isolator LED. SDO will have less than a400 mV loss in the drive voltage when sinking orsourcing 5 mA.

3.3 Serial Read and Write

The state machine decodes the command word as itis received. Data is written to and read from theCS5460A by using the Register Read/Write com-mand. Figure 9 illustrates the serial sequence nec-essary to write to, or read from the serial port’sbuffers. As shown in Figure 9, a transfer of data isalways initiated by sending the appropriate 8-bitcommand (MSB first) to the serial port (SDI pin).It is important to note that some commands use in-formation from the Cycle-Count Register and Con-figuration Register to perform the function. Forthose commands, it is important that the correct in-formation is written to those registers first.

3.3.1 Register Write

Command words instructing a register write mustbe followed by 24 bits of data. For instance, towrite the Configuration Register, the user wouldtransmit the command (0x40) to initiate the write.The CS5460A will then acquire the serial data in-put from the (SDI) pin when the user pulses the se-rial clock (SCLK) 24 times. Once the data isreceived the state machine would write the data tothe Configuration Register and return to the com-mand mode.

3.3.2 Register Read

Command words instructing a register read may beterminated at 8-bit boundaries (e.g., read transfersmay be 8, 16, or 24 bits in length). Also data regis-ter reads allow “command chaining”. For example,a command word instructs the state machine to reada signed output register. After the user pulsesSCLK for 16-bits of data, a write command word(e.g., to clear the Status Register) may be pulsed onto the SDI line at the same time the remaining8-bits of data are pulsed from the SDO line.

When a command involves a write operation, theserial port will continue to clock in the data bits(MSB first) on the SDI pin for the next 24 SCLKcycles. When a read command is initiated, the seri-al port will start transferring register content bitsserial (MSB first) on the SDO pin for the next 8, 16,or 24 SCLK cycles depending on the command is-sued. The micro-controller is allowed to send a newcommand while reading register data. The newcommand will be acted upon immediately andcould possibly terminate the register read. Duringthe read cycle, the SYNC0 command (NOP) shouldbe strobed on the SDI port while clocking the datafrom the SDO port.

CS5460A

20 DS284PP2

CS

SDI

SCLK

MSB MSBLSB

Command Time 8 SCLKs Data Time 24 SCLKs

LSB

SDI

MSB

SDO

LSB

MSB LSBCommand Time 8 SCLKs

Data Time 24 SCLKs

CS

SCLK

Figure 9. Command and Data Word Timing

Write Cycle

Read Cycle

CS5460A

DS284PP2 21

3.4 Serial Port Initialization

The serial port can be initialized to the commandmode in several different ways. One of these is byissuing the serial port initialization sequence. Theserial port initialization sequence involves clocking3 (or more) SYNC1 command bytes (0xFF) fol-lowed by one SYNC0 command byte (0xFE).There are other valid ways to set the chip into com-mand mode. For completeness, all of the possibleinitialization actions are listed here:

1) With power already on, issue Serial Port Initial-ization Sequence (described above). Or,

2) Power the chip on.

3) Wake the CS5460A out of Sleep Mode

4) Wake the CS5460A out of Stand-By Mode

5) Hardware Reset

6) Software Reset

Performing any of these actions will place the chipin the command mode, where it waits until a validcommand is received.

3.5 System Initialization

A software or hardware reset can be initiated at anytime. The software reset is initiated by writing alogic 1 to the RS (Reset System) bit in the configu-ration register, which automatically returns to logic0 after reset. At the end of the 32nd SCLK (i.e., 8 bitcommand word and 24 bit data word) internal syn-chronization delays the loading of the configura-tion register by 3 or 4 DCLK (MCLK/K). Then thereset circuit initiates the reset routine on the 1st fall-ing edge of MCLK.

A hardware reset is initiated when the RESET pinis forced low with a minimum pulse width of 50 ns.

The RESET signal is asynchronous, requiring noMCLKs for the part to detect and store a resetevent. The RESET pin is a Schmitt Trigger input,allows it to tolerate slow rise times and/or noisycontrol signals. (This can often turn out to be thecase, after a power failure or brown-out on thepower line.) Once the RESET pin is inactive, theinternal reset circuitry remains active for 5 MCLKcycles to insure resetting the synchronous circuitryin the device. The modulators are held in reset for12 MCLK cycles after RESET becomes inactive.After a hardware or software reset, the internal reg-isters (some of which drive output pins) will be resetto their default values on the first MCLK receivedafter detecting a reset event (see Table 2). TheCS5460A will then wait for a valid command on theserial port.

The reader should refer to the section titled “Regis-ter Description” for a complete description of theregisters listed in Table 2.

Configuration Register: 0x000001Offset Register: 0x000000Gain Registers 0x400000Pulse-Rate Register: 0x0FA000Cycle-Counter Register: 0x000FA0Timebase Register: 0x800000Status Register: 0x000000Mask Register: 0x000000Control Register: 0x000000AC Current Offset Register: 0x000000AC Voltage Offset Register: 0x000000Power Offset Register: 0x000000All Data Registers: 0x000000All Unsigned Data Registers 0x000000

Table 2. Internal Registers Default Value

CS5460A

22 DS284PP2

4. FUNCTIONAL DESCRIPTION

4.1 Pulse-Rate Output

As an alternative to reading the energy through theserial port, the EOUT and EDIR pins provide asimple interface with which signed energy can beaccumulated. Each EOUT pulse represents a prede-termined magnitude of energy. The accompanyingEDIR output represents the sign of the energy.With MCLK = 4.096 MHz, K = 1, the pulses willhave an average frequency equal to the frequencysetting in the Pulse Rate Register when the inputlevels into the voltage and current channels causefull-scale readings in the instantaneous voltage andcurrent registers. When MCLK/K is not equal to4.096 MHz, the user should scale the pulse-ratethat one would expect to get with MCLK/K =4.096 MHz by a factor of 4.096 MHz / (MCLK / K)to get the actual output pulse-rate.

EXAMPLE #1: Suppose that we want thepulse-frequency on the EOUT pin to be ‘IR’ = 100pulses per second (100 Hz) when the RMS-volt-age/RMS-current levels on the power line are220 V and 15 A respectively, noting that the max-imum rated levels on the power line are 250 V and20 A. We also assume that we have calibrated theCS5460A voltage/current channel inputs such thata DC voltage level of 250 mV across the volt-age/current channels will cause full-scale readingsof 1.0 in the CS5460A Instantaneous Voltage andCurrent Registers as well as in the RMS-Voltageand RMS-Current Registers. We want to find outwhat frequency value we should put into theCS5460A’s pulse-rate register (call this value‘PR’) in order to satisfy this requirement. Our firststep is to set the voltage and current sensor gainconstants, KV and KI, such that there will be accept-able input voltage levels on the inputs when thepower line voltage and current levels are at themaximum values of 250 V and 20 A, respectively.We need to calculate KV and KI in order to deter-mine the appropriate ratios of the voltage/current

transformers and/or shunt resistor values to use inthe front-end voltage/current sensor networks.

We assume here that we are dealing with a sinuso-idal AC power signal. For a sinewave, the largestRMS value that can be accurately measured (with-out over-driving the inputs) will register at ~0.7071of the maximum DC input level. Since power sig-nals are often not perfectly sinusoidal in real-worldsituations, and to provide for some over-range ca-pability, we will set the RMS-Voltage andRMS-Current Registers to measure at 0.6 when theRMS-values of the line-voltage and line-currentlevels are at 250 V and 20 A. Therefore, when theRMS registers measure 0.6, the voltage level at theinputs will be 0.6 x 250 mV = 150 mV. We nowfind our sensor gain constants, KV and KI, by de-manding that the voltage and current channel in-puts should be at 150 mV RMS when the powerline voltage and current are at the maximum valuesof 250 V and 20 A.

KV = 150 mV / 250 V = 0.0006

KI = 150 mV / 20 A = 0.0075 Ohms

These sensor gain constants can help determine theratios of the transformer or resistor-divider sensornetworks. We now use these sensor gain constantsto calculate what the input voltage levels will be onthe CS5460A inputs when the line-voltage andline-current are at 220 V and 15 A. We call thesevalues VVnom and VInom.

VVnom = KV * 220 V = 132 mV

VInom = KI * 15 A = 112.5 mV

The pulse rate on EOUT will be at ‘PR’ pulses persecond (Hz) when the RMS-levels of voltage/cur-rent inputs are at 250 mV. When the voltage/cur-rent inputs are set at VVnom and VInom, we want thepulse rate to be at ‘IR’ = 100 pulses per second. IRwill be some percentage of PR. The percentage isdefined by the ratios of VVnom/250 mV andVInom/250 mV with the following formula:

CS5460A

DS284PP2 23

We can rearrange the above equation and solve forPR. This is the value that we put into the pulse-rateregister.

Therefore we set the Pulse-Rate Register to~420.875 Hz. Therefore, the Pulse-Rate Registerwould be set to 0x00349C.

The above equation is valid when current channelis set to x10 gain. If current channel gain is set tox50, then the equation becomes:

where it is assumed that the current channel hasbeen calibrated such that the current-register willread at full-scale when the input voltage across theIIN+ and IIN- inputs is 50 mV (DC).

EXAMPLE #2: Suppose that instead of being giv-en a desired frequency of pulses per second to be is-sued at a specific voltage/current level, we aregiven a desired number of pulses per unit energy tobe present at EOUT, given that the maximumline-voltage is at 250 V (RMS) and the maximumline-current is at 20 A (RMS). For example, sup-pose that the required number of pulses per kW-hris specified to be 500 pulses/kW-hr. In such a situ-ation, the nominal line voltage and current do notdetermine the appropriate pulse-rate setting. In-stead, the maximum line-voltage and line-currentlevels must be considered. We use the given maxi-mum line-voltage and line-current levels to deter-mine KV and KI as previously described to get:

KV = 150 mV / 250 V = 0.0006

KI = 150 mV / 20 A = 0.0075 Ohms

where we again have calculated our sensor gainssuch that the maximum line-voltage and line-cur-rent levels will measure as 0.6 in the RMS-voltageand RMS-current registers.

We can now calculate the required Pulse-Rate Reg-ister setting by using the following equation:

Therefore PR = ~1.929 Hz.

Note that the Pulse-Rate Register cannot be set to afrequency of exact 1.929 Hz. The closest settingthat the Pulse-Rate register can obtain is 0x00003E= 1.9375. To improve the accuracy, either gain reg-ister can be programmed to correct for theround-off error in PR. This value would be calcu-lated as

4.2 Multi-Phase Option for Pulse Output

To allow for a simpler interface in a multi-phasesystem, the EOUT and EDIR pins can be connectedtogether and used in a wire-AND configuration. Inthis type of operation, the EWA bit in the Configu-ration Register must be activated (set to 1), and theuser must supply external pull-up devices in orderto pull the wire-AND output to logic-high. SeeFigure 11. The parts must be driven with the sameclock and programmed with different phases (seePH[1:0] bits in the Configuration Register). Thepulse width and the pulse separation is an integermultiple of system clocks (approximately equal to1/8 of the period of the contents of the pulse-rateregister). The maximum frequency is thereforeMCLK/K/8. A timing diagram for a multi-phasesystem is shown in Figure 10.

PulseRate IR PRVVnom

250mV------------------

VInom

250mV------------------⋅ ⋅= =

PRIR

VVnom

250mV------------------

VInom

250mV------------------×

-------------------------------------------- 100Hz132mV250mV------------------ 112.5mV

250mV-----------------------×

------------------------------------------------= =

PRIR

VVnom

250mV------------------

VInom

50mV---------------×

-----------------------------------------=

PR 500pulseskW hr⋅------------------ 1hr

3600s-------------- 1kW

1000W------------------ 250mV

KV------------------ 250mV

KI------------------⋅ ⋅ ⋅ ⋅=

Ign or VgnPR

1.929------------- 1.00441≅ 0x404830= =

CS5460A

24 DS284PP2

CS5460A

CS5460A

CS5460A

EOUT

EDIR

EOUT

EDIR

EOUT

EDIR

EOUT

EDIR

VDD

5 K5 K

Figure 11. Option for wire and configuration of EOUT and EDIR pins for multi-phase metering

Phase - 00

Phase - 01

Phase - 10

Phase - 11t

@Pulse-Rate Register Period

8

N

MCLK/K= for Integer N

t

t

Figure 10. Multi-Phase System (Normal Mode only)

CS5460A

DS284PP2 25

4.3 Pulse Output for Normal Mode, Stepper Motor Mode and Mechanical Counter Mode

The EOUT and EDIR output formats can be modi-fied so that the time duration of the pulses is in-creased to the point that they can drive either anelectro-mechanical counter or a stepper motor.These modes are controlled by setting certain bitsin the Control Register.

4.3.1 Normal Mode

Referring to the description of the Control Registerin Section 5., REGISTER DESCRIPTION, if boththe MECH and STEP bits are set to ‘0’, the EOUTand EDIR pulse outputs for a single CS5460A havethe same format as the “Phase - 00” signal shownin Figure 10--active-low pulses with very shortwidth. When energy is positive, EDIR is alwayshigh. When energy is negative, EDIR has the sameoutput as EOUT. When MCLK/K is not equal to4.096 MHz, the user can predict the pulse-rate

4.3.2 Mechanical Counter Mode

Setting the MECH bit in the control register to ‘1’and the STEP bit to ‘0’ enables wide stepping puls-es for mechanical counters and similar appliances.In this mode, active-low pulses are 128 ms widewhen using a 4.096 MHz crystal and K=1. Whenenergy is positive, the pulses appear on EOUT.

When energy is negative, pulses appear on EDIR.It is up to the user to insure that pulses will not oc-cur at a rate faster than the 128 ms pulse duration,or faster than the mechanical counter can accom-modate. The user must make sure that thePulse-Rate Register is set to an appropriate value.Because the duration of each pulse is set to 128 ms,the maximum output pulse frequency is limited to~7.8 Hz. (See Figure 12.) For values of MCLK / Kdifferent than 4.096 MHz, the duration of one pulseis (128 * 4.096 MHz)/(MCLK / K) milliseconds.

4.3.3 Stepper Motor Mode

Setting the STEP bit in the control register to ‘1’and the MECH bit to ‘0’ transforms the EOUT andEDIR pins into two stepper motor phase outputs.When an energy pulse occurs, one of the outputschanges state. When the next energy pulse occurs,the other output changes state. The direction themotor will rotate is determined by the order of thestate changes. When energy is positive, EOUT willlead EDIR. When energy is negative, EDIR willlead EOUT. See Figure 13.

4.4 Auto-Boot Mode Using EEPROM

The CS5460A has a MODE pin. When the MODEpin is set to logic low, the CS5460A is in normaloperating mode, called command mode. Thismode denotes the normal operation of the part, that

128 ms

128 msEOUT

EDIRPositive Energy Negative Energy

Figure 12. Mechanical Counter Mode on EOUT and EDIR

EOUT

EDIRPositive Energy Negative Energy

Figure 13. Stepper Motor Mode on EOUT and EDIR

CS5460A

26 DS284PP2

has been described so far. But when this pin is setto logic high, the CS5460A auto-boot mode is en-abled. In auto-boot mode, the CS5460A is config-ured to request a memory download from anexternal serial EEPROM. The download sequenceis initiated by driving the /RESET pin to logic high.Auto-Boot mode allows the CS5460A to operatewithout the need for a microcontroller. Note that ifthe MODE pin is left unconnected, it will default tologic low because of an internal pull-down on thepin.

Figure 14 shows the typical connections betweenthe CS5460A and a serial EEPROM for proper au-to-boot operation. In this mode, /CS and SCLK aredriven outputs. SDO is always an output. Duringthe auto-boot sequence, the CS5460A drives /CSlow, provides a clock output on SCLK, and drivesout-commands on SDO. It receives the EEPROMdata on SDI. The serial EEPROM must be pro-grammed with the user-specified commands andregister data that will be used by the CS5460A toinitialize and begin conversions.

Figure 14 also shows the external connections thatwould be made to a calibrator device, such as a PCor custom calibration board. When the meteringsystem is installed, the calibrator would be used to

control calibration and/or to program user-speci-fied commands and calibration values into the EE-PROM. The user-specified commands/data willdetermine the CS5460A’s exact mode of operationonce the auto-boot sequence is initiated. Any of thevalid commands can be used. For example, the EE-PROM can be programmed so that it would firstsend out commands that write calibration values tothe calibration registers inside the CS5460A, then itcould enable the EOUT and EDIR functionalityand set a Pulse-Rate Register value. Finally, thecode can send out the commands to initiate contin-uous conversions, and to set the pulse-output modeto specific format (e.g., set the MECH bit in theControl Register). The serial data for such a se-quence is shown below in single-byte hexidecimalnotation:

40 00 00 61 ;In configuration Register,turn high-pass filters on, set K= 1.

44 7F C4 A9 ;Write value of 0x7FC4A9 toCurrent Gain Register.

46 7F B2 53 ;Write value of 0xFFB253 toDC Voltage Offset Register.

4C 00 00 14 ;Set Pulse Rate Register to0.625 Hz.

CS5460AEEPROM

/EOUT

/EDIR

MODE

SCK

SDI

SDO

/CS

SCK

SO

SI

/CS

Connector to Calibrator

VD+

5 K

5 K

Figure 14. Typical Interface of EEPROM to CS5460A

CS5460A

DS284PP2 27

E8 ;Start continuous conversions.

78 00 01 40 ;Write stop bit to CS5460A toterminate auto-boot sequence,and set the EOUT pulses toMechanical Counter Mode.

This data from the EEPROM will drive the SDI pinof the CS5460A during the auto-boot sequence.

The following sequence of user-controlled eventswill cause the CS5460A to enter auto-boot mode:(A simple timing diagram for this sequence isshown below in Figure 15.) After the CS5460Ahas been powered on and has been allowed to ini-tialize, if the MODE pin is set to logic high, thenchanging the /RESET pin from active state to inac-tive state (low to high) will cause CS5460A tobring the /CS pin low, and then issue the standardblock read command out of the SDO line. Then theCS5460A will continue to issue SCLKs, to acceptdata from the EEPROM. A more detailed timingdiagram can be found in the SWITCHING CHAR-ACTERISTICS section of this data sheet.

Several industry-standard serial EEPROMs thatwill successfully run auto-boot with the CS5460Aare listed below:

• Atmel

AT25010AT25020AT25040

• National Semiconductor

NM25C040M8NM25020M8

• Xicor

X25040SI

These types of serial EEPROMs expect a specific8-bit command word (00000011) in order to per-form a memory download. The CS5460A has beenhardware programmed to transmit this 8-bit com-mand word to the EEPROM at the beginning of theauto-boot sequence.

The auto-boot sequence is terminated by writing a‘1’ to the STOP bit in the CS5460A’s Control Reg-ister. This action is performed as the last commandin the EEPROM command sequence. Once thisevent occurs, SCLK stops, and /CS rises, therebyreducing power consumed by the EEPROM. Whenthe CS5460A is commanded by the EEPROM toperform a certain operation, it will continue to exe-cute that operation after the STOP bit has been re-ceived. In the above example, the ‘continuousconversion’ command (0xE8) is issued from theEEPROM, and therefore the CS5460A will contin-ue performing conversions even after the STOP bitis written.

RES

CS

SCLK

SDO

SDI

EE Read Address 0

5460A Commands Stop

MODE

Figure 15. Timing Diagram for Auto-Boot Sequence

CS5460A

28 DS284PP2

4.5 Interrupt and Watchdog Timer

4.5.1 Interrupt

The INT pin is used to indicate that an event hastaken place in the converter that needs attention.These events inform the system about operationconditions and internal error conditions. The INTsignal is created by combining the Status registerwith the Mask register. Whenever a bit in the Statusregister becomes active, and the corresponding bitin the Mask register is a logic 1, the INT signal be-comes active. The interrupt condition is clearedwhen the bits of the Status Register are returned totheir inactive state.

4.5.1.1 Clearing the Status Register

Unlike the other registers, the bits in the StatusRegister can only be cleared (set to logic 0). Whena word is written to the Status Register, any 1s inthe word will cause the corresponding bits in theStatus Register to be cleared. The other bits of theStatus Register remain unchanged. This allows theclearing of particular bits in the register withouthaving to know the state of the other bits. Thismechanism is designed to facilitate handshakingand to minimize the risk of losing events that ha-ven’t been processed yet.

4.5.1.2 Typical use of the INT pin

The steps below show how interrupts can be han-dled.

• Initialization:

Step I0 - All Status bits are cleared by writingFFFFFF (Hex) into the Status Register.

Step I1 - The conditional bits which will beused to generate interrupts are then written tologic 1 in the Mask register.

Step I3 - Enable interrupts.

• Interrupt Handler Routine:

Step H0 - Read the Status Register.

Step H1 - Disable all interrupts.

Step H2 - Branch to the proper interrupt serviceroutine.

Step H3 - Clear the Status Register by writingback the value read in step H0.

Step H4 - Re-enable interrupts.

Step H5 - Return from interrupt service routine.

This handshaking procedure insures that anynew interrupts activated between steps H0 andH3 are not lost (cleared) by step H3.

4.5.1.3 INT Active State

The behavior of the INT pin is controlled by the SI1and SI0 bits of the configuration register. The pincan be active low (default), active high, active on areturn to logic 0 (pulse-low), or active on a returnto logic 1 (pulse-high).

4.5.1.4 Exceptions

The IC (Invalid Command) bit of the Status Regis-ter can only be cleared by performing the port ini-tialization sequence. This is also the only StatusRegister bit that is active low.

To properly clear the WDT (WatchDog Timer) bitof the Status Register, first read the Energy Regis-ter, then clear the bit in the Status Register.

4.5.2 Watch Dog Timer

The Watch Dog Timer (WDT) is provided asmeans of alerting the system that there is a potentialbreakdown in communication with the micro-con-troller. By allowing the WDT to cause an interrupt,a controller can be brought back, from some un-known code space, into the proper code for pro-cessing the data created by the converter. Thetime-out is preprogrammed to approximately 5 sec-onds. The countdown restarts each time the Energyregister is read. Under typical situations, the Ener-gy register is read every second. As a result, theWDT will not time out. Other applications that usethe watchdog timer will need to ensure that the En-

CS5460A

DS284PP2 29

ergy register is read at least once in every 5 secondspan.

4.6 Oscillator Characteristics

XIN and XOUT are the input and output, respec-tively, of an inverting amplifier to provide oscilla-tion and can be configured as an on-chip oscillator,as shown in Figure 16. The oscillator circuit is de-signed to work with a quartz crystal or a ceramicresonator. To reduce circuit cost, two load capaci-tors C1 are integrated in the device, one betweenXIN and DGND, one between XOUT and DGND.Lead lengths should be minimized to reduce straycapacitance. With these load capacitors, the oscil-lator circuit is capable of oscillation up to 20 MHz.To drive the device from an external clock source,XOUT should be left unconnected while XIN isdriven by the external circuitry. There is an ampli-fier between XIN and the digital section which pro-vides CMOS level signals. This amplifier workswith sinusoidal inputs so there are no problemswith slow edge times.

The CS5460A can be driven by a clock rangingfrom 2.5 to 20 MHz. The user must appropriatelyset the K divider value such that the internal DCLKwill run somewhere between 2.5 MHz and 5 MHz.The K divider value is set with the K[3:0] bits in theConfiguration Register. As an example, if XIN =MCLK = 15 MHz, and K is set to 5, then DCLK is3 MHz, which is a valid value for DCLK. Note thatif the K[3:0] bits are all set to zero, the value of theK divider value is 16.

4.7 Analog Inputs

The CS5460A accommodates a full scale range of150 mVRMS on both input channels. System cali-bration can be used to increase or decrease the fullscale span of the converter as long as the calibra-tion register values stay within the limits specified.See Section 4.9, Calibration, for more details.

The current input channel has an input range of30 mVRMS when the internal x50 gain stage is en-

abled. This signal range is designed to handle lowlevel signals from a shunt sensor.

4.8 Voltage Reference

The CS5460A is specified for operation with a+2.5 V reference between the VREFIN and VA-pins. The converter includes an internal 2.5 V ref-erence (60 ppm/°C drift) that can be used by con-necting the VREFOUT pin to the VREFIN pin ofthe device. If higher accuracy/stability is required,an external reference can be used.

4.9 Calibration

4.9.1 Overview of Calibration Process

The CS5460A offers AC or DC calibration. Theuser decides which calibration is being performedby setting/clearing one or more of the 8 bits in theCalibration command word. Regardless of wheth-er an AC or DC calibration is desired, there are twocalibration modes: system offset and system gain.During calibration, the user must supply the inputcalibration signals to the “+” and “-” pins of thevoltage-/current-channel input. These input cali-bration signals represent full-scale and ground in-put levels. Whether it is AC or DC calibration, theuser must provide the positive full-scale referencesignals to perform a system gain calibration, and a

OscillatorCircuit

DGND

XIN

XOUT

C1

C1 = 22 pF

C1

Figure 16. Oscillator Connection

CS5460A

30 DS284PP2

ground-referenced signal to perform a system off-set calibration. The differential voltage levels ofthe user-provided calibration signals must be with-in the specified voltage input limits (refer to “Dif-ferential Input Voltage Range” in Section 1.,Characteristics and Specifications). The voltagelevel of these calibration input signals must bewithin the specified calibration limits for each spe-cific calibration step and channel.

4.9.2 The Calibration Registers

Since both the voltage and current channels haveseparate offset and gain registers associated withthem, the system offset or system gain can be per-formed on either channel without the calibrationresults from one channel affecting the other. Re-ferring to Figure 6, it is important to note that forboth the voltage channel and current channel, thereare separate calibration registers for the AC and DCoffset corrections. This is not true for gain correc-tions, as there is only one gain register per chan-nel--AC and DC gain calibration results are storedin the same register. The results in the gain regis-ters reflect either the AC or DC gain calibration re-sults, whichever was performed most recently.Both a DC and AC offset can be applied to the sys-tem at the same time, but only one gain calibrationcan be applied to the system. The user must decidewhich type of gain calibration will be used: AC orDC, but not both. Therefore, the following six reg-isters exist:

• Voltage Gain Register

• Current Gain Register

• DC Voltage Offset Register

• DC Current Offset Register

• AC Voltage Offset Register

• AC Current Offset Register

Referring to Figure 6, one should note that the ACOffset Registers affect the output results differentlythan the DC Offset Registers. The DC offset values

are applied to the voltage/current signals very earlyin the signal path, and so the DC Offset Registervalue affects all CS5460A results. This is not truefor the AC Offset. The AC Offset Registers onlyaffect the results of the rms-voltage/rms-currentcalculations.

4.9.3 Calibration Sequence

The basic flow of the calibration sequence is to firstapply the appropriate calibration signals to the “+”and “-” pins of the voltage/current channel inputs,and then the user must send the appropriate calibra-tion command to the CS5460A. The calibrationcommand is an 8-bit command. Various bits with-in this command specify the exact type of calibra-tion that is to be performed (e.g., AC gain cal forvoltage channel, DC offset cal for current channel,etc.) After the CS5460A is finished running its in-ternal calibration, and storing the results in the ap-propriate calibration registers, the DRDY bit is set(in the Status Register) to indicate that the calibra-tion sequence has been completed.

Note that when the calibration command is sent tothe CS5460A by the user, the device should NOTbe running in conversion mode. The calibrationwill not run if the part is already running in eitherof the two available conversion modes.

Figure 17 shows the basic setup for gain calibra-tion. If a DC gain calibration is desired, the usershould apply a DC voltage level that truly repre-sents the absolute maximum voltage level that willbe needs to be measured across the inputs.a DCvoltage level that represents the desired absolutepeak full-scale value. However, in many practicalpower metering situations, an AC signal is pre-ferred over a DC signal to calibrate the gain. If theuser decides to perform AC gain calibration insteadof DC, the user should apply an AC reference sig-nal that is set to the desired maximum RMS level.In general, the RMS level of the AC gain calibra-tion signals will need to be significantly lower thanthe maximum output value of the instantaneous

CS5460A

DS284PP2 31

voltage and current registers in order to avoid clip-ping the signals when they reach their maximumpeak value. For example, the largest sinusoid thatcan be used in AC calibration is one whoseRMS-value is ~0.7071 of the value of the peak DCinput voltage value.

For the offset configuration, there is no differencebetween the AC and DC calibration signals, as theuser should simply ground the voltage-/cur-rent-channel input(s) during this calibration. (SeeFigure 18.)

The user should not try to run both an offset andgain calibration at the same time. This will causeundesirable calibration results.

4.9.4 Duration of Calibration Sequence

The value of the Cycle Count Register (N) deter-mines the number of conversions averaged to ob-tain the calibration results. When N is increased bythe user, the accuracy of the calibration results willincrease. For DC offset/gain calibrations, the cali-bration sequence always takes at least N + 30 con-version cycles to complete. For AC offset/gaincalibrations, the calibration sequence takes at least6N + 30 A/D conversion cycles to complete, (about6 computation cycles). For all calibrations (AC orDC), once a calibration cycle is complete, theDRDY bit is set and the results are stored in eitherthe gain or offset registers.

4.9.5 Description of Calibration Algorithms

The algorithms for the AC and DC calibrations areshown in Figure 19. This figure applies to both thevoltage channel and the current channel. The fol-lowing descriptions of calibration algorithms willfocus on the voltage channel, but apply equally tothe current channel.

The AC voltage gain calibration algorithm attemptsto adjust the voltage gain register value so that thecalibration reference signal level presented at thevoltage inputs will result in a value of 0.6 in theRMS-voltage register. The level of the calibrationsignal is determined by the user. During AC volt-age gain calibration, the value in the RMS-voltageregister is divided into 0.6. This result is the ACgain calibration value, stored in the gain register.

Note: For proper calibration, it is assumed that the value of the Voltage/Current Gain Registers are set to 1.0 before running the gain calibration(s), and the value in the AC and DC Offset Registers is set to 0 before running calibrations. This can be accomplished by a software or hardware reset of the device. The values in the Voltage/Current Gain Registers do affect the results of the AC/DC gain calibrations.

+

-

XGAIN

+

-

ExternalConnections

+-

AIN+

AIN-CM +-

Full Scale(DC or AC)

Figure 17. System Calibration of Gain.

+

-

XGAIN

+

-

ExternalConnections

0V +-

AIN+

AIN-CM +-

Figure 18. System Calibration of Offset.

CS5460A

32 DS284PP2

The idea of the AC offset calibration is to obtain anoffset value that reflects the square of the RMS out-put level when the inputs are grounded. Duringnormal operation, when the CS5460A is calculat-ing the latest result for the RMS-Voltage Register,this AC offset register value will be subtractedfrom the square of each successive voltage samplein order to nullify the AC offset that may be inher-ent in the voltage-channel signal path. Note thatthe value in the AC offset register is proportional tothe square of the AC offset. First, the inputs shouldbe grounded by the user, and then the AC offset cal-ibration command should be sent to the CS5460A.When the AC offset calibration sequence is initiat-ed by the user, the most recent RMS-Voltage Reg-ister result is squared. This value is then subtractedfrom the square of each voltage sample that comesthrough the RMS data path. See Figure 19.

After the user-provided calibration voltage hasbeen applied to the inputs, the CS5460A deter-mines the DC Gain Register value by averaging theoutput signal values over one computation cycle (Nsamples) and then dividing this average into 1.Therefore, after the DC voltage gain calibration hasbeen executed, the instantaneous voltage registerwill read at full-scale when the DC level of the in-put signal is equal to the level of the DC calibrationsignal that was applied to the voltage channel in-

puts during the DC gain calibration. For example,if a 240 mV DC signal is applied to the voltagechannel inputs during the DC gain calibration forthe current channel, then the Instantaneous VoltageRegister will measure at unity whenever a 240 mVDC level is applied to the voltage channel inputs.

The DC offset register holds the negative of thesimple average of N samples taken while the DCcalibration was executed. The inputs should begrounded during DC offset calibration. The DCoffset value is added to the signal path to nullify theDC offset in the system.

4.9.6 Is Calibration Required?

The CS5460A does not have to be calibrated. Afterthe part is reset or powered on, the device is func-tional and can perform measurements without be-ing calibrated. The output register values will beaffected by the default values of the on-chip regis-ters (Gain = 1.0, DC Offset = 0.0, AC Offset = 0).Although the device can be used without perform-ing an offset or gain calibration, the accuracy andlinearity specs of the CS5460A will not be validuntil after a gain/offset calibration is performed.Note that the 0.1% linearity specs in this data sheetassume that the device has been calibrated withMCLK = 4.096 MHz, K = 1, and N = 4000.

In Modulator + x

to V*, I*, P*, E* Registers

Filter

N

V RMS

N

Σ

÷

SINC

DC Offset* Gain*

+X2

X

-X

1x

N

AC Offset*

X2

0.6x

++

-+2 *÷

* Denotes readable/writable register

Figure 19. Calibration Data Flow

CS5460A

DS284PP2 33

4.9.7 Calibration Tips

To minimize digital noise, the user should wait foreach calibration step to be completed before read-ing or writing to the serial port.

After a calibration is performed, the offset and gainregister contents can be read and stored externally.by the system micro-controller and recorded inmemory. The same calibration words can be up-loaded into the offset and gain registers of the con-verters when power is first applied to the system, orwhen the gain range on the current channel ischanged.

An offset calibration should be performed before again calibration. Each gain calibration depends onthe zero calibration point obtained from the offsetcalibration.

4.10 Phase Compensation

Bits 23 to 17 of the Configuration Register are usedto program the amount of phase delay that is addedto the voltage channel signal path. This phase de-lay is applied to the voltage channel signal in orderto compensate for phase delay that is may be intro-duced by the user-supplied voltage and current sen-sor circuitry, which is external to the CS5460A.Voltage and current transformers, as well as othersensor equipment applied to the front-end of theCS5460A inputs can often introduce a phase delayin the system, which distorts the phase relationshipbetween the voltage and current signals that are tobe measured. The user can set the phase compen-sation bits to nullify this undesirable phase distor-tion between the two channels.

The CS5460A does not provide automatic phasecalibration. The user must determine the phasecompensation empirically. The default value of thephase compensation bits is 0000000. With this de-fault setting, the phase delay on the voltage channelis ~0.0215 degrees (assuming a 60 Hz power sig-nal). Note that the 7-bit phase compensation wordis a 2’s complement binary number. With MCLK

= 4.096 MHz and K=1, the range of the internalphase compensation ranges from -2.8 degrees to+2.8 degrees when the input voltage/current signalsare at 60 Hz. In this condition, each step of thephase compensation register (value of one LSB) is~0.04 degrees. For values of MCLK other than4.096 MHz, these values for the span (-2.8 to +2.8degrees) and for the step size (0.04 degrees) shouldbe scaled by 4.096 MHz / (MCLK / K). For powerline frequencies other than 60Hz (e.g., 50 Hz), theuser can predict the values of the range and stepsize by converting the above values to time-do-main, and then computing the new range and stepsize in terms of degrees with respect to the new linefrequency.

To calibrate the phase delay, the user may try ad-justing the phase compensation bits while theCS5460A is in normal continuous conversionmode. Before doing so, the user should provide apurely resistive load (no inductance or capacitance)to the power line, such that nominal-level voltageand current signals from the power line are sensedinto the voltage and current channels of theCS5460A. In this condition, any phase delay be-tween the measured voltage and current signals isdue only to phase delay introduced by the user’sexternal voltage/current sensor circuitry. The ob-jective is to adjust the phase compensation bits un-til the Energy Register value is maximized.

4.11 Time-Base Calibration Register

The Time-Base Calibration Register (notated as“TBC” in Figure 6) is used to compensate for slighterrors in the XIN frequency. External oscillatorsand crystals have certain tolerances. If the user isconcerned about improving the accuracy of theclock for energy measurements, the Time-BaseCalibration Register can be manipulated to com-pensate for the frequency error. Note from Figure6 that the TBC Register only affects the value in theEnergy Register.

CS5460A

34 DS284PP2

As an example, if the desired XIN frequency is4.096 MHz, but the crystal is measured to actuallybe 4.091 MHz. The ratio of the desired frequencyto the actual frequency is 4.096 MHz/4.091 MHz =~1.00122219506. The TBC Register can be set to1.0012223364 = 0x80280C(h), which is very closeto the desired ratio.

4.12 Power Offset Register

Referring to Figure 6, note the Poff Register that ap-pears just after the power computation. This regis-ter can be used to offset system power sources thatmay be resident in the system, but do not originatefrom the power line signal. These sources of extraenergy in the system contribute undesirable andfalse offsets to the power/energy measurement re-sults. For example, when a voltage signal is ap-plied to the voltage channel inputs and the currentchannel has no line current, the current channelmay still register a very small amount of current.This current measurement is cause by leakage ofthe voltage channel input signal into the currentchannel input signal path. The user can experimen-tally determine the amount of stray power thatmight be induced into the input pins, and then pro-gram the Power Offset Register to nullify the ef-fects of this unwanted energy.

4.13 Input Protection and Filtering

In Figure 4 and Figure 5, note the series resistorRPI which is connected to the IIN+ input pin. Thisresistor is used to provide current-limit protectionfor the current-channel input pin in the event of apower surge or lightening surge. The voltage/cur-rent-channel inputs have surge-current limits of100 mA. This applies to brief voltage/currentspikes (<500 msec). The limit is 10 mA for DC in-put overload situations.

The VIN+ pin does not need a protection resistorfor the configurations shown in Figure 4 andFigure 5. This is because a resistive voltage-divid-er is used as the sensor, and so series resistance is

already provided to the VIN+ input pin. InFigure 5, if a voltage transformer is used as thevoltage sensor, then a resistor RPV should be in-stalled in series with the VIN+ pin.

Figure 4 shows how the analog inputs are connect-ed for a common-mode configuration. Figure 5shows a differential configuration. A differentialinput configuration can be used, because the volt-age/current channel inputs are able to accept inputvoltage levels all the way down to -250 mV belowthe potential of the VA- pin (which is normallyconnected to ground). Note that a differential con-figuration could have been used in Figure 4, and acommon-mode input configuration could havebeen used in Figure 5. If the negative sides of theCS5460A input channels are not grounded (i.e., ifVIN- and IIN- are connected in a differential con-figuration) then it is appropriate to put protectionresistors on these inputs as well (see Figure 5). Infact, even in the common-mode configuration, pro-tection resistors and filter caps may be placed onthe VIN- and IIN- inputs in order to provide a morebalanced configuration, to improve common-moderejection of very high-frequency EMI.

Capacitors CPV and CPI should be included to pro-vide for attenuation of high-frequency noise thatmay be coupled into the input lines. In differentialinput configurations, such a capacitor should beadded to the VIN- and IIN- pins in addition to theVIN+ and IIN+ pins. These capacitors should beplaced in close proximity to the input pins for opti-mal protection against EMI.

Values for RPV/I and CPV/I must be chosen with theapproximate input lowpass cutoff frequency inmind. In general, the cutoff frequency should notbe less than 10 times the roll-off frequencies of theinternal voltage/current channel filters (seeFigure 7 and Figure 8). From these figures we seethat the internal voltage channel roll-off is at~1400 Hz while the current channel roll-off is at~1600 Hz. If the cutoff frequency of the external

CS5460A

DS284PP2 35

protection is much less than 10x these values(14000 Hz and 16000 Hz), then some of the har-monic content that may be present in the volt-age/current signals may start to get attenuated bythis input filtering, which is undesirable.

The exact values of RPV/I and CPV/I must be calcu-lated for each particular application. The primarygoal is to make sure that the input pins never re-ceive transient input currents greater than 100 mA.Also, they should never be exposed to DC currentsgreater than 10 mA. The user-supplied protectionresistors RPV and RPI will limit the current thatcomes into the pins in over-voltage situa-tions--when the internal protection diodes turn oninside the CS5460A. For example, suppose that thevalue for RPI (on the current channel input) waschosen to be 1000 Ohms. Then we know that thecurrent channel can withstand brief voltage spikesof up to ~100 V (referenced to GND) without dam-age to the part. This is because 100 V / 1000 Ohm= 100 mA. The pin will also be protected for up to~10 VDC, as we see that 10V / 1000 Ohm =10 mA.

When computing appropriate values for RPV/I, thedifferential input impedance of the CS5460A’svoltage channel and current channel should also beconsidered. This is especially true for the currentchannel, which has a lower differential input im-pedance than the voltage channel. These imped-ance specs are given at the beginning of this datasheet (see the specification titled “Effective InputImpedance” for the voltage and current channels).For example, the differential input impedance inthe current channel is spec’d to be 30 kOhm. Asthe user increases the value of RPI to provide formore and more common-mode surge protection,the voltage drop across the external protection re-

sistor increases, and it divides the input signaldown more and more. This in turn reduces the dy-namic range of the signals that are ultimately pre-sented to the CS5460A’s inputs. This voltagedivision by the protection resistors can sometimesby minimized, or even totally avoided: When pos-sible, the user should first consider the input pro-tection that is going to be necessary, and thendetermine the sensor gains such that the drop acrossthe protection resistors is taken into account.

Typical values for these components are RPI =500 Ohm, CPI = 0.02 uF, CPV = 0.002 uF and ifnecessary, RPV = 5 kOhm.

4.14 PCB Layout

The CS5460A should be placed entirely over an an-alog ground plane with both the VA- and DGNDpins of the device connected to the analog plane.Place the analog-digital plane split immediately ad-jacent to the digital portion of the chip.

Note: See the CDB5460 data sheet for suggested layout details and Applications Note 18 for more detailed layout guidelines. Before layout, please call for our Free Schematic Review Service.

CS5460A

36 DS284PP2

5. REGISTER DESCRIPTION

Note: 1. ** “default” => bit status after software or hardware reset

2. Note that all registers can be read from, and written to.

5.1 Configuration Register Address: 0

Default** = 0x000001

K[3:0] Clock divider. A 4 bit binary number used to divide the value of MCLK to generate the internal clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-tween 1 and 16. Note that a value of “0000” will set K to 16 (not zero).

iCPU Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals are sampled, the logic driven by CPUCLK should not be active during the sample edge.0 = normal operation (default)1 = minimize noise when CPUCLK is driving rising edge logic

IHPF Control the use of the High Pass Filter on the Current Channel.0 = High-pass filter is disabled. If VHPF is set, use all-pass filter. Otherwise, no filter is used. (default)1 = High-pass filter is enabled.

VHPF Control the use of the High Pass Filter on the voltage Channel.0 = High-pass filter is disabled. If IHPF is set, use all-pass filter. Otherwise, no filter is used. (default)1 = High-pass filter enabled

23 22 21 20 19 18 17 16PC6 PC5 PC4 PC3 PC2 PC1 PC0 Gi

15 14 13 12 11 10 9 8EWA PH1 PH0 SI1 SI0 EOD DL1 DL0

7 6 5 4 3 2 1 0RS VHPF IHPF iCPU K3 K2 K1 K0

CurrentChannel

VoltageChannel

Cycle-Counter Register (1 × 24)

Gain Register (1 × 24)

Gain Register (1 × 24)

Configuration Register (1 × 24)

Status Register (1 × 24)

Serial Interface

Pulse-Rate Register (1 × 24)

Mask Register (1 × 24)

Timebase Register (1 × 24)

Offset Register (1 × 24)

Offset Register (1 × 24)

Unsigned Output Registers (2 × 24)(I , V )

Command WordState Machine

Transmit Buffer

Receive Buffer

Signed Output Registers (4 × 24)(I, V, P, E)

RMS RMS

24-Bit

SDI

CS

SDO

SCLK

INT

DC

DC

AC/DC

AC/DC

AC Offset Register

AC Offset Register

Control Register

Power Offset Register

Figure 20. CS5460A Register Diagram

CS5460A

DS284PP2 37

RS Start a chip reset cycle when set 1. The reset cycle lasts for less than 10 XIN cycles. The bit is automatically returned to 0 by the reset cycle.

DL0 When EOD = 1, EDIR becomes a user defined pin. DL0 sets the value of the EDIR pin.Default = ’0’

DL1 When EOD = 1, EOUT becomes a user defined pin. DL1 sets the value of the EOUT pin.Default = ’0’

EOD Allows the EOUT and EDIR pins to be controlled by the DL0 and DL1 bits. EOUT and EDIR can also be accessed using the Status Register.0 = Normal operation of the EOUT and EDIR pins. (default)1 = DL0 and DL1 bits control the EOUT and EDIR pins.

SI[1:0] Soft interrupt configuration. Select the desired pin behavior for indication of an interrupt.00 = active low level (default)01 = active high level10 = falling edge (INT is normally high)11 = rising edge (INT is normally low)

PH[1:0] Set the phase of the EOUT and EDIR output pin pulse. The EOUT and EDIR pins, on different phases, can be wire-ANDed together as a simple way of summing the frequency of different parts.00 = phase 0 (default)01 = phase 110 = phase 211 = phase 3

Note: The above pulse-phase settings for multi-phase metering are intended for use in Normal Mode only, NOT intended for use in Stepper Mode and Mechanical Counter Mode.

EWA Allows the output pins of EOUT and EDIR of multiple chips to be connected in a wire-AND, us-ing an external pull-up device.0 = normal outputs (default)1 = only the pull-down device of the EOUT and EDIR pins are active

Gi Sets the gain of the current PGA0 = gain is 10 (default)1 = gain is 50

PC[6:0] Phase compensation. A 2’s complement number used to set the delay in the voltage channel. When MCLK=4.096 MHz and K=1, the phase adjustment range is about -2.8 to +2.8 degrees and each step is about 0.04 degrees (this assumes that the power line frequency is 60 Hz). If (MCLK / K) is not 4.096 MHz, the values for the range and step size should be scaled by the factor 4.096MHz / (MCLK / K).Default setting is 0000000 = 0.0215 degrees phase delay (when MCLK = 4.096 MHz).

CS5460A

38 DS284PP2

5.2 DC Current Offset Register and DC Voltage Offset RegisterAddress: 1 (DC Current Offset Register)

3 (DC Voltage Offset Register)

Default** = 0.000

The DC Offset Registers are initialized to zero on reset, allowing the device to function and perform measure-ments. The register is loaded after one computation cycle with the current or voltage offset when the proper input is applied and the DC Calibration Command is received. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensa-tion. The value is in the range ± full scale. The numeric format of this register is two’s complement notation.

5.3 AC/DC Current Gain Register and AC/DC Voltage Gain RegisterAddress: 2 (Current Gain Register)

4 (Voltage Gain Register)

Default** = 1.000

The Gain Registers are initialized to 1.0 on reset, allowing the device to function and perform measurements. The Gain Registers hold the result of either the AC or DC gain calibrations, whichever was most recently per-formed. If DC calibration is performed, the register is loaded after one computation cycle with the system gain when the proper DC input is applied and the Calibration Command is received. If AC calibration is performed, then after ~(6N + 30) A/D conversion cycles (where N is the value of the Cycle-Count Register) the register(s) is loaded with the system gain when the proper AC input is applied and the Calibration Command is received. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensation. The value is in the range 0.0 ≤ Gain < 4.0.

5.4 Cycle Count Register Address: 5

Default** = 4000

The Cycle Count Register determines the length of an energy and RMS conversion. A conversion cycle is de-rived from (MCLK/K)/(1024∗N) where MCLK is master clock, K is clock divider, and N is cycle count. N must be greater than 10 for IRMS, VRMS and energy calculations to be performed.

MSB LSB

-(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

21 20 2-1 2-2 2-3 2-4 2-5 2-6 ..... 2-16 2-17 2-18 2-19 2-20 2-21 2-22

MSB LSB

223 222 221 220 219 218 217 216 ..... 26 25 24 23 22 21 20

CS5460A

DS284PP2 39

5.5 Pulse-Rate Register Address: 6

Default** = 32000.00Hz

The Pulse-Rate Register determines the frequency of the train of pulses output on the EOUT pin. Each EOUT pulse represents a predetermined magnitude of energy. The register’s smallest valid value is 2 -4 but can be in 2-5 increments.

5.6 I,V,P,E Signed Output Register Results Address: 7 - 10

The Signed Registers contain the last value of the measured results of I, V, P, and E. The results are in the range of -1.0 ≤ I, V, P, E < 1.0. The value is represented in two's complement notation, with the binary point place to the right of the MSB (which is the sign bit). I, V, P, and E are output results registers which contain signed values. Note that the I, V, and P registers are updated every conversion cycle, while the E register is only updated after each computation cycle. The numeric format of this register is two’s complement notation.

5.7 IRMS, VRMS Unsigned Output Register Results Address: 11,12

The Unsigned Registers contain the last value of the calculated results of IRMS and VRMS. The results are in the range of 0.0 ≤ IRMS,VRMS < 1.0. The value is represented in binary notation, with the binary point place to the left of the MSB. IRMS and VRMS are output result registers which contain unsigned values.

5.8 Timebase Calibration RegisterAddress: 13

Default** = 1.000

The Timebase Register is initialized to 1.0 on reset, allowing the device to function and perform computations. The register is user loaded with the clock frequency error to compensate for a gain error caused by the crys-tal/oscillator tolerance. The value is in the range 0.0 ≤ TBC < 2.0.

MSB LSB

218 217 216 215 214 213 212 211 ..... 21 20 2-1 2-2 2-3 2-4 2-5

MSB LSB

-(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24

MSB LSB

20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

CS5460A

40 DS284PP2

5.9 Power Offset RegisterAddress: 14

Default** = 0.000

This offset value is added to each power value that is computed for each voltage/current sample pair before being accumulated in the energy register. The numeric format of this register is two’s complement notation. This register can be used to offset contributions to the energy result that are caused by undesirable sources of energy that are inherent in the system.

5.10 AC Current Offset Register and AC Voltage Offset RegisterAddress: 16 (AC Current Offset Register)

17 (AC Voltage Offset Register)

Default** = 0.000

The AC Offset Registers are initialized to zero on reset, allowing the device to function and perform measure-ments. First, the ground-level input should be applied to the inputs. Then the AC Offset Calibration Command is should be sent to the CS5460A. After ~(6N + 30) A/D conversion cycles (where N is the value of the Cy-cle-Count Register), the gain register(s) is loaded with the square of the system AC offset value. DRDY will be asserted at the end of the calibration. The register may be read and stored so the register may be restored with the desired system offset compensation. Note that this register value represents the square of the AC cur-rent/voltage offset.

5.11 Status Register and Mask RegisterAddress: 15 (Status Register)

26 (Mask Register)

Default** = 0x000000 (Status Register)

0x000000 (Mask Register)

The Status Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user can simply write back to the Status Register to clear the bits that have been seen, without concern of clearing any newly set bits. Even if a status bit is masked to prevent the interrupt, the status bit will still be set in the Status Register so the user can poll the status.

The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the mask register will allow the corresponding bit in the Status Register to activate the INT pin when the status bit becomes active.

MSB LSB

-(20) 2-1 2-2 2-3 2-4 2-5 2-6 2-7 ..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

MSB LSB

2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 ..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24

23 22 21 20 19 18 17 16DRDY EOUT EDIR CRDY MATH Res IOR VOR

15 14 13 12 11 10 9 8PWOR IROR VROR EOR EOOR Res ID3 ID2

7 6 5 4 3 2 1 0ID1 ID0 WDT VOD IOD LSD 0 IC

CS5460A

DS284PP2 41

IC Invalid Command. Normally logic 1. Set to logic 0 when the part is given an invalid command. Can be deactivated only by sending a port initialization sequence to the serial port. When writing to Status Register this bit is ignored.

LSD Low Supply Detect. Set when the voltage at the PFMON pin falls below the low-voltage thresh-old (with respect to VA- pin). For a given part, this threshold can anywhere between 2.3 V to 2.7 V.

IOD Modulator oscillation detect on the current channel. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the current channel’s Differential Input Voltage Range.

VOD Modulator oscillation detect on the voltage channel. Set when the modulator oscillates due to an input above Full Scale. Note that the level at which the modulator oscillates is significantly higher than the current channel’s Differential Input Voltage Range.

Note: This IOD and VOD bits may be ‘falsely’ triggered by very brief voltage spikes from the power line. This event should not be confused with a DC overload situation at the inputs, when the IOD and VOD bits will re-assert themselves even after being cleared, multiple times.

WDT Watch-Dog Timer. Set when there has been no reading of the Energy register for more than 5 seconds. (MCLK = 4.096 MHz, K = 1) To clear this bit, first read the Energy register, then write to the Status Register with this bit set to logic '1'. When MCLK / K is not 4.096 MHz, the time duration is 5 * [4.096 MHz / (MCLK / K)] seconds.

ID3:0 Revision/Version Identification.

EOOR /EOUT Energy Summation Register went out of range. Note that the /EOUT Energy Summing Register is different than the Energy Register available through the serial port. This register cannot be read by the user. Assertion of the this bit can be caused by having an output rate that is too small for the power being measured. The problem can be corrected by specifying a higher frequency in the Pulse-Rate Register.

EOR Energy Out of Range. Set when the calibrated energy value is too large or too small to fit in the Energy Register, which can be read via the serial port.

VROR RMS Voltage Out of Range. Set when the calibrated RMS voltage value is too large to fit in the RMS-Voltage Register.

IROR RMS Current Out of Range. Set when the calibrated RMS current value is too large to fit in the RMS-Current Register.

PWOR Power Calculation Out of Range. Set when the magnitude of the calculated power is too large to fit in the Instantaneous Power Register.

VOR Voltage Out of Range.

IOR Current Out of Range. Set when the magnitude of the calibrated current value is too large or too small to fit in the Instantaneous Current Register.

MATH General computation Indicates that a divide operation overflowed. This can happen normally in the course of computation. If this bit is asserted but no other bits are asserted, then there is no error, and this bit should be ignored.

CS5460A

42 DS284PP2

CRDY Conversion Ready. Indicates a new conversion is ready. This will occur at the output word rate, which is usually 4 kHz.

EDIR Set whenever the EOUT bit asserted (see below) as long as the energy result is negative.

EOUT Indicates that the energy limit has been reached for the /EOUT Energy Summation Register, and so this register will be cleared, and one pulse will be generated on the /EOUT pin (if en-abled). The energy flow may indicate negative energy or positive energy. This must be deter-mined by looking at the EDIR bit (above). This EOUT bit is cleared automatically when the energy rate drops below the level that produces a 4 KHz EOUT pin rate. The bit can also be cleared by writing to the Status Register. This status bit is set with a maximum frequency of 4 KHz (when MCLK/K is 4.096 MHz). When MCLK/K is not equal to 4.096 MHz, the user should scale the pulse-rate that one would expect to get with MCLK/K = 4.096 MHz by a factor of 4.096 MHz / (MCLK/K) to get the actual pulse-rate.

DRDY Data Ready. When running in single or continuous conversion mode, this bit will indicate the end of computation cycles. When running calibrations, this bit indicates that the calibration se-quence has completed, and the results have been stored in the offset or gain registers.

5.12 Control Register Address: 28

Default** = 0x000000

STOP 1 = used to terminate the new EEBOOT sequence.

Res Reserved. These bits must be set to zero.

MECH 1 = widens EOUT and EDIR pulses for mechanical counters.

INTL 1 = converts the /INT output to open drain configuration.

SYNC 1 = forces internal A/D converter clock to synchronize to the initiation of a conversion command.

NOCPU 1 = converts the CPUCLK output to a one-bit output port. Reduces power consumption.

NOOSC 1 = saves power by disabling the crystal oscillator for external drive.

STEP 1 = enables stepper-motor signals on the EOUT/EDIR pins.

23 22 21 20 19 18 17 16Res Res Res Res Res Res Res Res

15 14 13 12 11 10 9 8Res Res Res Res Res Res Res STOP

7 6 5 4 3 2 1 0Res MECH Res INTL SYNC NOCPU NOOSC STEP

CS5460A

DS284PP2 43

6. PIN DESCRIPTION

1

2

3

4

5

6

7

8 17

18

19

20

21

22

23

24

9

10

11

12 13

14

15

16

Crystal Out XOUT

CPU Clock Output CPUCLK

Positive Digital Supply VD+

Digital Ground DGND

Serial Clock Input SCLK

Serial Data Output SDO

Chip Select CS

Mode Select MODE

Differential Voltage Input VIN+

Differential Voltage Input VIN-

Voltage Reference Output VREFOUT

Voltage Reference Input VREFIN

XIN Crystal In

SDI Serial Data Input

EDIR Energy Direction Indicator

EOUT Energy Output

INT Interrupt

RESET Reset

NC No Connect

PFMON Power Fail Monitor

IIN+ Differential Current Input

IIN- Differential Current Input

VA+ Positive Analog Supply

VA- Analog Ground

Clock Generator

Crystal OutCrystal In

1,24 XOUT, XIN - A gate inside the chip is connected to these pins and can be used with a crystal to provide the system clock for the device. Alternatively, an external (CMOS compatible clock) can be supplied into XIN pin to provide the system clock for the device.

CPU Clock Output 2 CPUCLK - Output of on-chip oscillator which can drive one standard CMOS load.

Control Pins and Serial Data I/O

Serial Clock Input 5 SCLK - A clock signal on this pin determines the input and output rate of the data for the SDI and SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low.

Serial Data Output 6 SDO - SDO is the output pin of the serial data port. Its output will be in a high impedance state when CS is high.

Chip Select 7 CS - When low, the port will recognize SCLK. An active high on this pin forces the SDO pin to a high impedance state. CS should be changed when SCLK is low.

Mode Select 8 MODE - When at logic high, the CS5460A can perform the auto-boot sequence with the aid of an external serial EEPROM to receive commands and settings. When at logic low, the CS5460A assumes normal command-mode operation. This pin is pulled down to logic low if left unconnected.

Interrupt 20 INT - When INT goes low it signals that an enabled event has occurred. INT is cleared (logic 1) by writing the appropriate command to the CS5460A.

Energy Output 21 EOUT - The energy output pin output a fixed-width pulse rate output with a rate (pro-grammable) proportional to energy.

Energy Direction Indicator

22EDIR - The energy direction indicator indicates if the measured energy is negative.

Serial Data Input 23 SDI - the input pin of the serial data port. Data will be input at a rate determined by SCLK.

Measurement and Reference Input

DifferentialVoltage Inputs

9,10 VIN+, VIN- - Differential analog input pins for voltage channel.

CS5460A

44 DS284PP2

Voltage Reference Output

11 VREFOUT - The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 2.5 V and is reference to the VA- pin on the converter.

VoltageReference Input

12 VREFIN - The voltage input to this pin establishes the voltage reference for the on-chip modulator.

Differential Current Inputs

15,16 IIN+, IIN- - Differential analog input pins for current channel.

Power Supply Connections

Positive Digital Supply

3 VD+ - The positive digital supply is nominally +5 V ±10% relative to DGND.

Digital Ground 4 DGND - The digital ground is at the same level as VA-.

Negative Analog Supply

13 VA- - The negative analog supply pin must be at the lowest potential.

Positive Analog Supply

14 VA+ - The positive analog supply is nominally +5 V ±10% relative to VA-.

Power Fail Monitor 17 PFMON - The power fail Monitor pin monitors the analog supply. Typical threshold level is 2.5 V with respect to the VA- pin, with +/-50 mV of hysteresis. If PFMON voltage threshold is tripped, the LSD (low-supply detect) bit is set in the Status Register.

RESET 19 Reset - When reset is taken low, all internal registers are set to their default states.

Other

No Connection 18 NC - No connection. Pin should be left floating.

CS5460A

DS284PP2 45

7. PACKAGE DIMENSIONS

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side.

2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition.

3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.

INCHES MILLIMETERS NOTEDIM MIN NOM MAX MIN NOM MAX

A -- -- 0.084 -- -- 2.13A1 0.002 0.006 0.010 0.05 0.13 0.25A2 0.064 0.068 0.074 1.62 1.73 1.88b 0.009 -- 0.015 0.22 -- 0.38 2,3D 0.311 0.323 0.335 7.90 8.20 8.50 1E 0.291 0.307 0.323 7.40 7.80 8.20

E1 0.197 0.209 0.220 5.00 5.30 5.60 1e 0.022 0.026 0.030 0.55 0.65 0.75L 0.025 0.03 0.041 0.63 0.75 1.03∝ 0° 4° 8° 0° 4° 8°

JEDEC #: MO-150

Controlling Dimension is Millimeters.

24L SSOP PACKAGE DRAWING

E

N

1 2 3

e b2 A1

A2 A

D

SEATINGPLANE

E11

L

SIDE VIEW

END VIEW

TOP VIEW

∝

CS5460A

46 DS284PP2

INCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAX

A 0.093 0.098 0.104 2.35 2.50 2.65A1 0.004 0.008 0.012 0.10 0.20 0.30b 0.013 0.017 0.020 0.33 0.42 0.51C 0.009 0.011 0.013 0.23 0.28 0.32D 0.598 0.606 0.614 15.20 15.39 15.60E 0.291 0.295 0.299 7.40 7.50 7.60e 0.040 0.050 0.060 1.02 1.27 1.52H 0.394 0.407 0.419 10.00 10.34 10.65L 0.016 0.026 0.050 0.40 0.65 1.27∝ 0° 4° 8° 0° 4° 8°

JEDEC #: MS-013

Controlling Dimension is Millimeters

24L SOIC (300 MIL BODY) PACKAGE DRAWING

D

HE

b

A1

A

c

L

∝

SEATINGPLANE

1

e

• Notes •

Documents

Cs5460A No Proteguido