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CS61C L29 CPU Design : Pipelining to Improve Performance II (1) Garcia, Fall 2006 © UCB
Running away with it Our #8 football team had a
great effort and bit of the Bruins’ help to push them past UCLA 38-24. They outgained us,
but missed several field goals, key catches, & had a few turnovers. Plus we have DeSean,
Marshawn and Nate. 8-straight, baby! AU next
Lecturer SOE Dan Garcia
www.cs.berkeley.edu/~ddgarcia
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures
Lecture 29 – CPU Design : Pipelining to Improve Performance
2006-11-06
calbears.cstv.com/sports/m-footbl/recaps/110406aab.html
CS61C L29 CPU Design : Pipelining to Improve Performance II (2) Garcia, Fall 2006 © UCB
Review: Processor Pipelining (1/2)
• “Pipeline registers” are added to the datapath/controller to neatly divide the single cycle processor into “pipeline stages”.
•Optimal Pipeline• Each stage is executing part of an instruction
each clock cycle.
• One inst. finishes during each clock cycle.
• On average, execute far more quickly.
•What makes this work well?• Similarities between instructions allow us to use
same stages for all instructions (generally).
• Each stage takes about the same amount of time as all others: little wasted time.
CS61C L29 CPU Design : Pipelining to Improve Performance II (3) Garcia, Fall 2006 © UCB
Review: Pipeline (2/2)• Pipelining is a BIG IDEA
• widely used concept
•What makes it less than perfect?
• Structural hazards: Conflicts for resources. Suppose we had only one cache? Need more HW resources
• Control hazards: Branch instructions effect which instructions come next. Delayed branch
• Data hazards: Data flow between instructions.
CS61C L29 CPU Design : Pipelining to Improve Performance II (4) Garcia, Fall 2006 © UCB
Control Hazard: Branching (1/8)
Where do we do the compare for the branch?
I$
beq
Instr 1
Instr 2
Instr 3
Instr 4A
LU I$ Reg D$ Reg
AL
U I$ Reg D$ Reg
AL
U I$ Reg D$ RegA
LUReg D$ Reg
AL
U I$ Reg D$ Reg
Instr.
Order
Time (clock cycles)
CS61C L29 CPU Design : Pipelining to Improve Performance II (5) Garcia, Fall 2006 © UCB
Control Hazard: Branching (2/8)•We had put branch decision-making hardware in ALU stage
• therefore two more instructions after the branch will always be fetched, whether or not the branch is taken
•Desired functionality of a branch• if we do not take the branch, don’t waste any time and continue executing normally
• if we take the branch, don’t execute any instructions after the branch, just go to the desired label
CS61C L29 CPU Design : Pipelining to Improve Performance II (6) Garcia, Fall 2006 © UCB
Control Hazard: Branching (3/8)• Initial Solution: Stall until decision is made
• insert “no-op” instructions (those that accomplish nothing, just take time) or hold up the fetch of the next instruction (for 2 cycles).
• Drawback: branches take 3 clock cycles each (assuming comparator is put in ALU stage)
CS61C L29 CPU Design : Pipelining to Improve Performance II (7) Garcia, Fall 2006 © UCB
Control Hazard: Branching (4/8)•Optimization #1:
• insert special branch comparator in Stage 2
• as soon as instruction is decoded (Opcode identifies it as a branch), immediately make a decision and set the new value of the PC
• Benefit: since branch is complete in Stage 2, only one unnecessary instruction is fetched, so only one no-op is needed
• Side Note: This means that branches are idle in Stages 3, 4 and 5.
CS61C L29 CPU Design : Pipelining to Improve Performance II (8) Garcia, Fall 2006 © UCB
Control Hazard: Branching (5/8)
Branch comparator moved to Decode stage.
I$
beq
Instr 1
Instr 2
Instr 3
Instr 4A
LU I$ Reg D$ Reg
AL
U I$ Reg D$ Reg
AL
U I$ Reg D$ RegA
LUReg D$ Reg
AL
U I$ Reg D$ Reg
Instr.
Order
Time (clock cycles)
CS61C L29 CPU Design : Pipelining to Improve Performance II (9) Garcia, Fall 2006 © UCB
• User inserting no-op instruction
Control Hazard: Branching (6a/8)
add
beq
nop
AL
U I$ Reg D$ Reg
AL
U I$ Reg D$ RegA
LUReg D$ Reg I$
Instr.
Order
Time (clock cycles)
bubble
• Impact: 2 clock cycles per branch instruction slow
lw
bubble
bubble
bubble
bubble
CS61C L29 CPU Design : Pipelining to Improve Performance II (10) Garcia, Fall 2006 © UCB
• Controller inserting a single bubble
Control Hazard: Branching (6b/8)
add
beq
lw
AL
U I$ Reg D$ Reg
AL
U I$ Reg D$ RegA
LUReg D$ Reg I$
Instr.
Order
Time (clock cycles)
bubble
• Impact: 2 clock cycles per branch instruction slow
CS61C L29 CPU Design : Pipelining to Improve Performance II (11) Garcia, Fall 2006 © UCB
Control Hazard: Branching (7/8)•Optimization #2: Redefine branches
• Old definition: if we take the branch, none of the instructions after the branch get executed by accident
• New definition: whether or not we take the branch, the single instruction immediately following the branch gets executed (called the branch-delay slot)
•The term “Delayed Branch” meanswe always execute inst after branch
•This optimization is used on the MIPS
CS61C L29 CPU Design : Pipelining to Improve Performance II (12) Garcia, Fall 2006 © UCB
Control Hazard: Branching (8/8)•Notes on Branch-Delay Slot
• Worst-Case Scenario: can always put a no-op in the branch-delay slot
• Better Case: can find an instruction preceding the branch which can be placed in the branch-delay slot without affecting flow of the program
re-ordering instructions is a common method of speeding up programs
compiler must be very smart in order to find instructions to do this
usually can find such an instruction at least 50% of the time
Jumps also have a delay slot…
CS61C L29 CPU Design : Pipelining to Improve Performance II (13) Garcia, Fall 2006 © UCB
Example: Nondelayed vs. Delayed Branch
add $1 ,$2,$3
sub $4, $5,$6
beq $1, $4, Exit
or $8, $9 ,$10
xor $10, $1,$11
Nondelayed Branch
add $1 ,$2,$3
sub $4, $5,$6
beq $1, $4, Exit
or $8, $9 ,$10
xor $10, $1,$11
Delayed Branch
Exit: Exit:
CS61C L29 CPU Design : Pipelining to Improve Performance II (14) Garcia, Fall 2006 © UCB
Data Hazards (1/2)
add $t0, $t1, $t2
sub $t4, $t0 ,$t3
and $t5, $t0 ,$t6
or $t7, $t0 ,$t8
xor $t9, $t0 ,$t10
•Consider the following sequence of instructions
CS61C L29 CPU Design : Pipelining to Improve Performance II (15) Garcia, Fall 2006 © UCB
Data-flow backward in time are hazards
Data Hazards (2/2)
sub $t4,$t0,$t3
AL
UI$ Reg D$ Reg
and $t5,$t0,$t6
AL
UI$ Reg D$ Reg
or $t7,$t0,$t8 I$
AL
UReg D$ Reg
xor $t9,$t0,$t10
AL
UI$ Reg D$ Reg
add $t0,$t1,$t2IF ID/RF EX MEM WBA
LUI$ Reg D$ Reg
Instr.
Order
Time (clock cycles)
CS61C L29 CPU Design : Pipelining to Improve Performance II (16) Garcia, Fall 2006 © UCB
• Forward result from one stage to another
Data Hazard Solution: Forwarding
sub $t4,$t0,$t3
AL
UI$ Reg D$ Reg
and $t5,$t0,$t6A
LUI$ Reg D$ Reg
or $t7,$t0,$t8 I$
AL
UReg D$ Reg
xor $t9,$t0,$t10
AL
UI$ Reg D$ Reg
add $t0,$t1,$t2IF ID/RF EX MEM WBA
LUI$ Reg D$ Reg
“or” hazard solved by register hardware
CS61C L29 CPU Design : Pipelining to Improve Performance II (17) Garcia, Fall 2006 © UCB
• Dataflow backwards in time are hazards
Data Hazard: Loads (1/4)
sub $t3,$t0,$t2A
LUI$ Reg D$ Reg
lw $t0,0($t1)IF ID/RF EX MEM WBA
LUI$ Reg D$ Reg
• Can’t solve all cases with forwarding• Must stall instruction dependent on load, then forward (more hardware)
CS61C L29 CPU Design : Pipelining to Improve Performance II (18) Garcia, Fall 2006 © UCB
• Hardware stalls pipeline• Called “interlock”
Data Hazard: Loads (2/4)
sub $t3,$t0,$t2A
LUI$ Reg D$ Reg
bubble
and $t5,$t0,$t4
AL
UI$ Reg D$ Regbubble
or $t7,$t0,$t6 I$
AL
UReg D$bubble
lw $t0, 0($t1)IF ID/RF EX MEM WBA
LUI$ Reg D$ Reg
CS61C L29 CPU Design : Pipelining to Improve Performance II (19) Garcia, Fall 2006 © UCB
Data Hazard: Loads (3/4)
• Instruction slot after a load is called “load delay slot”
• If that instruction uses the result of the load, then the hardware interlock will stall it for one cycle.
• If the compiler puts an unrelated instruction in that slot, then no stall
•Letting the hardware stall the instruction in the delay slot is equivalent to putting a nop in the slot (except the latter uses more code space)
CS61C L29 CPU Design : Pipelining to Improve Performance II (20) Garcia, Fall 2006 © UCB
Data Hazard: Loads (4/4)•Stall is equivalent to nop
sub $t3,$t0,$t2
and $t5,$t0,$t4
or $t7,$t0,$t6 I$
AL
UReg D$
lw $t0, 0($t1)
AL
UI$ Reg D$ Reg
bubble
bubble
bubble
bubble
bubble
AL
UI$ Reg D$ Reg
AL
UI$ Reg D$ Reg
nop
CS61C L29 CPU Design : Pipelining to Improve Performance II (21) Garcia, Fall 2006 © UCB
Historical Trivia
•First MIPS design did not interlock and stall on load-use data hazard
•Real reason for name behind MIPS: Microprocessor without Interlocked Pipeline Stages
• Word Play on acronym for Millions of Instructions Per Second, also called MIPS
CS61C L29 CPU Design : Pipelining to Improve Performance II (22) Garcia, Fall 2006 © UCB
Administrivia
•Project 3 out today; start soon!
•Advanced Pipelining!• “Out-of-order” Execution
• “Superscalar” Execution
CS61C L29 CPU Design : Pipelining to Improve Performance II (23) Garcia, Fall 2006 © UCB
Pipeline Hazard: Matching socks in later load
A depends on D; stall since folder tied up; Note this is much different from processor cases so far. We have not had a earlier instruction depend on a later one.
Task
Order
B
C
D
A
E
F
bubble
12 2 AM6 PM 7 8 9 10 11 1
Time303030 3030 3030
CS61C L29 CPU Design : Pipelining to Improve Performance II (24) Garcia, Fall 2006 © UCB
Out-of-Order Laundry: Don’t Wait
A depends on D; rest continue; need more resources to allow out-of-order
Task
Order
12 2 AM6 PM 7 8 9 10 11 1
Time
B
C
D
A
303030 3030 3030
E
F
bubble
CS61C L29 CPU Design : Pipelining to Improve Performance II (25) Garcia, Fall 2006 © UCB
Superscalar Laundry: Parallel per stage
More resources, HW to match mix of parallel tasks?
Task
Order
12 2 AM6 PM 7 8 9 10 11 1
Time
B
C
D
A
E
F
(light clothing) (dark clothing) (very dirty clothing)
(light clothing) (dark clothing) (very dirty clothing)
303030 3030
CS61C L29 CPU Design : Pipelining to Improve Performance II (26) Garcia, Fall 2006 © UCB
Superscalar Laundry: Mismatch Mix
Task mix underutilizes extra resources
Task
Order
12 2 AM6 PM 7 8 9 10 11 1
Time303030 3030 3030
(light clothing)
(light clothing) (dark clothing)
(light clothing)
A
B
D
C
CS61C L29 CPU Design : Pipelining to Improve Performance II (27) Garcia, Fall 2006 © UCB
Peer Instruction (1/2)
Assume 1 instr/clock, delayed branch, 5 stage pipeline, forwarding, interlock on unresolved load hazards (after 103 loops, so pipeline full)Loop: lw $t0, 0($s1)
addu $t0, $t0, $s2sw $t0, 0($s1)addiu $s1, $s1, -4bne $s1, $zero, Loopnop
•How many pipeline stages (clock cycles) per loop iteration to execute this code?
12345678910
CS61C L29 CPU Design : Pipelining to Improve Performance II (28) Garcia, Fall 2006 © UCB
Peer Instruction Answer (1/2)•Assume 1 instr/clock, delayed branch, 5
stage pipeline, forwarding, interlock on unresolved load hazards. 103 iterations, so pipeline full.
Loop: lw $t0, 0($s1)addu $t0, $t0, $s2sw $t0, 0($s1)addiu $s1, $s1, -4bne $s1, $zero, Loopnop
•How many pipeline stages (clock cycles) per loop iteration to execute this code?
1.2. (data hazard so stall)
3.4.5.6.
(delayed branch so exec. nop)7.
1 2 3 4 5 6 7 8 9 10
CS61C L29 CPU Design : Pipelining to Improve Performance II (29) Garcia, Fall 2006 © UCB
Peer Instruction (2/2)
Assume 1 instr/clock, delayed branch, 5 stage pipeline, forwarding, interlock on unresolved load hazards (after 103 loops, so pipeline full). Rewrite this code to reduce pipeline stages (clock cycles) per loop to as few as possible. Loop: lw $t0, 0($s1)
addu $t0, $t0, $s2sw $t0, 0($s1)addiu $s1, $s1, -4bne $s1, $zero, Loopnop
•How many pipeline stages (clock cycles) per loop iteration to execute this code?
12345678910
CS61C L29 CPU Design : Pipelining to Improve Performance II (30) Garcia, Fall 2006 © UCB
Peer Instruction (2/2) How long to execute?
•How many pipeline stages (clock cycles) per loop iteration to execute your revised code? (assume pipeline is full)
•Rewrite this code to reduce clock cycles per loop to as few as possible:
Loop: lw $t0, 0($s1)addiu $s1, $s1, -4 addu $t0, $t0, $s2bne $s1, $zero, Loopsw $t0, +4($s1)
(no hazard since extra cycle)
1.
3.4.5.
2.
(modified sw to put past addiu)
1 2 3 4 5 6 7 8 9 10
CS61C L29 CPU Design : Pipelining to Improve Performance II (31) Garcia, Fall 2006 © UCB
“And in Conclusion..”
•Pipeline challenge is hazards• Forwarding helps w/many data hazards
• Delayed branch helps with control hazard in 5 stage pipeline
• Load delay slot / interlock necessary
•More aggressive performance: • Superscalar
• Out-of-order execution