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Lecture 4: Basic Pipelining 4-1/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
CS650Computer Architecture
Lecture 4Basic Pipelining
Andrew SohnComputer Science Department
New Jersey Institute of Technology
Lecture 4: Basic Pipelining 4-2/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
ALU
add
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 0
1
0
1
0
1
0
1
Very Simple 32-bit Computer
registers
16bits32bits
Lecture 4: Basic Pipelining 4-3/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
Simple Five-stage Pipelining1. F Fetch instruction, increment PC:
IR =Memory[PC];PC = PC + 4;
2. D Instruction decode, register fetch: A = Register[IR[25-21]];B = Register[IR[20-16]];Target = PC + (sign-extend (IR[15-0]) << 2)
3. E Execution, address computation, branch completion: ALU output = A op B;ALU output = A + sign-extend(IR[15-0]);if (A = B) PC = Target;
4. M Memory access, or R-type instruction completion: memory-data = Memory[ALU output];Register[IR[15-11]] = ALU output;
5. W Write-back: Register[IR[20-16]] = memory-data;
Lecture 4: Basic Pipelining 4-4/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
Sample 32-bit Instruction Format
6 bits 5 bits 5 bits 6 bits5 bits 5 bits
5-010-615-1120-1625-21
functop rs rt rd shamt
op rs rt offset
31-26
20-1625-2131-26
6 bits 5 bits 5 bits 16 bits
Register-based instructions
Branch/Memory instructions
Lecture 4: Basic Pipelining 4-5/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
Register-based InstructionsAdd R3, R2, R1
r3=r2+r1
1. Fetch instruction, increment PC2. Decode instruciton, read registers3. ALU operation4. Write result back to register
Lecture 4: Basic Pipelining 4-6/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
ALU
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 0
1
0
1
0
1
0
1
add r3, r2, r1
1: Fetch instruction, increment PC
PC
add
Lecture 4: Basic Pipelining 4-7/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
ALU
add
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 0
1
0
1
0
1
0
1
2: Decode instruction, read registers
add r3, r2, r1
Lecture 4: Basic Pipelining 4-8/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
add
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
0
1
0
1
0
1
0
1
3: ALU operation
ALUzero
add r3, r2, r1
Lecture 4: Basic Pipelining 4-9/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
ALU
add
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 0
1
0
1
0
1
0
1
4: Register write back
add r3, r2, r1
mux
mux
muxm
ux
Lecture 4: Basic Pipelining 4-10/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
Load/Store InstructionsLoad R3, Offset(R1)
1. Fetch instruction, increment PC2. Decode instruciton, read a register, 3. Compute memory address4. Read data from memory 5. Write back to a register
Lecture 4: Basic Pipelining 4-11/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
ALU
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 0
1
0
1
0
1
0
1
load r3, offset(r1)
1: Fetch instruction, increment PC
PC
add
Lecture 4: Basic Pipelining 4-12/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0 Offset
4
instructionmemory
ALUcontrol
ALU
add
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 0
1
0
1
0
1
0
1
2: Decode instruction, read a register
signextend
load r3, offset(r1)
16 bits in32 bits out
Lecture 4: Basic Pipelining 4-13/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
add
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
0
1
0
1
0
1
0
1
3: ALU operation for effective memory address computation
ALUzero
lw r3, offset(r1)
Lecture 4: Basic Pipelining 4-14/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
ALU
add
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 1
0
0
1
0
1
0
1
4: Memory read
lw r3, offset(r1)
Lecture 4: Basic Pipelining 4-15/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
ALU
add
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 0
1
0
1
0
1
0
1
5: Register write back
lw r3, offset(r1)
Lecture 4: Basic Pipelining 4-16/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
Branch InstructionsBeq R1, R2, Offset
1. Fetch instruction, increment PC2. Decode instruction, read two registers3. Branch target address computation
and condition testing4. Decide PC: stay or jump
Lecture 4: Basic Pipelining 4-17/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
ALU
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 0
1
0
1
0
1
0
1
beq r1, r2, offset
1: Fetch instruction, increment PC
PC
add
Lecture 4: Basic Pipelining 4-18/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0 Offset
4
instructionmemory
ALUcontrol
ALU
add
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 0
1
0
1
0
1
0
1
2: Decode instruction, read registers
beq r1, r2, offset
next address
Lecture 4: Basic Pipelining 4-19/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
0
1
0
1
0
1
0
1
3: Branch target address computation and condition testing
ALUzero
beq r1, r2, offset
add
r1-r2
1
11
Offset
next address
Lecture 4: Basic Pipelining 4-20/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
branch
regdst
memreadmemtoreg
aluopmemwrite
alusrcregwrite
31-26
25-21
20-16
15-11
15-0
4
instructionmemory
ALUcontrol
ALU
add
datamemory
read reg1
read reg2
write reg
write data
readaddress
inst
ruct
ion
PC
signextend
writedata
writeaddress
readdata
readaddress
5-0
cont
rol
read
dat
a1re
ad d
ata2
zero 0
1
0
1
0
1
4: Decide PC: stay or jump
beq r1, r2, offset
0
1add
next address
branch address
Lecture 4: Basic Pipelining 4-21/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
Pipelining
Consider the following assembly codeadd r1, r2, r3sub r4, r1, r5and r6, r1, r7or r8, r1, r9xor r10, r1, r11
Lecture 4: Basic Pipelining 4-22/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
bran
ch
regdst
memread
mem
tore
g
aluop
mem
writ
e
alusrc
regwrite
4
DataMemory
M
EX
WB
M
WBWB
0
1
writedata
writeaddress
readdata
readaddress
add
ALUzero
ALUcontrol
0
1
0
1
cont
rol
read reg1
read reg2
write reg
write data
data
2
Registers
data
1
signextend
add
0
1
InstructionMemory
readaddress
inst
ruct
ion
PC
Pipelining
F D E M W
add r1, r2, r3sub r4, r1, r5and r6, r1, r7or r8, r1, r9xor r10, r1, r11
Lecture 4: Basic Pipelining 4-23/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
alusrc
4
writedata
writeaddress
readdata
readaddress
add
ALUzero
ALUcontrol
0
1
read reg1
read reg2
write reg
write data
data
2
Registers
data
1
signextend
add
InstructionMemory
readaddress
inst
ruct
ion
PC
F D E M W
add r1, r2, r3
0
1
add r1, r2, r3sub r4, r1, r5and r6, r1, r7or r8, r1, r9xor r10, r1, r11
Clock 0
Lecture 4: Basic Pipelining 4-24/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
alusrc
4
writedata
writeaddress
readdata
readaddress
add
ALUzero
ALUcontrol
0
1
read reg1
read reg2
write reg
write data
data
2
Registers
data
1
signextend
add
InstructionMemory
readaddress
inst
ruct
ion
PC
F D E M W
add r1, r2, r3sub r4,r1,r5
0
1
add r1, r2, r3sub r4, r1, r5and r6, r1, r7or r8, r1, r9xor r10, r1, r11
Clock 1
Lecture 4: Basic Pipelining 4-25/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
alusrc
4
writedata
writeaddress
readdata
readaddress
add
ALUzero
ALUcontrol
0
1
read reg1
read reg2
write reg
write data
data
2
Registers
data
1
signextend
add
InstructionMemory
readaddress
inst
ruct
ion
PC
F D E M W
add r1, r2, r3sub r4,r1,r5and r6, r1, r7
0
1
add r1, r2, r3sub r4, r1, r5and r6, r1, r7or r8, r1, r9xor r10, r1, r11
Clock 2
Lecture 4: Basic Pipelining 4-26/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
alusrc
4
writedata
writeaddress
readdata
readaddress
add
ALUzero
ALUcontrol
0
1
read reg1
read reg2
write reg
write data
data
2
Registers
data
1
signextend
add
InstructionMemory
readaddress
inst
ruct
ion
PC
F D E M W
add r1, r2, r3sub r4,r1,r5and r6, r1, r7or r8, r1, r9
0
1
add r1, r2, r3sub r4, r1, r5and r6, r1, r7or r8, r1, r9xor r10, r1, r11
Clock 3
Lecture 4: Basic Pipelining 4-27/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
alusrc
4
writedata
writeaddress
readdata
readaddress
add
ALUzero
ALUcontrol
0
1
read reg1
read reg2
write reg
write data
data
2
Registers
data
1
signextend
add
InstructionMemory
readaddress
inst
ruct
ion
PC
F D E M W
addsub r4,r1,r5and r6, r1, r7or r8, r1, r9xor r10, r1, r11
0
1
add r1, r2, r3sub r4, r1, r5and r6, r1, r7or r8, r1, r9xor r10, r1, r11
Clock 4
Lecture 4: Basic Pipelining 4-28/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
Pipeline Hazards
Data (register) hazardsStructural hazardsControl (branch) hazards
Lecture 4: Basic Pipelining 4-29/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
ALUInstruct Reg Reg
ALUReg Reg
ALUReg Reg
ALUReg
ALUReg
Clock 1 2 3 4 5 6 7
add r1,r2,r3
sub r4,r1,r5
and r6,r1,r7
or r8,r1,r9
xor r10,r1,r11
MemDataMem
InstructMem
InstructMem
InstructMem
InstructMem
DataMem
DataMem
DataMem
Register Hazards
Lecture 4: Basic Pipelining 4-30/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
ALUInstruct Reg Reg
ALUReg Reg
ALUReg Reg
ALUReg
ALUReg
Clock 1 2 3 4 5 6 7
add r1,r2,r3
sub r4,r1,r5
and r6,r1,r7
or r8,r1,r9
xor r10,r1,r11
MemDataMem
InstructMem
InstructMem
InstructMem
InstructMem
DataMem
DataMem
DataMem
Forwarding
Lecture 4: Basic Pipelining 4-31/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
ALUInstruct Reg
Clock 1 2 3 4 5 6 7
add r1,r2,r3
store 78(r1),r4
MemDataMem Reg
ALUInstruct RegMemDataMem Reg
ALUInstruct RegMemDataMem Reg
ALUInstruct RegMemDataMem
load r4, 39(r1)
or r4, r5,r6
Store Forwarding
Lecture 4: Basic Pipelining 4-32/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
ALUInstruct Reg
Clock 1 2 3 4 5 6 7
add r1,r2,r3
store 78(r1),r4
MemDataMem Reg
ALUInstruct RegMemDataMem Reg
ALUInstruct RegMemDataMem Reg
ALUInstruct RegMemDataMem
load r4, 39(r1)
Store Forwarding
Lecture 4: Basic Pipelining 4-33/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
ALUInstruct Reg
Clock 1 2 3 4 5 6 7
MemDataMem Reg
ALUInstruct RegMemDataMem Reg
ALUInstruct RegMemDataMem Reg
ALUInstruct RegMemDataMem
sub r4,r1,r5
load r1,0(r2)
and r6,r1,r7
or r8,r1,r9
Load Forwarding
Lecture 4: Basic Pipelining 4-34/34 9/27/3004 A. Sohn
NJIT Computer Science Dept CS650 Computer Architecture
ALUInstruct Reg
Clock 1 2 3 4 5 6 7
MemDataMem Reg
ALUInstruct RegMemDataMem Reg
ALUInstruct RegMemDataMem
ALUInstruct RegMem
sub r4,r1,r5
load r1,23(r2)
and r6,r1,r7
or r8,r1,r9
Bub
ble
Load Forwarding
