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Chapter 6
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Principles of Computer Architecture
ALU & MICROARHITECTURE DESIGN
Construction 1 bit ALU
Design an ALU logic circuit with the following functions:-
ALU1Bit
F 1F 0
YA
B
F1F0 Function(Y)0 0 AND(A,B)0 1 OR(A,B)1 0 NOR(A,B)1 1 XOR(A,B)
Boolean Expression & Circuit Design )BA(0F.1F)BA.(0F.1F)BA.(0F.1F)AB.(0F.1FY
F10V
F00V
B5V
A5V
Y
Using multiplexer
F15V
F00VB
5VA5V
Y
0
1
2
3
4:1M ux
Using MUX 74153 B5V
A5V
F00V
F10V
Y
74LS153I3aI2aI1aI0aS1S0I3bI2bI1bI0b
Ea
Eb
Ya
Yb
Expanding the ALUALU1Bit
Y1A 1
B 1
ALU1Bit
Y2A 2
B 2
ALU1Bit
Y3A 3
B 3
ALU1Bit
Y4A 4
B 4
F1F0
AND(A,B) Operation
A= 0010 (2) B= 0011 (3) Output Y = 0010 (2)
OR(A,B) Operation
A= 0010 (2) B= 0011 (3) Output Y = 0011 (3)
NOR(A,B) Operation
A= 0010 (2) B= 0011 (3) Output Y = 1100 (C)
XOR(A,B) Operation
A= 0010 (2) B= 0011 (3) Output Y = 0001 (1)
Designing A Microarchitecture Hardware component:-
ALU Register for Source Operand Register for Destination Operand Bus for Data Transfer Register to ALU(read) Bus for Data Transfer ALU to Register(write)
Designing A Microarchitecture Using ALU 74181
R0
R1
R2
R3
ENB
ENB
ENB
ENB
ENB
ENB
ENB
ENB
ABus BBus
ALU74181
S3S2S1S0
CBus
W riteEnable
C Decoder A Decoder BDecoder
ALU 74181
Refer to ALU74181.doc
Creating the Datapath
1234
1
4555
A1
A0
EQ0
Q1
Q2
Q3
1/2
U7B
1234
DISP2
1234
DISP1
1234
0
4555
A1
A0
EQ0
Q1
Q2
Q3
1/2
U7A
74LS1264C4A3C3A2C2A1C1A
4Y
3Y
2Y
1Y
74LS1264C4A3C3A2C2A1C1A
4Y
3Y
2Y
1Y
74LS1264C4A3C3A2C2A1C1A
4Y
3Y
2Y
1Y
74LS1264C4A3C3A2C2A1C1A
4Y
3Y
2Y
1Y
74LS1264C4A3C3A2C2A1C1A
4Y
3Y
2Y
1Y
74LS1264C4A3C3A2C2A1C1A
4Y
3Y
2Y
1Y
74LS1264C4A3C3A2C2A1C1A
4Y
3Y
2Y
1Y
74LS1264C4A3C3A2C2A1C1A
4Y
3Y
2Y
1Y
1234
1
Select
S1+V5V
4555
A1A0
E Q0Q1Q2Q3
1/2
D0D1D2D3
Q0Q1Q2Q3
CP
R3
1234
Output
D0D1D2D3
Q0Q1Q2Q3
CP
R2
1234
Output
1234
Output
D0D1D2D3
Q0Q1Q2Q3
CP
R1
D0D1D2D3
Q0Q1Q2Q3
CP
R01234
Output
1234
3
Input
R11k
3210
3210
3
2
1
0
3
2
1
0
3
2
1
0
0
1
2
3
BBus
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0ABus
3210
3210
3210
3210
3210
CBus BBusABusCBus
Creating the Datapath
R0 2 1. Input 2 to Cbus.2. Select 0 to choose R0.3. Press S1 to load to R0.
R1 31. Input 3 to Cbus.2. Select 1 to choose R1.3. Press S1 to load to R1.
Abus R0Select 0 to choose R0.
Bbus R1Select 1 to choose R1.
Creating the control sequence Cmux = to choose data from memory or ALU
0 input to Cbus 1 ALU output to Cbus
M, C & S3S2S1S0 = input for ALU 74181 Abus = register to Abus. Bbus = register to Bbus. Cbus = Cbus to Register.
Cmux M C S3S2S1S0 Abus Bbus Cbus1bit 1bit 1bit 4bit 2bit 2bit 2bit
Example 1
Determine the control sequence for
R2<-R0 plus R1, where R0=2 &R1=3
R1 plus 0R2R
31R
20R
Cmux M C S3S2S1S0 Abus Bbus Cbus0 x x xxxx xx xx 00 Load R00 x x xxxx xx xx 01 Load R11 0 0 1001 0 1 10 R2=R0 plus R1
Example 2 Determine the control sequence for
R3<-R0 plus R1plus R2, where R0=2 , R1= 3 & R2=4
R2 plus R3 R3
R1 plus 0R3R
42R
31R
20R
Cmux M C S3S2S1S0 Abus Bbus Cbus0 x x xxxx xx xx 00 Load R00 x x xxxx xx xx 01 Load R10 x x xxxx xx xx 10 Load R21 0 0 1001 00 01 11 R3=R0 plus R11 0 0 1001 11 10 11 R3=R3 plus R2
Example 3
Determine the control sequence for R2<-R1 minus R0 where R1=2 & R0=3
10R1R2R
2R1R2R
3R0R2R
0R0R
13R
21R
30R
or
2R1R2R
1 plus 0R2R
0R0R
21R
30R
