CSC Synchronization Procedure CSC Synchronization Procedure and Plansand Plans

UpdatedJuly 29, 2005

Jay Hauser / David Matlock / Yangheng ZhengUniversity of California, Los Angeles

Martin Von der MeyFermilab

What is done now

What should be done

04/19/23Slice Test at CERN2

Overview: Step I, without needing L1AOverview: Step I, without needing L1A

1. Make sure to disable interaction between different TMB/DMB setups in one peripheral crate. Allow only 1 chamber to trigger.

2. Adjust transmit/receive phases on the TMB for CFEB and ALCT within 25ns base period to get proper data transmission between boards.

3. Adjust ALCT delay to bring it into coincidence with CLCT

4. Preliminary check of LCT winner bits returned from MPC to TMB.

04/19/23Slice Test at CERN3

Overview: Step II: adjusting LCT-to-L1A Overview: Step II: adjusting LCT-to-L1A timing to 2.900 us required by CFEBstiming to 2.900 us required by CFEBs

5. Adjust LCT or L1A delays to get fixed 2.9us between LCT pretriggers and L1As as seen on the CFEBs.

04/19/23Slice Test at CERN4

Overview: Step III, with L1A but not DAQOverview: Step III, with L1A but not DAQ

6. Adjust ALCT-L1A coincidence to get ALCT to send ALCT readout data block TMB(passthrough) DMB

7. Adjust CLCT/TMB-L1A coincidence to get TMB to send its readout data block DMB

04/19/23Slice Test at CERN5

Overview: Step IV, getting data read out Overview: Step IV, getting data read out into DMB FIFOs with L1A gatinginto DMB FIFOs with L1A gating8. Adjust delayed CFEB, ALCT, CLCT

Data AVailable (DAV) bits to be in coincidence with L1A on the DMB to get data blocks read into DMB memory (FIFO chips).

9. Find the trigger data in the output record to verify.

04/19/23Slice Test at CERN6

Overview: Step V, with L1A and DAQ Overview: Step V, with L1A and DAQ readout workingreadout working

10. Equalize BX numbers between ALCT, TMB, and CFEBs within a chamber for DAQ readout.

11. For different chambers in the same peripheral crate use TMB output delay registers to equalize LCT times at the SP.

12. Equalize time of arrival of LCT signals from different crates at SP. Can do this either with TMB output delays or SP input delays.

13. Equalize BX numbers between chambers in DAQ readout.

04/19/23Slice Test at CERN7

Overview: Step VI, only done with LHC Overview: Step VI, only done with LHC OperationOperation

14.Adjust ALCT fine delay timing (in 2ns steps) to get events in ~1 bx at SP (for synchronous or semi-synchronous beam)

15.Overall offset to all BX numbers to make them agree with LHC-defined BX numbers.