CS/ECE 3330Computer Architecture

Chapter 1Power / Parallelism

CS/ECE 3330 – Fall 2009

Performance Analysis• It’s all relative

• Make sure the units cancel out!• What is a Hz?

• Amdahl’s Law• Benchmarking

Last Time

2

cycle Clock

Seconds

nInstructio

cycles Clock

Program

nsInstructioTime CPU

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Why Worry about Power Dissipation?

Environment

Thermal issues: affect cooling, packaging, reliability, timing

Batterylife

CS/ECE 3330 – Fall 2009

“The Power Wall”

Power Trends

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Must design with strict power envelopes• 130W servers, 65W desktop, 10-30W laptops, 1W mobile

Power Dissipation Has Peaked

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How Hot Does it Get?

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Cooling Issues

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http://www.youtube.com/watch?v=nYhEpHEPqcc

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Intel vs. Duracell

No Moore’s Law in batteries: 2-3%/year growth

Processor (MIPS)

Hard Disk (capacity)

Memory (capacity)

Battery (energy stored)

0 1 2 3 4 5 6

16x

14x

12x

10x

8x

6x

4x

2x1x

Improvement(compared to year 0)

Time (years)

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• Environment Protection Agency (EPA): computers consume 10% of commercial electricity consumption– Includes peripherals, possibly also manufacturing

• Data center growth was cited as a contribution to the 2000/2001 California Energy Crisis

• Equivalent power (with only 30% efficiency) for AC

• CFCs used for refrigeration• Lap burn• Fan noise

Environment

CS/ECE 3330 – Fall 2009

Power Matters at Scale…

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[J. Koomey (LBL), 2007]

Eric Schmidt, CEO of Google: "What matters most to the computer designers at Google is not speed, but power - low power, because data centers can consume as much electricity as a city."

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But Remember Amdahl’s Law

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Power vs. Energy

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Power vs. Energy

Power consumption in watts• Determines battery life in hours• Sets packaging limits

Energy efficiency in joules• Rate at which power is consumed over time• Energy = power * delay (joules = watts * seconds)• Lower energy number means less power to perform

a computation at same frequency

CS/ECE 3330 – Fall 2009

Another Fallacy: Low Power at Idle

X4 power benchmark• At 100% load: 295W• At 50% load: 246W (83%)• At 10% load: 180W (61%)

Google data center• Mostly operates at 10% – 50% load• At 100% load less than 1% of the time

Consider designing processors to make power proportional to load

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Capacitive Power Dissipation

Power ~ C V2 f

Capacitance:Function of wire length, transistor size

Supply Voltage:Has been dropping with successive fab generations

Frequency switched:Clock frequency + likelihood of change

CS/ECE 3330 – Fall 2009

Reducing Power

Suppose a new CPU has 75% of capacitive load of old CPU 25% voltage and 25% frequency reduction

0.320.75FVC

0.75F0.75)(V0.75C

P

P 4

old2

oldold

old2

oldold

old

new

The power wall We can’t reduce voltage further We can’t remove more heat

How else can we improve performance?

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CS/ECE 3330 – Fall 2009

Uniprocessor Performance

Constrained by power, instruction-level parallelism, memory latency

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CS/ECE 3330 – Fall 2009

Multiprocessors

Multicore microprocessors• More than one processor per chip

Multiprocessors and clusters – another course

Requires explicitly parallel programming• Compare with instruction-level parallelism

– Hardware executes multiple instructions at once– Hidden from the programmer• Hard to do

– Programming for performance– Load balancing– Optimizing communication and synchronization

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CS/ECE 3330 – Fall 2009

Multicore Architecture Examples

2 × quad-coreIntel Xeon e5345(Clovertown)

2 × quad-coreAMD Opteron X4 2356(Barcelona)

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CS/ECE 3330 – Fall 2009

Multicore Architecture Examples

2 × oct-coreIBM Cell QS20

2 × oct-coreSun UltraSPARCT2 5140 (Niagara 2)

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CS/ECE 3330 – Fall 2009

Power has become a limiting factor• Power vs energy• P = C * (V^2) * F

One solution: Multicore processors• Different scale than “old” parallel processors• More detail in Chapter 7

Key Points

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