Current and Voltage Sources

F. Maloberti : Design of CMOS Analog Integrated Circuits - “Current and Voltages Sources”

Design of CMOS AnalogIntegrated Circuits

Franco Maloberti

Current and Voltage Sources

F. Maloberti : Design of CMOS Analog Integrated Circuits - “Current and Voltages Sources” 24/

Current Mirrors

A current mirror gives a replica (if necessary, attenuated or amplified) of a bias or signal current.

• Simple current mirror

• Wilson current mirror

• Improved Wilson Current Mirror

• Cascode current mirror

• Modified cascode current mirror

• The high compliance current mirror

• The regulated cascode current mirror


Simple current mirror:

to simplify the calculation let

( ) ( )1DS2

Th1GS1

1ref V1VVL

W

2

kII λ+−

==

( ) ( )2DS2

Th2GS2

2out V1VVL

W

2

kII λ+−

==

2GS1GS1DS VVV ==

( )2DS

1

2refout V1

LWLW

II λ+

⋅=

2dsout

out rI

1r =

λ=


Factors affecting the mirror accuracy:

• Channel length modulation ( )• Threshold offset• Parasitic resistances• Imperfect geometrical matching and current mobility variation• Technological parameter mismatch

if:

It can be improved by increasing the output resistance.

21 L

W

L

W

=

( )( )1DS

2DS

ref

out

V1

V1

I

I

λ+λ+=

λ


The accuracy:

• The threshold mismatch is inversely proportional to the overdrive• The threshold of the MOS transistors placed in close proximity are

matches within within few mV. By contrast, for MOS transistors which are hundred of microns apart have threshold voltages that can differ by few tens of mV.

• The last term refers to a mismatch in VGS. It can be derived from resistive voltage drop. This is due to a parasitic resistance in series with the source.

• The metal resistance is in the order of 20 -50 mΩ/ with 10 squares it results in 0.2 - 0.5 Ω. If the current is 10 mA an equivalent offset of 2 -5 mV.

• and are minimized with closed and centroid common structures

• and depends on the lithographic proces

µδµ

ox

ox

C

Cδ

W

WδL

Lδ

2

ThGS

GS2

ThGS

Th22

ox

ox222

out

out

VV

V2

VV

V2

C

C

L

L

W

W

I

I

−

δ+

−

δ+

µδµ+

δ+

δ+

δ=

δ


• For a large W a goodstrategy is to have Wnot much larger thanL and to put equaltransistor in parallel

• The common centroidstructures achieves toreduce the parasitic capacitances.

δ+

δ+⋅⋅⋅=

δ 222

out

out

L

L

W

W

n

1

I

I

Iref IOut


Wilson Current Mirror

Increases the output resistance.

• RL must be large• There is a systematic error because VDS1 = VGS3 + VDS2

T2g1m3g2mx3s2g rvgvg/ivv −===

( ) ( )

+++=−== T1m

2m

3m3ds

2mout3ds3gs3mx

2m

xx rg1

g

g1r

g

1rrvgi

g

iv


ExampleSimulate with Spice the Wilson current mirror. Use the followingtransistors’ sizing (in µ): M1: 50/1 M3: 100/1. Find the difference between reference and generated current as a function of Iref in the range 0 - 200 µ A.

As expected, the output current is less than the reference current. Moreover, the difference is almost linear with the reference current and has a slope around 1%.


Improved Wilson Current Mirror

4GS2DS3GS1DS VVVV −+=

4GS3GS2DS1DS VVifVV ==


Small signal equivalent analysis:

• The output swing in the Wilson and improved Wilson schemes is limited to

4mL

4mL'T2g1m3g gR1

gRrVgV

+−=

( )4mL1ds'T g1Rrr +=

4mL

4mL'T1m

2m

3m3dsout gR1

gRrg

g

grr

+≅

3,sat1,satn,Th3,sat1GSmin,out VVVVVV ++=+=


It increases the output resistance without loop feedback. It has the same resistance of the cascode load.

• The output swing is limited to:

Cascode Current Mirror

( ) 2ds3m3dsoutx2ds3m3dsx2dsx rgrrirg1rirv ≅++=

satTh3sat3Gmin,out3GS4GS1GS3G V2VVVVVVVV +≈+=−+=


• The function of the transistor M4 is to shift the voltage VDS1 of the amount enough to bias te gate of M3 without bringing M2 out of saturation.• The use of M4 (matched with M3) allows to get VDS1 = VDS2 (this is paid with the output swing limitation).• The output swing is improved by the use of a level shift Vsat < ∆V < VTh.

Modified Cascode Current Mirror


The geometrical dimensions of M1, M6, M4, M5 determine, with Vov,4, ∆V.

5ox

55

4ox

445GS4GS WC

LI2

WC

LI2VVV

µ−

µ=−=∆


• All transistors operate in saturation

I = I1 = I2 = I3 = I4 (current scaling ispossible)

β1 = β2 = β3 = βVov1 = Vov2 = Vov3 = Vov

I4 = β4 (Vov4)2 ; I2 = β (Vov)2 ; I3 = β (Vov)2 ;Vov = ∆V

VDS2 = Vov

VGS3 = VTH + Vov

VGS4 = VTH + 2Vov Vov4 = 2Vov Therefore β = 4 β4

High - Compliance Current Mirror

4321 L

W4

L

W

L

W

L

W

=

=

=


• Current gain:

Systematic error due to VDS1 ≠ VDS2

Systematic error due to body effect on M3

• Output swing: Voutmin = 2VDSsat

• Output impedance: rout = rout4 gm2 rout2


M1 = M2 ; M3 = M4 Therefore Iout = Iref

To properly work, we must impose VDSsatM4 > VTh1

High - Compliance Current Mirror (II)


• Output impedance:Rout = (gm3rout3) rout2 (gm4rout4)

• Output swing:Voutmin = VGS4 + VDSsat3 ≈ VTh + 2Vsat

Regulated - Cascode Current Mirror(possible implementation)


Most of the analog blocksrequire a reference current.The circuits in the figureare supply dependent:

The accuracy of a generated current is:

• The global inaccuracy is around 32%• The dependence on the bias becomes critical when supply lines are affected by spur signals since the disturbance are transformed in current spurs.

Current Reference

( ) 2

L

L2

1GSDD

1GSDD2

fRe

fRe

R

R

VV

VV

I

δ+

−−δ=

δ

L

1GSDDfRe R

VVI

−=


• Self biased (or bootstrapped) current reference

Two operating points. It is necessary to use a start-up circuitry

( )2ThGS1

21 VVL

W

2

kII −

==

43 L

W

L

W

=

Th1

11GS12 V

W

L

k

I2VRIRI +

===


• Self biased low current reference generator

• Assume M3 = M4 ideal mirror I3 = I4• Assume VTh1 = VTh2

For k = 10, VR ≈ 60 mV if it is requiredI = 1µA R = 60 kΩ

1kW

Lk

W

L

W

L

W

L

2143

>

=

⋅

=

22ox

22

1ox

11 RIWC

LI2

WC

LI2 +µ

=µ


• VT-based reference generatorFor p-well technology, a verticle npn transistor with the collector tied to VDD is available (the complementary for n-well)

both VT and R have positive temperature coefficients

4321 W

L

W

L;

W

L

W

L

=

=

BA21 VV;III ===

SS

1T2BE

SS

1T1BE nAI

IlnVV;

AI

IlnVV ==

1

SS

SS

1T2BE1BE1 I

nAI

AI

IlnVVVRI =−=

( )nlnR

VI T=


• VBE multiplier

• Threshold voltage difference

• Band gap

Voltage References


• VBE-multiplier:

• VBE has a negative temperature coefficient

521 W

L

n

1

W

L

W

L

=

=

43 W

L

W

L

=

BA VV =

R

VI 1BE=

BEDDDDout nVVnRIVV −=−=


• Threshold voltage difference

M1 and M2 have different threshold (enhancement and depletion or enhancement and enhancement)


• Band gap voltage reference:

In order to have a reference voltage with zero temperature coefficient (in a defined temperature range) it is necessary to:

• VBE has a negative temperature coefficient (-2.2 mV/°C at 300 K)

• VT has a positive temperature coefficient (+0.086 mV/°C at 300 K)m ≈ 25.6

TBEref mVVV +=


For a p-well process:

231S

2S

2

1TBE IR

I

I

I

IlnVV ==∆

2Q

1Q

2S

1S

2

1

2

1

A

A

I

I;

LWLW

I

I =

=

=∆−−=−= BE3

21BE222ref V

R

RVIRVV

+−=1Q

2Q

2

1

3

2TBE A

A

LWLW

lnR

RVV

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Current and Voltage Sources