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Current Challenges of Semiconductor Technology in the Nanometric Generations. Exploratrory Workshop, Romanian R&D in Diaspora 17 September 2007, Bucharest, Romania. Dr. Andreas Wild Director, Technology Solutions Organization EMEA. Content. Scaling More Moore Lithography - PowerPoint PPT Presentation
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Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
Current Challenges of Semiconductor Technology in the Nanometric GenerationsExploratrory Workshop, Romanian R&D in Diaspora17 September 2007, Bucharest, Romania
Dr. Andreas WildDirector, Technology Solutions Organization EMEA
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. 2
Content
Scaling More Moore
• Lithography• Transistor scaling• Interconnect• Power
More than Moore Manufacturing Conclusions
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2005
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. 4
Scaling: smaller features + larger wafers = diminishing costAverage Transistor CostFeature Size (nm) Wafer Size (mm)
ITRS 2007 Edition: Affordable Cost per Function in 10 yearsPackaged, ½ pitch 16nm
- Transistor in MPU : $19n- DRAM bit : $1n
?
Scaling : Moore’s Law
?
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Semiconductors Entering the Nanoscale
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Functionality to the Consumer means…1. Longer battery life2. Streaming video3. Better phone graphics4. Longer Phone Ranges5. More memory for your digital camera6. Faster, smaller portable computers7. Laptops which won’t burn your lap8. … Anything you can imagine…
Portable, Longer Lasting Electronics Which Do More Things!
=
Product Functionality
Scaling Improves Transistors, Enables Better Products
Power Consumption
Battery Life
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2005
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Lithography
- 193nm still used• Immersion• Double exposure• Model-based OPC• Insolation
- EUV and eBeam still suffering of known problems
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MOS Transistor Scaling Challenges
On chip in 10 years: 275Gbit, 6BTransistors- Lateral scaling
* Lithography - Vertical scaling
* Leakage : high-k dielectric * Gate material
- Performance enhancement - Reliability - Yield
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Transport : SiGe, Parasitics : “Suitable Metal” NiSi Contacts on SiGe
SiGe
NiSiGe
TEM
18
Si ref.SiGe
10 12 14 16
10%
33%
50%67%
90%
M1-P+ Resistance (Ohm/via)
Cum
ulat
ive
Perc
enta
ge20% Improvement
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Transistor and Process Challenges
Reliability,Yield
Speed
30% higher performance40% improved power
40nm-thick Strained-Si
Buried Insulator
Substrate
Strained Si
Gate
S-SOI S-SOI
Leakage
ParasiticsReduced extrinsic resistance (ErSi, PtSi)Low K spacersmsec anneals
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Gate Leakage Control
Thicker gate oxide with a higher dielectric constant will reduce leakage while keeping the electrostatic properties : Cox = keoA/dox
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High k Candidates
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Gate MaterialsCV characteristics of ALD HfO2 and SiO2 core devices
Changing polysilicon doping from n+ to p+ shifts its Fermi level from the conduction band edge to the valence band edge :
- SiO2 CV curves shift by about 1V
Cap
acita
nce
(pF)
60
40
20
0
NMOSFET Devices (U31308)
0.E+00
2.E-11
4.E-11
6.E-11
-2 -1 0 1 2Gate Voltage (V)
Cap
actia
nce
(F)
20Å SiO2 (black)
45Å HfO2 (grey)
P+ Gate (Dashed)
N+ Gate (Solid)
1.0 V
0.13 V
Cap
acita
nce
(pF)
60
40
20
0
NMOSFET Devices (U31308)
0.E+00
2.E-11
4.E-11
6.E-11
-2 -1 0 1 2Gate Voltage (V)
Cap
actia
nce
(F)
20Å SiO2 (black)
45Å HfO2 (grey)
P+ Gate (Dashed)
N+ Gate (Solid)
1.0 V
0.13 V
PMOSFET Devices (U31308)
0.E+00
2.E-11
4.E-11
6.E-11
-2 -1 0 1 2
Gate Voltage (V)
Cap
actia
nce
(F) 20Å SiO2 (black)
45ÅHfO2(grey)
P+ Gate(Dashed)
N+ Gate (Solid)
0.99 V
0.24 V
Cap
acita
nce
(pF)
60
40
20
0
PMOSFET Devices (U31308)
0.E+00
2.E-11
4.E-11
6.E-11
-2 -1 0 1 2
Gate Voltage (V)
Cap
actia
nce
(F) 20Å SiO2 (black)
45ÅHfO2(grey)
P+ Gate(Dashed)
N+ Gate (Solid)
0.99 V
0.24 V
Cap
acita
nce
(pF)
60
40
20
0
NMOS PMOS
- HfO2 curves show little shift (0.13V, respectively 0.24V) → Fermi level pinning
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Materials to Study for Gate Dielectric Shown in RED
Materials to Study for Gate Electrode shown in RED
Good mid-gap metals, good N-channel metals, is P-channel still
a problem ?
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Mid Gap Metal : FDSOI for 32nm
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-9.0
-8.0
-7.0
-6.0
-5.0
Ioff
(Log
A/u
m)
400 500 600 700 800Id,sat (A/m)
Si ref.
SiGe+20%
Int. #2
SiGeSiGeNiSiGe
NiSiGe
Si
BOX
380 A
Speed : Strain
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Dual Gate Integration
FSL, IEDM 2002
Gate Last = no thermal budget issues
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The Promise of the FinFET ArchitectureFin Profile MG Metal Gate Multi Fin SRAM
FinFET integration showing :- Single Gate- Multi Gates- Independent Gates- Midgap Metal Gate and undoped channel
(FD) DevicesCalibrated circuit simulation show 34% Fmax increase at 1.1v Enable new circuits and application beyond the planar devices
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Dopant Fluctuations => Statistical Variation in IV
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Impact of Random Fluctuation on SRAM functionality(MASTAR Simulation)
Lower doping => less fluctuations
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Scaling: Transistors and Interconnections
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Interconnect Scaling Challenges7-
11 L
evel
Cop
per
Inte
rcon
nect
s
On chip in 10 years:> 35km interconnect > 20 billion vias
Challenges - Performance (switching delay ~RC)
* Resistance : Material : aluminium – copper – nanotubes ? Cross section : deposition * Parasitic capacity : low-k dielectrics
- Reliability * cleaning * enhancement – barrier layers
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Interconnect Scaling Challenges
Resistance
Reliability,Yield
Capacity
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"Sixty percent of fab-related (yield) problems are related to cleans, and another twelve percent to etching steps,"
Wide range of potential wafer cleaning technologies for robust volume production requirements at the 45nm node and below:
• incumbent : the ubiquitous RCA clean technique and its derivatives• Shock tube-enhanced laser-induced plasma (LIP) shockwaves for sub-50 nm nanoparticle removal. This approach confines LIP beams to specially engineered "shock tubes" to increase the cleaning power of shock waves. • Ionized molecular-activated coherent technology, which employs a charged solution of ammonia in water to form clusters that attract particles at the molecular level, without damaging the wafer surface.• Particles removal by forming nanoscale bubbles to absorb the contaminants• etc….
2007 Surface Preparation and Cleaning Conference, organized by SEMATECH
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Power
Power dissipation already induced major changes in technology choice (MOS versus bipolar, CMOS versus NMOS)
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2005
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. 28
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. 29
Resistance, Capacity : 3D-I, Optical Interconnect
Reduce global interconnect length
Optical interconnect ?
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Nanowires
Nano-PLA
- statistical assembly- lithographic overhead for nanowire addressing- high defect rates, the small feature
On 5 nm half pitch, NanoPLAhas 1-2 orders of magnitude greater density than 22 nm lithographic FPGAs
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New Switches Automotive SmartMOS + HDTMOS
Future applications for
very high current
Actual applications for Smart Power(Low voltage / Low current)
Application fields evolution
High Voltage IGBT
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2005
TMFreescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006. 33
TOTAL DISCRETES : 6.7% OPTOELECTRONICS : 6.4% TOTAL MOS MICRO : 21.4Diodes Displays MOS MPU
Small Signal Diodes Lamps (22%) MOS MCUZener Diodes Couplers MOS DSPTransient Protection Devices Image Senosrs (43%) TOTAL LOGIC : 25.2RF & Microwave Diodes Other Optoelectronics Logic, Standard
Small Signal Transistors Infrared Digital BipolarBipolar Small Signal Transistors Laser Pickup MOS General Purpose LogicField Effect Transistors Laser Transmitter MOS Gate ArraysRF & Microwave SS Transistors SENSORS & ACTUATORS : 2.1% MOS Standard Cells & FPLDs
Power Transistors Temperature Sensors MOS Display DriversBipolar & Other Power Transistors Pressure Sensors MOS Special Purpose Logic RF & Microwave Power Transistors Acceleration & Yaw Rate Sensors (16%) Consumer RF & Micro Pwr Transistor Modules Magnetic Field Sensors (19%) Computer & Peripherals Bipolar Gen Purpose Power Transistors Other Sensors Communication Bipolar General Purpose PTR Modules Actuators (53%) AutomotiveMOSFET Power Transistors TOTAL ANALOG : 14.4% Multipurpose & Other Field Effect Gen Purpose Transistors Standard Linear (39%) TOTAL MOS MEMORY : 23.7 Field Effect Gen Purpose PTR Modules Amplifiers MOS DRAMInsulated Gate Bipolar Transistors Interface MOS SRAM Insulated Gate BP Transistors (IGBT) Voltage Regulators & Ref (19%) Total Flash Memory Insulated Gate BP Transistor Modules Data Conversion Circuits MOS Mask PROM & EPROM
Rectifiers Comparators Total Other MemoryRectifiers, 0.5 - 3.0 Amps Application Specific Analog (61%)Rectifiers, 3.1 - 35 Amps ConsumerRectifiers, Above 35 Amps Computer & Peripherals
Thyristors CommunicationThyristors, 0 - 55 Amps AutomotiveThyristors, Above 55 Amps Multipurpose & Other
All Other Discretes
2007 (this estimation) : $253BReference: WSTS data
Some Market Data
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SiP : RCP Process
Process steps• Die placed face down on tape
mounted carrier• Non-compression encapsulant
applied over die• Low temperature cure of
encapsulant & de-tape• Panel buildup with dielectric and Cu
redistribution• Panel bumped after final dielectric
layer applied
Pre-tested dieMold frame
Carrier
Die place onto carrier tape face down prior to encapsulation.
Panel encapsulation
CarrierTape
Mold frame removed, panel separated from carrier, ready to de-tape
Solder bumpCu interconnect
Encapsulant Die
Cu via
Panel cross-section after build up process and bump appliedAnimated Build-up
Process
Finished Singulated BGA’s
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6.7% 6.4%2.1%
14.4%
21.4%25.2%
23.7%DiscretesOptoSensors+actAnalogMicroLogicMemory
2007 (this estimation) : $253BReference: WSTS data
Some Market Data
More Moore : 79.1%More Than Moore : 8.5%Others (discretes, std analog) : 12.3%
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Wafer Production Capacity
• ITRS2007 assums that CMOS scaling continues• Historic cost trends (process equipment, factory) hard to maintain• Older technologies remain in use longer than generally believed, they are the majority of existing capacity
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Wafer Capacity
0.00
1.00
2.00
3.00
4.00
5.00
6.00
2000 2001 2002 2003 2004 2005 2006 2007
Production of silicon in millions of square meters
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Searching for Solutions in the Periodic Table of Elements
High-K / Metal Gate CMOS
N+ Poly
TaC
~30 Å HfO2
~8 Å SiOxinterlayer
NMOS: Metal Gate/HfO2
PMOS: Metal Gate/HfO2
N+ Poly
TaC
~30 Å HfO2
~8 Å SiOxinterlayer
N+ Poly
TaC
~30 Å HfO2
~8 Å SiOxinterlayer
NMOS: Metal Gate/HfO2
PMOS: Metal Gate/HfO2
N+ Poly
TaC
~30 Å HfO2
~8 Å SiOxinterlayer
Materials use 1960-2000
Materials use 2000-2006
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Scalable Transistor Architectures : Forever Planar ?
Double Gate, Ultra Thin Body transistors : excellent potential, if manufacturable…
Need to detect sub-100nm defects in SOI wafers
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Conclusions• Scaling continues, driven by the economy of scale
• Mastering the rare events• More than Moore <10% of market and does not grow faster
• Manufacturing re-shapes the industry:• Economical 300mm fab = 2.5ha (5 acres) clean space class 1 @ US$ 3–10B• What about 450mm wafers ?
• The industry will continue to concentrate• Innovation requires 10-15 years to be used – is the pipeline filled ?• Model for equipment development with decreasing number of fabs ?
Ready for disruptive technology CHALLENGE : who can build the “pocket fab” ?
70 % PS30 % PMMA
TM