Current-Mode CMOS Image Sensor Ying HuangCurrent-Mode CMOS Image Sensor by Ying Huang A thesis presented to the University of Waterloo in fulﬁllment of the thesis requirement for

Current-Mode CMOS Image Sensor

by

Ying Huang

A thesis

presented to the University of Waterloo

in fulfillment of the

thesis requirement for the degree of

Master of Applied Science

in

Electrical Engineering

Waterloo, Ontario, Canada, 2002

c©Ying Huang, 2002

I hereby declare that I am the sole author of this thesis.

I authorize the University of Waterloo to lend this thesis to other institutions or individ-

uals for the purpose of scholarly research.

Ying Huang

I authorize the University of Waterloo to reproduce this thesis by photocopying or other

means, in total or in part, at the request of other institutions or individuals for the

purpose of scholarly research.

Ying Huang

ii

The University of Waterloo requires the signatures of all persons using or photocopying

this thesis. Please sign below, and give address and date.

iii

Acknowledgements

I would like to express my sincere gratitude for the friendships and support that had made

my time here at Waterloo the most rewarding experience. This thesis would not have

been possible without the countless individuals who have both inspired and supported

me along the way.

First I would like to give my sincere thanks to my supervisor, Professor Richard

Hornsey. He has been an excellent mentor and a constant source of knowledge, motivation,

and encouragement throughout my graduate studies.

My heartfelt thanks also go to Jennifer Chen who radiates energy, joy and countless

hours of entertainment, Marcus Silva for his numerous attempts at rescuing the pop

culture vacuum, Z. Shu and Ka Lok Lee for great friendships and highly appreciated

tutorials on circuit design and simulation, and Ji Soo Lee whose technical expertise has

helped me throughout my work. I would also like to thank Michael Obrecht for his support

on device simulations, and the entire Integrated Camera Group for their valuable technical

support and discussions. Many thanks to all the professors and colleagues whose pursuits

of knowledge and innovation serve as a constant source of inspiration. My deepest thanks

go to my family, who has given me unconditional love, patience, and support throughout

the years.

Finally, I am grateful for the fabrication services supported by the Canadian Micro-

electronics Corporation, and I would like to thank the Unversity of Waterloo for their

financial assistance during my graduate studies.

iv

Abstract

This thesis presents a current-mode CMOS image sensor using lateral bipolar photo-

transistors (LPTs). The objective of this design is to improve the photosensitivity of the

image sensor, and to provide photocurrent amplification at the circuit level.

Lateral bipolar phototransistors can be implemented using a standard CMOS technol-

ogy with no process modification. Under illumination, photogenerated carriers contribute

to the base current, and the output emitter current is amplified through the transistor

action of the bipolar device. Our analysis and simulation results suggest that the LPT

output characteristics are strongly dependent on process parameters including base and

emitter doping concentrations, as well as the device geometry such as the base width. For

high current gain, a minimized base width is desired. The 2D effect of current crowding

has also been discussed.

Photocurrent can be further increased using amplifying current mirrors in the pixel

and column structures. A prototype image sensor has been designed and fabricated in

a standard 0.18µm CMOS technology. This design includes a photodiode image array

and a LPT image array, each 70× 48 in dimension. For both arrays, amplifying current

mirrors are included in the pixel readout structure and at the column level. Test results

show improvements in both photosensitivity and conversion efficiency. The LPT also

exhibits a better spectral response in the red region of the spectrum, because of the n-

well/p-substrate depletion region. On the other hand, dark current, fixed pattern noise

(FPN), and power consumption also increase due to current amplification.

This thesis has demonstrated that the use of lateral bipolar phototransistors and

amplifying current mirrors can help to overcome low photosensitivity and other deterio-

ration imposed by technology scaling. The current-mode readout scheme with LPT-based

photodetectors can be used as a front end to additional image processing circuits.

v

Contents

1 Introduction 1

2 Background and Overview 5

2.1 Research and Development in Image Sensors . . . . . . . . . . . . . . . . 5

2.1.1 The Digital Approach . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1.2 Smart Sensors: Vision Algorithms using Analog VLSI Circuits . . 9

2.2 Fundamentals of CMOS Image Sensors . . . . . . . . . . . . . . . . . . . . 11

2.2.1 Optical Absorption and Photo-Generation . . . . . . . . . . . . . . 11

2.2.2 Photocurrent and Quantum Efficiency . . . . . . . . . . . . . . . . 13

2.2.3 Current density derivation . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Current-Mode Pixel Readout Structure . . . . . . . . . . . . . . . . . . . 19

3 Lateral Bipolar Phototransistor 23

3.1 Operation of Lateral Bipolar Phototransistor . . . . . . . . . . . . . . . . 23

3.2 Analysis of Lateral Bipolar Phototransistors . . . . . . . . . . . . . . . . . 26

3.2.1 A Survey of Lateral Bipolar Transistor Models . . . . . . . . . . . 27

3.2.2 Physics of Lateral Bipolar Transistor . . . . . . . . . . . . . . . . . 27

3.2.3 Base Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2.4 Substrate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

vi

3.3 Device Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4 Design of Image Sensor

Circuits and Layouts 45

4.1 Design Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.2 Pixel Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.3 Column Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

4.4 Sample-and-Hold Circuit(S/H) . . . . . . . . . . . . . . . . . . . . . . . . 57

4.5 Readout Control Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

4.6 Complete Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5 Tests and Performances 64

5.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.2 Test Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.2.1 Photosensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.2.2 Spectral Response . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.2.3 Dark Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.2.4 Image Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.3 Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

6 Conclusion and Future Work 79

6.1 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Bibliography 83

vii

List of Tables

3.1 Three device simulation structures. . . . . . . . . . . . . . . . . . . . . . . 34

5.1 Bias condition used for image capture . . . . . . . . . . . . . . . . . . . . 72

5.2 Summary of experimental results . . . . . . . . . . . . . . . . . . . . . . . 77

viii

List of Figures

2.1 CMOS APS architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Photodiode APS and logrithmic pixel structure. . . . . . . . . . . . . . . . 8

2.3 Absorption coefficients of common semiconductors . . . . . . . . . . . . . 12

2.4 Collection of photogenerated carriers through carrier drift and minority

carrier diffusion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5 Integration mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.6 Current-mode photodiode APS. . . . . . . . . . . . . . . . . . . . . . . . . 19

2.7 Current-mediated active pixel from McIlrath. . . . . . . . . . . . . . . . . 20

2.8 Three transistor configurations. . . . . . . . . . . . . . . . . . . . . . . . . 21

2.9 Two-transistor current-controlled current conveyor. . . . . . . . . . . . . . 21

2.10 Current conveyor used to fan-out current copies. . . . . . . . . . . . . . . 22

2.11 Winner-takes-all (WTA) circuit . . . . . . . . . . . . . . . . . . . . . . . . 22

3.1 Structure of a CMOS-integrated lateral PNP transistor. . . . . . . . . . . 24

3.2 Lateral bipolar transistor incorporating three SPICE Gummel-Poon models. 28

3.3 Equivalent circuit diagram of MODELLA. . . . . . . . . . . . . . . . . . . 28

3.4 Schematic cross section of a lateral PNP transistor. . . . . . . . . . . . . . 30

3.5 Lateral bipolar simulation structure. . . . . . . . . . . . . . . . . . . . . . 34

3.6 Simulated forward charcteristics of bipolar transistor Device 1. . . . . . . 36

ix



3.9 Device 2 current gain with varying base width at 0.25µm, 0.252µm, 0.255µm.. 40

3.10 Device 2 x-current density at Vbe = 0.4V and Vbe = 1.2V . . . . . . . . . . 41

3.11 LPT output characteristics for two photogeneration rates. . . . . . . . . . 42

3.12 Collector current output at different photogeneration y-characteristic length. 43

4.1 Overall image sensor design. . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.2 Image sensor current path. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.3 Pixel structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.4 Layout view of the photodiode pixel. . . . . . . . . . . . . . . . . . . . . . 48

4.5 Layout view of the LPT pixel. . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.6 Simulated pixel current output I pixel. . . . . . . . . . . . . . . . . . . . . 52

4.7 Simulated pixel current amplification I pixel/I photo. . . . . . . . . . . . . 53

4.8 Column current mirror with amplification. . . . . . . . . . . . . . . . . . . 54

4.9 Layout view of the column current mirror. . . . . . . . . . . . . . . . . . . 55

4.10 Simulated pixel current output I column. . . . . . . . . . . . . . . . . . . . 56

4.11 Simulated pixel current amplification I column/I pixel. . . . . . . . . . . . 56

4.12 Sample-and-Hold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.13 Layout view of the sample-and-hold. . . . . . . . . . . . . . . . . . . . . . 58

4.14 Shift register used to generate row select signal. . . . . . . . . . . . . . . . 59

4.15 Complete circuit schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.16 Layout view of 1× 1 array. . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.17 Simulated voltage output. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.1 Chip micrograph. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.2 Test setup for image sensor IC . . . . . . . . . . . . . . . . . . . . . . . . 66

x

5.3 Photosensitivity curve for photodiode and LPT image sensor arrays. . . . 67

5.4 Dark image for photodiode and LPT image sensor arrays. . . . . . . . . . 68

5.5 Photo-response non-uniformity. . . . . . . . . . . . . . . . . . . . . . . . . 70

5.6 Spectral response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.7 Dark signal measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

5.8 Photodiode image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.9 LPT image. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

5.10 Image captured with different V LPTgate. . . . . . . . . . . . . . . . . . . 75

5.11 Image captured with different V CMbias. . . . . . . . . . . . . . . . . . . . 76

5.12 Image captured with different V ibias. . . . . . . . . . . . . . . . . . . . . 76

5.13 Image captured with different V outbias. . . . . . . . . . . . . . . . . . . . 76

xi

Chapter 1

Introduction

Today, advances and improvements continue to be made in the growing digital imaging

world. Apart from the existing applications in fax machines, scanners, security cameras

and camcorders, new markets are emerging in the consumer imaging industry such as

digital still cameras, toys and PC cameras, cameras for cell phones and PDAs, biometrics,

and automobiles.

The two main silicon-based image sensor technologies are charge-coupled devices

(CCDs) and CMOS image sensors (CISs). Up until the mid-1990s, CCDs have been

the dominant technolgy in the imaging world, while traditional ICs are fabricated with

the CMOS technology. Since then, however, there has been a growing interest in the

development of CMOS image sensors. The historical background of these two competing

technologies is summarized in [1]. The first CCD was reported by Bell Labs in 1970. It

was adopted over other solid-state image sensors, including CIS, because of its reduced

fixed pattern noise (FPN) and smaller pixel size. In the thirty years since its inception,

CCD image sensors have attracted much of the research and development, thus achieving

a very high level of performance with low readout noise, high dynamic range, and excel-

lent responsivity. At the same time, however, the functional limitations of CCDs have

1

CHAPTER 1. INTRODUCTION 2

also become apparent. CCD fabrication process does not allow cost-efficient integration

of on-chip ancillary circuits such as signal processors, and analog-to-digital converters

(ADCs). As a result, a CCD-based camera system requires not one image sensor chip,

but a set of chips, which increases power consumption and hampers miniaturization of

cameras. In addition, the shift-style of the CCD operation does not allow “window of in-

terest” readout. Consequently, the resurgence in CIS development is primarily motivated

by the demand for an alternative imaging technology offering low cost, low power, high

miniaturization, and increased functionality. The research and development activities

in the past ten years have resulted in significant advances in CIS, offering performance

as competitive as CCD, but with increased functionality and lower power consumption.

Circuit techniques have been introduced on-chip to reduce FPN and enhance dynamic

range. In addition, the advancement and miniturization of CMOS technology, driven by

the tremendous growth in digital IC market, has outpaced similar improvements in CCD

technology [1, 2].

On the other hand, technology and device scaling does not always lead to better

image sensor performance. Wong [3] has reported on the impact of scaling on image

sensor performances, and has concluded that for CMOS technology at 0.5µm and lower,

minor fabrication process modifications and/or innovations of the pixel architecture are

required for good CMOS imaging quality. The PN junction photodiode, commonly used

in CISs, is the simplest photodetecting device and is easily integrated in a standard digital

CMOS process. Photodiode-based image sensors, however, suffer from low responsivity

to input light. Thus, the main obstacle of CIS systems comes from the unscalability and

low responsivity of the photosensor. The challenge then is to develop photodetectors and

pixel architectures that potentially eliminate these device and process limitations.

The vast majority of the reported image sensors is implemented in voltage-mode,

examples can be found in [1, 4–7]. An alternative to this architecture is the current-


mode image sensor, which has the potential to offer several advantages, including lower

supply voltage, increased dynamic range, smaller real estate, higher operation speed, and

broad design techniques such as translinear and switched-current circuits. In addition,

operations such as addition and subtraction can be more easily implemented in current

mode [8, 9].

The photocurrent of an ordinary photodiode is typically small, usually in the pico-

amperes range, the subsequent image processing is limited to the subthreshold operation

region. Commonly in active pixel sensors (APSs), the signal is amplified through charge

integration or accumulation over a time period τint. The current-mode APSs reported

so far include a charge modulation device (CMD) image sensor [8, 10] and a CMOS APS

[8, 9]. Because the operations of these image sensors generally involve a sequence of reset,

signal integration, and signal readout, they can not be used in analog parallel collective

processing schemes that are continuous in time.

Incorporating these ideas, the motivation of the present research is to design a current-

mode CMOS pixel structure, with signal amplification, which can be operated in a

continuous-time mode. Traditional analog current amplifers occupy a large silicon area

and, if included in a pixel structure, they would completely overwhelm the actual light

sensing area of the pixel, giving a diminishing fill factor. Thus, the objective of this thesis

is to explore simpler and more area-efficient methods of signal amplification at the detec-

tor and/or the circuit level. Specifically, two means of current amplification are studied.

First, lateral bipolar phototransistors (LPTs) are used as the photodetector, where the

output emitter current is amplified through the bipolar transistor action. Second, current

mirrors with amplifying ratios are used per pixel and per column. Combining these two

techniques, a prototype image sensor is designed and fabricated in a standard 0.18µm

CMOS technology. The objective in designing and building this imager has been to eval-

uate its performance for current amplification and to determine its potential for further


development.

In Chapter 2, we begin with a literature survey of the recent research and develop-

ment in image sensors. We then take a low level approach and present the fundamental

operation principles of a photodiode-based CIS. This is followed by a brief description of

the existing current-mode pixel structures.

Chapter 3 focuses on the photodetector, more specifically the lateral bipolar photo-

transistor. We first introduce the LPT with a discussion on its principle of operation. The

modelling and analysis of the LPT are adapted from traditional lateral bipolar devices.

Device simulation results are then presented and discussed. The chapter concludes on

the potential use of LPT as the photodetector in image sensors.

The complete pixel circuit design is presented in Chapter 4. A design overview is

introduced first, followed by a description of each of its main components, including pixel

structure, column current mirror, sample-and-hold, and readout control. Included is a

discussion on the use of amplifying current mirror in the pixel structure, and per column.

Whenever appropriate, HSPICE simulation results on the extracted view are presented

along with the schematic and layout view. We conclude the chapter with the full layout

of a 1× 1 pixel structure, along with its simulation results, as well as a conclusion on the

complete circuit performance.

The CMOS image sensor design is subsequently fabricated; its test results are reported

in Chapter 5. A description of the test setup is presented, along with measurement

results for photosensitivity, dark current, spectral response, and image capture. Both the

photodiode and LPT measurements are included for comparison. We finally conclude the

chapter with a discussion on the overall sensor performance.

In our final Chapter 6, we summarize on the use of LPT and current mirrors for signal

amplification along with directions for future work.

Chapter 2

Background and Overview

2.1 Research and Development in Image Sensors

There are two general trends in the development of image sensors. In the more common

digital approach, images are obtained through an image sensor array, and very little image

processing is performed at the detector level. Analog-to-digital conversion (ADC) occurs

early in the image acquisition process, and true image processing usually occurs in the

form of digital signal processing (DSP) on-chip or off-chip. The second approach applies

analog VLSI circuit techniques at the detector level, and builds perception systems where

certain low-level image processing is performed through parallel collective computation

of input signals. Often, these analog implementations are inspired by the neural networks

of biological vision systems, thus providing a similarly nonlinear and adaptive response.

This section describes these two schemes in more detail.

2.1.1 The Digital Approach

In the digital scheme, analog-to-digital conversion (ADC) occurs early and much of the

true image processing occur in the form of an on-chip or off-chip all-digital computa-

5

CHAPTER 2. BACKGROUND AND OVERVIEW 6

tion. Typically, analog circuits are employed solely to improve the performance of the

image sensor, including noise suppression such as correlated double sampling (CDS) or

delta-difference sampling (DDS), dynamic range enhancement, multiresolution imaging,

programmable amplification, and on-chip clock generation. They usually do not add to

the functionality of the image sensor system, and do not perform any image processing

computation.

There are several advantages to this approach: digital technology is a mature tech-

nology offering high noise immunity, great precision, and large dynamic range; there is

a large library of available Boolean algebra based functionalities; DSP algorithms are

generally designed by computer scientists implementing programmable algorithms, which

can be more easily designed and tested. Thus, the role of an image sensor designer is

to design photodetectors with high quantum efficiency, signal readout circuits, analog

circuits for tasks such as CDS, accurate methods of ADC, and other control, drive and

interface electronics.

The significant advancements in the development of digital electronic cameras in the

past decade are outlined by Fossum in [1]. A common implementation architecture based

on APS is shown in Figure 2.1. It includes a pixel array, which can be selectively controlled

by digital logic circuitry such as shift registers or decoders. When selected, the pixel signal

is read out to the vertical column buses. The analog signal processor can be designed

to perform functions such as charge integration, gain, sample-and-hold, and FPN noise

suppression. Additional timing and control signals can be incorporated on-chip. In Figure

2.1, a column-based ADC performs the signal translation into digital format, pixel-level

ADCs have also been reported [11, 12].

Various types of photodetectors have been developed for improved noise suppression

or greater conversion efficiency compared to the conventional photodiode. Previously

demonstrated photodetectors include photogate-APSs [1, 4], pinned photodiodes devel-


Figure 2.1: CMOS APS architecture integrating pixel array with timing and control,ADC, and other circuitry on the same chip [1].

oped by JPL/Kodak [13], charge modulation devices(CMDs) [8, 10], and base stored

image sensors (BASISs) [14, 15]. Common photogate implementations require double-

poly CMOS technology, also the use of overlying poly-Si gate reduces overall quantum

efficiency and makes it difficult to implement in advanced sub-micron processes. Pinned

photodiodes, CMDs and BASISs can be CMOS-compatible, but typically require addi-

tional fabrication steps.

There are also different pixel structures available. The conventional photodiode-type

APS and the logarithmic pixel structure are shown in Figure 2.2. In contrast to the

photodiode APS, the output of the logarithmic pixel is proportional to the logarithm of

the photosignal, thus allowing a wide intrascene dynamic range. It also does not require

charge integration, therefore, continuous-time applications are also possible. The main

drawbacks of logarithmic pixels include slow response time at low light levels, and large

FPN. Self-calibrating logarithmic pixels have been reported in [16, 17], however, these

implementations often involve a much greater pixel complexity resulting in a larger pixel

size and reduced fill factor, while providing only limited FPN reduction when compared

to the integration-mode pixels.


(a) Photodiode APS. The photodiodeis reset by transistor RST, after signalintegration, the photodiode voltage isbuffer by a source follower to the col-umn bus, selected by RS.

(b) Logarithmic pixel structure. Outputsignal is proportional to the logarithm ofthe photosignal.

Figure 2.2: Photodiode APS and logrithmic pixel structure [1].

Besides traditional voltage-mode image sensors, current-mode alternatives have been

reported [8–10]. The potential advantages of the current-mode sensor design are: lower

supply voltage, increased dynamic range, smaller real estate, higher operation speed, and

easier implementation of certain operations. Current-mode pixel designs are described in

more detail in Section 2.3.

Fossum concluded in [1, 2] that all the components of a CMOS electronic camera-on-

a-chip have been realized. As CMOS-based imaging systems on a chip are becoming a

reality, however, improvement in on-chip ADC is required. Additional functionalities such

as full-colour signal processing, auto focus, and image/video compression will eventually

be integrated onto a single chip. However, because of the often needed modifications to the

standard CMOS fabrication process (especially when designing photodetectors), a two-

chip solution is anticipated. The CMOS imaging system can potentially be partitioned

into an image acquisition and preprocessing sensor, and a separate DSP and frame buffer


chip [1].

2.1.2 Smart Sensors: Vision Algorithms using Analog VLSI Circuits

Implementing smart sensors using analog VLSI circuits is another area of development

in image sensors. This is largely motivated by the demands for increasingly more spe-

cific vision and perception related tasks. These include the operations of segmentation,

recognition and classification applied to characters, faces, and postures. In a conven-

tional imaging system, image is acquired from a camera, followed by software processing

of this raw image information on a digital platform (either DSPs or ASICs). Despite im-

proved computational capabilities of digital platforms, the complexity of the vision tasks,

especially if real-time operation is desired, usually requires high-performance DSPs, de-

manding high power consumption and cost. A solution is to shift part of the computation

into the sensor itself. Many biological visual systems have demonstrated that a large de-

gree of low-level image processing takes place at the detector level, making effective use

of the spatial arrangement of the detectors that are relatively sparsely interconnected.

More sophisticated image processing is then performed in the visual cortex of the brain.

Similarly, the aim of many recent publications on analog VLSI vision sensors is to per-

form a number of low-level image processing steps that can be more efficiently achieved

at the detector level using analog circuitry, in a parallel fashion. This approach optimizes

computational resources – power and speed can generally be saved if the image processing

can be accomplished with simple analog circuits.

Principal drawbacks of analog VLSI circuits are their lack of flexibility and precision

[18]. In contrast to programmable digital signal processors, implementations of smart

sensors are always fully custom designed and task specific. In addition, digital computa-

tions can achieve high precision and dynamic range, while the precision of analog VLSI

systems is effected by many process-dependent parameters.


However, as evident in many biological vision systems, precise computation of signal

sequences is not necessarily required for tasks involving perception. What is often needed

for these tasks is a massively parallel collective processing of a large number of signals

that are continuous in time and in amplitude. Therefore, time sampling, amplitude

quantization, and high precision may not be necessary for implementations of perception

systems that are based on the collective processing of continuous data. Low-precision

analog VLSI circuits are better suited, especially if cost and power consumption are of

concern. However, care must be taken to maintain an acceptable level of precision by

applying design techniques that minimize or even eliminate any process dependencies

[19].

A set of circuit building blocks and design techniques for implementing a variety of

vision circuits is outlined in [19–21]. MOS transistor operation in subthreshold, strong

inversion, as well as the lateral bipolar mode are exploited in various circuit configurations

including current mirrors, differential pair, translinear loops, current conveyor, and pseu-

doconductance networks. An entire family of linear and non-linear operations are thus

possible using just a limited number of transistors. A large number of vision chips have

been reported, including resistive network based silicon retina [20], shunting-inhibition

vision chips which model several nonlinear features of the biological visual system [22–24],

and motion detection chips [25]. An extensive survey of existing spatial vision chips and

spatio-temporal vision chips can be found in [18, 26].

Despite its potential advantages of faster and more efficient computation, less chip

space, and low power consumption, there have been few practical applications of analog

image sensors. Most of the research and development are mainly centred around the

universities. In [27], Arreguit and Vittoz have pointed out several reasons for this re-

luctance in the industry. Presently, analog circuits have been mainly used to implement

artificial neural networks that were developed by the computer community, and it is more


difficult to attain the opposite of developing algorithms adapted to an analog VLSI im-

plementation. Second, the requirement for memory storage of analog weights and circuit

implementation of learning algorithms still need to be explored and addressed. Many

neural or perceptive systems require a large number of interconnections to achieve the

collective computation involving a large number of cells. To address this problem, new

interchip communication architectures have been designed for analog VLSI networks. In

addition, because analog VLSI implementations are often application specific, while tra-

ditional DSP solutions are more general purpose, the development of analog VLSI ICs

can only be justified when large productions are involved. Finally, the development of

analog VLSI has not reached a sufficient maturity, much effort is still required to provide

optimal industrial solutions beyond the initial proof of concept.

2.2 Fundamentals of CMOS Image Sensors

2.2.1 Optical Absorption and Photo-Generation

Optical absorption is a fundamental process that is exploited to convert optical energy

into electrical energy. The energy-band structure of a semiconductor determines both its

electrical and optical properties. When electrons make the transitions across the energy

bandgap (Eg) between the valence and conduction band, both energy and momentum

must be conserved. Silicon being an indirect bandgap materal, requires the generation or

consumption of a phonon in connection with an electron transition.

A photon is the smallest unit of optical signal, and it can be characterized by its

energy, as E = hc0/λ0, where c0 is the speed of light in vacuum, and λ0 is the wavelength.

When the energy of the photon is greater than the bandgap energy Eg, an electron in the

valence band may be excited to the conduction band, creating an electron-hole pair. On

the other hand, photons with energies smaller than Eg with corresponding wavelength


longer than λc = hc0/Eg, are not absorbed by the semiconductor.

Figure 2.3: Absorption coefficients of common semiconductors[28].

As a measure of absorption efficiency, the optical absorption coefficient α indicates the

fraction of photons absorbed in an incremental slice of photodetecting material at a given

wavelength. Alternatively, the penetration depth of light into the material is characterised

by 1/α, which is also described by Lambert-Beer’s law as I(y) = I0 exp(−αy). I, in

photons cm−2s−1, is the intensity of light at depth y, and I0 is the light intensity at the

incident surface. Figure 2.3 shows the absorption coefficient α of various semiconductor

materials [28]. Since α is a strong function of the wavelength, for a given semiconductor

the wavelength range in which appreciable photocurrent can be generated is limited.

Silicon detectors are apppropriate for detecting light at visible and near infrared spectral

range, (≈ 0.4− 1µm), but comparing to direct semiconductors such as GaAs and InP, its


absorption coefficient is one to two orders of magnitude lower. Despite its nonoptimum

optical absorption,however, silicon optoelectronic devices and integrated circuits remain

popular because of its economical importance.

2.2.2 Photocurrent and Quantum Efficiency

As described previously, the generation of electron-hole pairs occurs as photons with

energy greater than Eg are absorbed. However, opposing this generation, carrier recom-

bination also occurs in order to maintain equilibrium. As a result, efficient collection

of electron-hole pairs is necessary to minimise recombination. As shown in Figure 2.4,

photogenerated carriers are separated into two groups, those that are generated in the

depletion region with electric field, and others that are generated in the quasineutral re-

gions of the semiconductor, where no electric field is present. Carriers that are generated

in the depletion regions are effectively separated by the electric field, whether built-in,

or externally applied. Because the carrier drift speed is high, negligible recombination

occurs, thus practically all carriers photogenerated in the depletion region contribute to

the photocurrent.

On the other hand, the carriers that are generated in the quasineutral regions are

not collected so efficiently in the absence of the electric field. Nonetheless, a number

of these minority carriers, especially those within a diffusion length away, can diffuse to

the depletion region, where they can then be collected. The minority-carrier diffusion

length is inversely related to the doping concentration, and it is typically in the order of

tens of micro-meters for a doping concentration of 1018cm−3. Figure 2.4 shows a typical

n+-p-substrate photodiode. In the heavily doped n+ region, the minority carrier lifetime

(and therefore diffusion length) is significantly reduced, resulting in a high recombination

rate.

One of the important figures of merit for photodetectors is the quantum efficiency. The


Figure 2.4: Collection of photogenerated carriers through carrier drift and minority carrierdiffusion.


external quantum efficiency η is defined as the number of photogenerated electron-hole

pairs which contribute to photocurrent, divided by the number of the incident photons.

With a known incident optical power, external quantum efficiency can be calculated from

photocurrent measurements of a photodetector. Its expression is given as η = η0ηi.

The optical quantum efficiency, η0, takes into account that a fraction of the incident

optical power is reflected due to the difference in the index of refraction between the

semiconductor and its surrounding, it is given by η0 = 1−R, where R is the reflectivity.

Internal quantum efficiency, ηi, is the number of photogenerated carriers that contribute

to the photocurrent, divided by the number of photons penetrating into the semicon-

ductor. For carrier drift, practically all carriers photogenerated in the depletion region

contribute to the photocurrent, recombination is minimal. For carrier diffusion, recombi-

nation in the quasineutral regions reduces the internal quantum efficiency. In the highly

doped region 1, the carrier lifetime, and therefore diffusion length, is significantly lower.

Consequently, for light of short wavelength, with small penetration depth, the internal

quantum efficiency is considerably reduced. Light with long wavelength penetrates deep

into region 2. Again, the recombination of carriers there reduces the internal quantum

efficiency. In addition, the minority carrier diffusion speed is slow compare to drift ve-

locities. If the operation frequency is high enough, so that the carriers generated in the

quasineutral regions do not have enough time to diffuse to the depletion region before the

light intensity is reduced again, the dynamic quantum efficiency is further reduced.

2.2.3 Current density derivation

For the PIN photodiode, as well as the PN junction photodiode, the total steady-state

current density expression is derived in [29] and is outlined below, in addition, the reader

can refer to [30] for more accurate analysis.

A number of assumptions are made: the surface n+ layer is so thin that negligible


photon absorption occurs there; thermal generation current (or dark current) can be ne-

glected; all the carriers photogenerated in the depletion region or within a diffusion length

away contribute to the photocurrent (100% quantum efficiency with no recombination).

Total current density is given as

Jtotal = Jdrift + Jdiffusion. (2.1)

In addition, the carrier generation rate has the following expression

G(x) = I0αexp(−αx). (2.2)

I0 is the incident photon flux per unit area. The drift current Jdrift is expressed as

Jdrift = −q

∫ W

0G(x)dx = qI0[1− exp(−αW )], (2.3)

where W is the depletion layer width. For x > W in the p-substrate, the minority carrier

(electrons) concentration in the substrate is determined by the one-dimensional diffusion

equation. From the continuity equation, in the absence of recombination, we can write

Dnδ2np

δx2− np − np0

τn+ G(x) = 0, (2.4)

where Dn is the diffusion coefficient for electrons in the p-substrate, τn is the lifetime of

excess electrons, and np0 is the electron density at equilibrium. The boundary conditions

are

np = np0 for x = ∞

np = 0 for x = W.

(2.5)


Using the above boundary conditions, solution to 2.4 is given by

np = np0 − [np0 + C1 exp(−αW )]exp

(W − x

Ln

)+ C1 exp(−αx), (2.6)

where Ln =√

Dnτn and

C1 =(

I0

Dn

)αL2

n

1− α2L2n

. (2.7)

The diffusion current density is given as

Jdiffusion = −qDnδnp

δx x=W= qI0

αLn

1 + αLnexp(−αW ) + qnp0

Dn

Ln. (2.8)

Finally, the total current is obtained as

Jtotal = qI0

[1− exp(−αW )

1 + αLn

]+ qnp0

Dn

Ln. (2.9)

In most cases, the term involving np0 is less important, and the total photocurrent is

proportional to the incident photon flux. The maximum internal quantum efficiency can

be obtained as

ηi =Jtotal

qI0= 1− exp(−αW )

1 + αLn. (2.10)

Equation 2.10 indicates that large α and wide depletion region are desired for high quan-

tum efficiency. As seen in Figure 2.3, the absorption coefficient drops sharply at long

wavelengths, therefore, quantum efficiency reduces.

The photocurrent of an ordinary photodiode is very small, a charge integration based

operation is common in many active pixel sensors. The basic idea is illustrated in Figure

2.5. The capacitance C consists of the capacitance of any connected device at the node V

plus the photodiode junction capacitance itself. When light illuminates the photodiode,


Figure 2.5: Integration mode operation.

the reverse photocurrent discharges the output node V, therefore we can write

C(V )dV (t)

dt= −iphoto. (2.11)

For a n+ − p diode with ND >> NA, the junction capacitance is given by

C(V ) =A

2

[2qεSiNA

V (t)

]1/2

. (2.12)

Here, A is the diode area, NA is the acceptor concentration in the substrate, and ND is the

doping concentration of the n+ region. Combining Equations 2.11, 2.12, and integrating

we find

A

2(2qεSiNA)1/2

[2√

V]V (t)+Vbi

Vreset+Vbi

= −iphotot. (2.13)

where Vbi is the built-in voltage, and Vreset is the reset reverse bias. Solving for V(t), we

get

V (t) =[V

1/2reset −

iphotot

A(2qεSiNA)1/2

]2

. (2.14)

When V(t) is plotted as a function of time, linearity in the output is observed for a time

period. Worthy noting is that since iphoto ∝ I0A, the dependence on photodiode area can-


cels out. This is not entirely true in reality, since only photodiode junction capacitance is

included in the above equation. We have neglected the photodiode peripheral capacitance

and the capacitance of connected devices, which may or maynot be area dependent. In

general, a large photodiode area with high fill factor is desired.

2.3 Current-Mode Pixel Readout Structure

Current-mode photodiode (PD) APS is discussed in [8]. Its pixel readout structure is

shown in Figure 2.6. During reset, M2 is closed, the photodiode voltage is set to V reset.

When M2 is open, V reset is stored at the gate of the active device M1. During integration,

photogenerated current raises the photodiode voltage by Qsig/CPD, where Qsig is the

accumulated charge and CPD is the capacitance associated with the photodiode. At

readout, row select is on, and current I pixel flows onto the column bus. PMOSs are used

in Figure 2.6, this pixel structure can also be implemented using NMOS with the same

operation principle.

Figure 2.6: Current-mode photodiode APS [8].

For CMOS imagers, there are a number of sources of fixed pattern noise, including

detector dimension mismatch, transistor geometry mismatch, fabrication contamination;

a main component, however, arises from the variations in threshold voltage of the active


device. A similar but improved readout structure is shown in Figure 2.7 [9]. Here, the

design is based around a dynamic current mirror with reference current. At pixel reset,

both M2 and M3 switches are closed. The drain current flowing through M1 equals to the

column reference current. Its gate voltage, at sense node, is then reset to a value needed

to supply I ref. This voltage is stored on the sense node capacitance when the reset

switch opens. Thus, to first order, the pixel output signal is independent of the threshold

voltage of the active transistor M1. During signal integration, the photogenerated current

of the reverse-biased diode reduces the voltage at the sense node. Readout can be done

nondestructively by closing the row select switch. Drain of M1 is thus connected to the

column bus, and I ref is disconnected by opening the enable switch.

Figure 2.7: Current-mediated active pixel from McIlrath [9].

Both pixel structures shown above operate in integration-mode, following a routine

sequence of reset, integration, and readout. For continuous-time analog VLSI circuits,


current readout is straight forward. A current conveyor is commonly used in many vision

chips. Its operation is explained in [19, 21]. Shown in Figure 2.8, a transistor can transfer

a current from a high-conductance to a low-conductance node, as in the common gate

configuration, or transfer a voltage from a high-impedance to a low impedance node, as in

the common drain mode. Taking advantage of these two characteristics simultaneously,

in the common drain configuration, source voltage follows change in gate voltage, at the

same time, the source current is conveyed to the low-conductance drain node.

(a) Common source(inverting amplifier).

(b) Common drain(source follower orvoltage follower).

(c) Common gate(current buffer).

Figure 2.8: Three transistor configurations.

Figure 2.9: Two-transistor current-controlled current conveyor [21].

A two-transistor current-controlled current conveyor is shown in Figure 2.9. Its op-

eration can be simply described as IZ = IX and IY = f(VX), where f() is the function

that relates the output VX to the control current IY . This function varies depending on


the transistor operation mode, which can be subthreshold, linear, or saturation. Current

conveyor can be applied in a variety of analog circuits. It can be used to fan-out copies of

the input signal, as shown in Figure 2.10. In the Winner-takes-all (WTA) circuit, shown

in Figure 2.11, node X follows the greatest input current IY i, turning off all other current

conveyors. IX is then conveyed to the output node Zi identifying the i-th input current

as being the greatest.

Figure 2.10: Current conveyor used to fan-out copies of the current IY [21].

Figure 2.11: Winner-takes-all (WTA) circuit. With N inputs, the current conveyor thathas the largest input conveys the common line current IX , the rest have zero output [21].

Chapter 3

Lateral Bipolar Phototransistor

A number of photodetector devices have been listed in the previous chapter. For CMOS

image sensors, the simplest form of photodetector is a PN-junction photodiode, which

can be easily integrated into a standard CMOS process. The photodiode, however, suffers

from low responsivity. A lateral bipolar phototransistor (LPT) is an alternative device

that can be implemented in a standard CMOS process. With careful design, high current

gain and collector efficiency can potentially be achieved for use in image sensors. This

chapter begins with a description of the LPT operation in Section 3.1, followed by a device

physics based approach in the analysis of the LPT in 3.2. Finally, in 3.3, we present the

device simulation results and discussions.

3.1 Operation of Lateral Bipolar Phototransistor

The operation of an MOS transistor as a lateral bipolar transistor is described and ana-

lyzed in [31]. For a PMOS device, with a large enough positive VG, ID − VDS becomes

independent of the gate voltage, and is proportional to the term exp(−VDS/VT ), where

VT = kT/q. Bipolar operation dominates as the source-to-drain conduction is pushed

23

CHAPTER 3. LATERAL BIPOLAR PHOTOTRANSISTOR 24

away from the device surface. Unlike bipolar technology, however, the n+ buried layer is

absent here, carriers can be injected toward the substrate. As a result, the lateral bipolar

transistor is combined with the vertical PNP, and IE splits into base current IB, a lateral

collector current IC and a substrate collector current IS [31].

Figure 3.1: Structure of a CMOS-integrated lateral PNP transistor.

A typical LPT often suffers from low current gain and collector efficiency, as well as

current gain non-uniformity, thus it has not been widely adopted for use in CMOS image

sensors. However, Sandage and Connelly have shown that the performance can be greatly

improved by adding modifications to the typical LPT, while still being compatible in a

standard CMOS process [32]. Successful implementations of LPT based image arrays for

use in fingerprint detection systems are described in [33, 34]. A LPT-type photosensor,

referred to as photo-MOS transistor, is also reported in [35], where the photosensor was

used for on-chip signal processing with resistive networks. Traditionally, the photodiode

response is low, exhibiting a maximum photosensitivity of 0.3A/W (for a wavelength of

750nm and a quantum efficiency of 50%). Either very high ohmic resistors are required

for realization of the resistive network or current amplifiers must be employed in order

to obtain significant voltage drops. The photo-MOS transistor, with a much higher

sensitivity, allows resistors with significantly lower values to be used. Besides the CMOS


process, the lateral bipolar phototransistor has also been reported in the Silicon-On-

Insulator (SOI) technology [36].

The PNP phototransistor structure, shown in Figure 3.1, consists of a p+ emitter

surrounded by a p+ collector ring, all situated in an n-well base. The ring-shaped collector

structure increases the effective sidewall area of the emitter-base region. The parasitic

vertical PNP substrate transistor is formed with the same p+ emitter, n-well base, and

the p-type substrate. This vertical PNP reduces the collector current efficiency by 30% to

40% [31]. This reduction is not an issue, since the collector is connected to the substrate

in a common-collector configuration, and the photocurrent is drawn from the emitter.

To ensure that the collector-base junction remains reverse biased, both the collector

and the p-type substrate are connected to the most negative potential. The base of the

LPT is left floating and the base current is provided by electron-hole pairs created by

the absorbed photons. Photovoltaic operation of the base-collector PN-junction occurs.

As described in Chapter 2, the absorption process is dependent on the wavelength of the

incident light, and on the depletion region depth. The photodetector current obtained

from the emitter is (β+1) times the base current. The photocurrent can thus be increased

compared to a similar sized photodiode for a given light intensity.

From a 1D analysis of the PNP bipolar transistor, current gain β is given by

β ≈

[12

(Wb

Lp

)2

+DnWbNb

DpLnNe

]−1

, (3.1)

where Ln and Dn are respectively the electron diffusion length and electron diffusion

coefficient in the p+ emitter, Lp and Dp are the hole diffusion length and hole diffusion

coefficient in the n-well base, Nb is the n-well doping density of the base, Ne is the p+

emitter doping density, and Wb is width of the neutral base region. This equation assumes

that the base current is comprised of back injection of electrons from base to emitter,


and recombination current in the neutral base. Equation 3.1 shows that current gain is

inversely proportional to the base width, therefore, as technology feature size decreases,

small base widths give the possibility of high current gain. The minimum base width,

however, is limited by the collector-base depletion layer. The n-well base region is lightly

doped compared to the p+ collector, thus the majority of the collector-base depletion

layer extends into the base. Consequently, when designing the device, a wide enough

base is necessary to prevent collector-base depletion layer from reaching the emitter. To

remedy this, a polysilicon gate is added to help control and minimize the base width.

For the PNP phototransistor, the gate is connected to the most positive potential, thus

attracting majority carriers in the base to accumulate directly under the gate, limiting

the widening of the collector-base depletion region, and setting the base width to that of

the polysilicon gate. Because of this additional control on the base width, the polysilicon

gate also reduces the sensitivity of β to fluctuations in bias conditions.

3.2 Analysis of Lateral Bipolar Phototransistors

The study of LPT in image sensors can be directly adopted from available analysis and

models of traditional lateral bipolar transistors. This section begins with a brief survey

of the available compact models. These models, however, are often inaccurate, or they

are not contained in commercially available circuit simulators [37, 38]. For these reasons,

lateral PNP transistors cannot yet be accurately represented in a circuit simulation en-

vironment. A compact and accurate modelling of the lateral bipolar transistor is beyond

the scope of this thesis. Instead, we take a qualitative approach and carry out a physics

based analysis of the LPT, focusing on steady state conditions.


3.2.1 A Survey of Lateral Bipolar Transistor Models

The available models of lateral bipolar transistor can be grouped into four general cate-

gories:

• standard SPICE Gummel-Poon vertical PNP model;

• in-house hybrid models adapted from one-dimensional vertical NPN formulations;

• subcircuits incorporating three SPICE Gummel-Poon models, representing one lat-

eral PNP and two parasitic vertical PNPs [38–40];

• physics-based lateral PNP compact models [37, 41, 42]

The first two model options are often inaccurate. They fail to take substrate interac-

tion into account. The third model, shown in Figure 3.2 predicts the substrate effect, but

it neglects the complex two-dimensional effects, especially at high current levels. O’Hara

et al. proposed the physics-based MODELLA model, shown in Figure 3.3. This model,

with 42 parameters and 6 internal nodes, provides accurate results for both the forward

and reverse active regions [37]. Due to its complexity, however, it is not used in com-

mercially available simulators. Nonetheless, because its parameters are derived directly

from the physics and structure of the lateral PNP, it incorporates various device phe-

nomenons including current crowding effects and substrate effects, therefore, it serves as

an important reference for the analysis that follows.

3.2.2 Physics of Lateral Bipolar Transistor

The LPT consists of two 1D bipolar devices: the 1D lateral PNP, obtained by taking a

horizontal cross section just below the surface of the device, and the 1D parasitic vertical

PNP, obtained by taking a vertical cross section through the emitter. In this section, 1D

analysis is performed to obtain basic current equations. 2D effects are then discussed and


Figure 3.2: Lateral bipolar transistor incorporating three SPICE Gummel-Poon models[39].

Figure 3.3: Equivalent circuit diagram of MODELLA [37].


incorporated by modifying these equations. Here, we focus our analysis on steady state

conditions. In the sections below, main current equations are outlined for the forward

active operation region, with the reverse active case following from symmetry.

Collector Current

The general expression for the collector current in a 1D bipolar device is described by the

Moll-Ross relation [43]

Ic = IsQb0

Qb

[exp

(Vbe

VT

)− 1

](3.2)

The saturation current Is is expressed as

Is = AeffqDpn

2i

NbXb. (3.3)

where Dp is the average hole diffusion length in the base, ni is the intrinsic carrier

concentration of silicon, Aeff is the effective emitter area, Nb is the base doping (assumed

constant in this case), Xb is the width of the neutral base region, Qb is the total majority

carrier charge in the neutral base which will change with current level and bias, and Qb0

is the total majority carrier charge due to impurities alone with zero bias. From the basic

Gummel-Poon model,

Qb0

Qb=

12(1 + q1) +

12

√(1 + q1)2 + 4q2 (3.4)

(1 + q1) represents the Early factor, and can be represented as

(1 + q1) = 1− Vbc

Veaf(3.5)


with Early voltage parameter Veaf . The normalized charge q2 represents the charge

storage in the neutral base region, given as

q2 =If

Ikf,

If = Is

[exp

(Vbe

VT− 1

)],

(3.6)

Ikf represents knee current in the forward mode.

Figure 3.4: Schematic cross section of a lateral PNP transistor. The series resistances inthe emitter are included. The 2D collector current is shown to consist of a purely lateralflow originating from the emitter sidewall, and a flow along curved trajectories originatingfrom under the emitter.

Shown in Figure 3.4, series resistances in the emitter cause current crowding, especially


at high current levels. The total hole current can be roughly divided into two components:

1) a purely lateral flow which originates at the emitter sidewall, and 2) a flow along curved

trajectories which originates from the bottom of the emitter. The main difficulties in

modelling the lateral transistor lie in the fact that each of these current paths contains

different series resistances in the emitter and the collector, and each has a different base

width. The latter implies different base charges Qb0, different transit times and different

Early effects.

The component Ic1 dominates at low current levels. As current level increases, there

is a greater voltage drop across the lateral emitter resistance ReLAT , and the forward

bias at the sidewall junction is thereby reduced, lowering the lateral current component

Ic1. Consequently, at high current levels, the second current component Ic2 dominates, in

addition, current crowding is observed in the region under the emitter contact. Because

of the larger effective base width associated with the trajectory path of Ic2, the collector

current and therefore current gain β , as well as Early effect is significantly reduced [37].

In the physics-based MODELLA model [37] shown in Figure 3.3, incorporating the

2D effects, two diodes and current sources are used to represent the two collector current

components Ic1 and Ic2. Both current components are defined by Equation 3.2, however,

different emitter-base voltage, saturation current and Early voltage parameters are used

in the respective expressions. O’Hara further stated that 2D current density between the

emitter and the collector can be described accurately at all current levels by multiplying

the hole current density of the 1D lateral PNP device by a multiplier. The multiplier is

dependent on the device geometry, but not on the current level. In MODELLA then, a

parameter XIFV is introduced to represent the fraction of the collector current originating

from under the emitter, such that Equation 3.2 is multiplied by (1-XIFV) to obtain Ic1,

and by XIFV to obtain Ic2.


3.2.3 Base Current

In the lateral bipolar phototransistor, the base current is supplied by the photogener-

ated carriers. The processes of optical absorption and photocurrent collection have been

described in Section 2.2.

The base current is comprised of three principal components, Ib1, due to back injection

of electrons from the base into the emitter, Ib2, due to recombination in the neutral base,

and Ib3, due to recombination in the emitter-base space charge layer. Given the forward

biased emitter-base junction, the ideal base current Ib1 is given by [44],

Ib1 =qAeffDnn2

i

WeNe

[exp

(Vbe

VT

)− 1

]. (3.7)

The second component of base current Ib2, with the following expression, is a nonideal

recombination current in the neutral base.

Ib1 =qAeffWbn

2i

2τpNb

[exp

(Vbe

VT

)− 1

], (3.8)

where τp is the minority carrier lifetime of holes in the neutral base. This component is

negligible for regular bipolar transistors implemented using modern fabrication technolo-

gies, as the base width can be significantly smaller compared to the diffusion length of

the minority holes.

The third component of base current, Ib3, is another nonideal recombination current

in the emitter-base space charge layer. The expression for Ib3 is derived from the standard

Schockley-Read-Hall formulation and is given in [43] as

Ib3 =qAeffni

2τ

[exp(Vbe/VT )− 1

exp(Vbe/2VT ) + cosh(∆Et/kT )

], (3.9)

where for simplicity τ = τn0 = τp0 = (σνthNt)−1. Nt is the trap density, and ∆Et =


Et−Ei−kT ln(gt). Et is the energy level of the traps. This recombination current occurs

under the emitter due to the large ratio of bottom-to-sidewall areas.

3.2.4 Substrate Current

The substrate current is the hole current component that travels from the bottom region

of the emitter to reach the substrate. It can be modelled with the same formulations as

the collector current in Equation 3.2. The same knee current parameter Ikf can be reused

here, since the two current components share the same emitter-base junction. The vertical

PNP bipolar structure effectively reduces the lateral collector efficiency. However, the

present application uses a common-collector configuration, and this reduction in collector

efficiency does not pose a problem.

3.3 Device Simulation

2D Device simulations were performed using the commercially available numerical device

simulator MicroTec 3.06. We begin by simulating a regular lateral bipolar device, with

a base contact to provide the base current. The goal is to study the transistor action

of the bipolar device, and see how process and device geometry variations effect the

output characteristics. The Gummel plot and the forward current gain are obtained at

different current levels. In the next step, we remove the base contact, and substitute

photogeneration parameters into the simulation.

The structure used for the device simulation is shown in Figure 3.5. Both the emitter

and the collector are p+ diffusion regions, situated in the n-well base. The process param-

eters for the targeted TSMC 0.18µm fabrication technology are not published, therefore,

the exact doping densities and junction depth of the device are not known. Generally,

as seen from Equation 3.1, for high current gain, LnNe >> WbNb is desired. This calls


Figure 3.5: Lateral bipolar simulation structure.

Device 1 Device 2 Device 3p+-diffusion doping (cm−3) 1020 1020 1020

n-well doping Nnwell (cm−3) 1017 1018 1018

diffusion junction depth (µm) 0.07 0.07 0.07n-well junction depth Ynwell (µm) 0.3 0.3 0.5

Table 3.1: Three device simulation structures with different doping densities or junctiondepth.

for high emitter doping, small base width, and low base doping. Thus, to show the effect

of process parameter variations on the output performance, three devices, with different

doping densities or junction depth (Table 3.1) were simulated. The junction depth value

quoted in Table 3.1 are y-characteristic length associated with a Gaussian-type doping

profile.

A small base width is desirable for high current gain. However, the minimum base

width is determined by the distance at which punch-through occurs such that the emitter-

base and base-collector depletion regions overlap. As stated earlier, because the base


doping is lower than emitter and collector doping, the depletion region extends almost

entirely into the base. With zero bias,the 1D depletion width of either the emitter-base

junction or the base-collector is given by,

Wdep =

√2εsNp+Vbi

qNnwell(Nnwell + Np+)(3.10)

The minimum base widths Wbase for device 1, 2 and 3, are 0.35µm, 0.25µm, 0.25µm

respectively, below which the two depletion layers would overlap. Note that the base

width quoted here is the distance between the emitter and the collector, and it includes

the actual neutral base width plus both the emitter-base and base-collector depletion

width. Device 1 has a lower base (n-well) doping density, the depletion width extends

further into the base, therefore a greater base width is required to avoid punch-through.

In the following analysis, we first simulate the forward characteristics of the three

devices, with a fixed base width at 0.35µm. Gummel plot and current gain are shown in

Figures 3.6, 3.7, 3.8. The device is operated in the forward active mode with Vbc = 0.

From Figure 3.6, the onset of high level injection occurs at around Vbe = 0.8V . At low

current levels (up to Vbe ≈ 0.4V ), the lateral current component dominates, the collector

efficiency is high, and substrate current is low. As forward bias increases, because of

current crowding, saturation current increases more rapidly than the collector current.

This effect of series resistance and current crowding is discussed in more detail in Figure

3.10. A peak current gain of 80 is observed.

As seen in Figure 3.7 when the n-well base doping increases to 1018cm−3 in Device

2, current gain drops drastically. Coupled with the higher base doping concentration,

is an increase in neutral base width, since both the emitter-base and the base-collector

depletion layers narrow. These factors induce a greater back-injection of electrons into

the emitter, thus reducing overall current gain. In addition, the lateral current gain is


(a) Device 1 Gummel plot with Vbc = 0V .

(b) Device 1 current gain IcIb

and IeIb

.

Figure 3.6: Simulated forward charcteristics of bipolar transistor Device 1 (basewidth=0.35µm).




and IeIb

.



below 1, and the substrate current dominates.

From the simulation results of Device 3 (Figure 3.8), a change in the n-well junction

depth has little effect on the lateral collector current. The vertical PNP continues to

dominate. The n-well junction depth is proportional to the effective neutral base width

of the vertical PNP. Thus, as n-well depth increases, we see a slight drop in the current

ratio Ie/Ib, indicating a reduced substrate current.

Once the fabrication process parameters are determined, current gain can be con-

trolled by varying the lateral base width. To demonstrate this, we select Device 2 as

our sample, and simulate its forward characteristics at different base widths. Figure 3.9

demonstrates that current gain is strongly dependent on the basewidth, as base width

increases current gain drops. Also worth noting is that the maximum gain achievable

with Device 2 at the minimum base width of 0.25µm is around 40 which is a half of that

achieved with Device 1, indicating again that a low base doping is desired for high current

gain.

The effect of current crowding can be seen in the X-current density graph in Figure

3.10. Here, the emitter edge is located at X = 3.752µm and the collector edge located

at X = 3.5µm. At the low forward bias of Vbe = 0.4V , the collector current flows almost

purely laterally, close to the surface, thus high collector efficiency is achieved. At bias

level Vbe = 1.2V , current gain is reduced due to current crowding, as current flows deeper

in the device with a longer trajectory path. In fact, part of the injected hole current

recombines in the n-well.

Next, to simulate the photoresponse, we remove the base contact, and define pho-

togeneration parameters for base current generation. First the output characteristic is

plotted at two different photogeneration rates: 1019cm−3 and 1020cm−3. Then, keeping

the photogeneration rate fixed at 1020cm−3, we vary the Y-characteristic length of the

photogeneration, and measure the output collector current at Vec = 0.9V . This can be




and IeIb

.



(a) Current gain IcIb

.

(b) Current gain IeIb

.

Figure 3.9: Device 2 current gain with varying base width at 0.25µm, 0.252µm, 0.255µm..


(a) X-current density Vbe = 0.4V .

(b) X-current density Vbe = 1.2V .

Figure 3.10: Device 2 x-current density at Vbe = 0.4V and Vbe = 1.2V .


alternatively interpreted as changing the wavelength of the illumination source, and mea-

suring the spectral response. We should note here that these simulations do not include

the process of optical absorption, only photogeneration rate is specified, thus it assumes

that light of all wavelength is absorbed equally. We have seen in Chapter 2 Figure 2.3

that this is not the case. Nonetheless the simulation results, shown in Figure 3.11 and

Figure 3.12, help to explain certain behaviours, and characterize the device.

Figure 3.11: LPT output characteristics for two photogeneration rates.

The LPT output characteristics are as expected. Photogeneration rate determines

the base current, and therefore the forward emitter-base bias. As photogeneration rate

increases, the output collector current increases accordingly. In Figure 3.11, the collector

current is the highest at Ychar ≈ 0.7µm. This coincides with the n-well/p-substrate

depletion layer, where photocurrent can be collected efficiently in the presence of the


Figure 3.12: Collector current output at different photogeneration y-characteristic length.


electric field. In addition, the vertical PNP depletion area is greater than the lateral

PNP, thus a greater number of photogenerated carriers can be collected. Again, we

note that this result does not take optical absorption into account. In reality, light that

penetrates deeper into the device also has a low absorption coefficient. From previous

discussions on quantum efficiency, we have concluded that the internal quantum efficiency

decreases greatly for low absorption coefficient.

In conclusion, from the simulation results presented above, the transistor output char-

acteristic is strongly dependent on process parameters such as the n-well base doping and

emitter doping. Once the process parameters are determined, high current gain can be

achieved by minimizing the base width down to the limit of punch-through. The maxi-

mum current gain of 80 is achieved using the process parameters of Device 1. In addition,

current crowding is witnessed at high bias values. Because of the associated longer base

width and increased recombination, current gain is reduced.

Chapter 4

Design of Image Sensor

Circuits and Layouts

Previously, we have explored methods of current amplification at the photodetector level,

specifically through the use of LPT. This chapter concentrates on current amplification

and other image sensor operations from the circuit and layout perspective. In Section 4.1,

we begin with an overview of a complete current-mode CMOS image sensor structure.

Current amplification through the use of current mirrors is explored in Sections 4.2 and

4.3. This amplification idea is replicated at two levels: per-pixel and per-column. In

Section 4.4, the sample-and-hold (S/H) circuit is used to sample and integrate the current

output signal. Section 4.5 describes the generation of readout control signals through shift

registers (SR). Finally, in Section 4.6 we present the complete image sensor design. Both

the circuit design and layout are targeted for manufacturing in a standard 0.18µm CMOS

technology.

45

CHAPTER 4. DESIGN OF IMAGE SENSOR CIRCUITS AND LAYOUTS 46

Figure 4.1: Overall image sensor design. The left and right arrays are made up ofphotodiodes and lateral bipolar phototransistors respectively.

Figure 4.2: Image sensor current path.


4.1 Design Overview

The complete image sensor structure is shown in Figure 4.1, and the image sensor current

path is shown in Figure 4.2. Two sets of image sensor arrays, each 70× 48, are included

for comparison. The photodetector current output (I photo) is first amplified 20 times

in the pixel current mirror. When row select is on, I pixel outputs to the column bus,

and is amplified another 20 times in the column current mirror. For signal readout,

current I column is sampled and integrated over a capacitor in the S/H circuit. When

column select is on, the capacitor voltage is readout as the output. Shift-registers are

used to generate row select and column select signals.

4.2 Pixel Circuit

Figure 4.3: Pixel structure. M1 and M2 form a current amplifying current mirror.

The pixel schematic is shown in Figure 4.3. Here, the current mirror (M1 and M2)

is designed such that W/LM2 = 20 × W/LM1, the photo current is thus amplified 20


Figure 4.4: Layout view of the photodiode pixel.


Figure 4.5: Layout view of the LPT pixel. The output current is taken from the emitter.The collector is connected to ground. The base is left floating.


times. The output impedance of this simple current mirror is finite, as a result, the

output current is sensitive to the fluctuations of the drain-source voltage of M2 due

to channel-length modulation. Various methods of enhancing the current mirror out-

put impedance are outlined in [45]. In this design we use a feedback circuit (M3, M4)

to keep a stable drain-source voltage across M2. The output impedance is given by

rout ' 0.5× (gM3gM4rds2rds3rds4)[45]. Transistor M7 is used to bias the feedback circuit.

Alternatively, from an analog VLSI viewpoint, M2 and M3 can be thought of as a current

conveyor. Current output from M7 controls the gate voltage of M3, or the drain voltage

of M2. M4 then acts as a current buffer, and conveys current from the high conductance

source to the low conductance drain. When row select (M5) is on, pixel current is output

to the column bus. Transistor M6 allows current discharge when the row is not selected.

Although the photodiode is shown as the photodetector in Figure 4.3, the schematic

is the same for the LPT. The emitter of the LPT connects to the drain of M1, the

base is left floating, while the collector is connected to ground along with the substrate.

The layout view for the two photodetectors are presented in Figures 4.4 and 4.5. The

photodiode consists of n+-diffusion on p-substrate, and the photocurrent is extracted

from n+-diffusion. In the LPT case, a rectangular p+-diffusion emitter is surrounded

by a p+-diffusion collector, increasing the emitter cross-sectional area, both are enclosed

in a floating n-well base. Ideally, a ring-shaped gate, surrounding the emitter, can be

used to minimize the base width on all sides. However, in the present CMOS process a

ring-shaped gate is not allowed. As a result, polysilicon gate is placed on two sides, and

the base width of the remaining two sides is enlarged, at the cost of a lower current gain.

Unfortunately, the process parameters of the fabrication technology are not released, so

a conservative base width (1µm horizontally and 1.5µm vertically) is selected to avoid

punch-through. This can potentially be reduced in the future for higher current gain.

In addition, an n+-diffusion region is placed in the base to increase majority carrier


concentration, generating more photo-current for a given illumination intensity. The

collector is shorted to ground, along with the substrate, therefore the lateral and the

parasitic vertical bipolar phototransistors work simultaneously. Although the pixel size

in both cases is 21.54µm × 18µm, because of the greater layout complexity of LPT, its

actual light sensing area is lower at 57.92µm2 (15% fill factor), comparing to photodiode

with light sensing area of 103.84µm2 (27% fill factor).

In a standard CMOS technology, through a process of metal deposition on silicon

and wafer annealing, self-aligned silicide (or salicide) structures form on gate, source and

drain regions [46]. While silicide provides key benefits such as lowered sheet resistance of

gate, source, and drain areas,lowered contact resistance, and therefore improved device

speed, it is also opaque, and only 10% of the light is transmitted to the silicon substrate,

resulting in a significant reduction of photosensitivity of the sensor [3]. Consequently,

the layout of the photodiode and the LPT must also include a protection from salicide.

This can be done by defining a Resist Protective Oxide (RPO) layer, spanning the light

sensitive area of the photodetector. Design rules regarding RPO are well documented for

a specific process technology.

Precise transistor matching is an important factor for accurate current mirror oper-

ation, especially in the case when transistors operate in the subthreshold region . The

common-centroid layout approach [47] is used for implementing current mirrors. M2 in

Figure 4.3 combines ten unit transistors (each with a W/L ratio of 2µm/0.5µm). When-

ever possible, the layout of M1 and M2 are interdigitated, to help match errors caused

by gradient processing effects across a microcircuit. In addition, the transistor sizes are

enlarged beyond the minimum gate length of 0.18µm. The current mirror transistors are

all designed with a gate length of 0.5µm, again to minimize the effect of process variation

on current mirror performance. The trade off for larger device size is that the pixel fill

factor will be reduced.


In addition, the layout of the photodetector is surrounded by a guard ring of p+

connections to ground. This helps to reduce propagation of substrate noise from the

rest of the pixel circuit. It also prevents photogenerated carriers in the photodetector

substrate from diffusing to neighbouring circuits or photodetectors.

Figure 4.6: Simulated pixel current output I pixel.

Schematic and layout were entered using Cadence tools. The pixel layout was subse-

quently simulated using HSPICE (Figures 4.6). HSPICE does not include photodetector

circuit models, the photodiodes and the LPT are thus modelled as a current source (with

output current I photo) in parallel with a 50nF capacitor. Current amplification is plot-

ted in Figure 4.7. At medium I photo levels, the amplification factor is constant, at low

current levels, however, the amplification increases drastically beyond 20 times. With low

I photo, transistors in the current mirror operates in the subthreshold region, in which

current relates to drain-source voltage as


Figure 4.7: Simulated pixel current amplification I pixel/I photo.

IDS = I0(VGS)[1− exp

(−qVDS

kT

)]. (4.1)

Given a fixed VGS , if VDS is greater than 3(kT/q) (≈ 75mV ), the exponential term

in Equation 4.1 approximates to 1. This, however, is not the case for transistor M1

(Figure 4.3) when I photo is low. At I photo=2pA, VDS as well as VGS are approximately

50mV. At low current levels, despite enhanced output resistance of M2, the effect of

drain-source voltage variation is more pronounced. Consequently, the linearity of current

signal output is reduced under low light conditions. The amplification starts to degrade

beyond I photo = 1µA. This, however, does not have a big effect, since I photo is generally

in the pA ∼ nA range.


Figure 4.8: Column current mirror with amplification. M4 and M5 enhance the outputimpedance.

4.3 Column Current Mirror

The concept of using current mirrors to amplify signal is duplicated again at the column

level. I pixel from the column bus is amplified an additional 20 times in each column.

The total current amplification factor is now ideally 400 times. The schematic of the

column current mirror is shown in Figure 4.8. Similar to the pixel design, amplification

is achieved by designing W/LM6 = 20 × W/LM3. M4 and M5 are included again to

enhance output impedance of the current mirror. The circuit including M1, M2, and M3

operates almost identically to a diode-connected transistor, it is used to ensure that all

transistor bias voltages are matched to the output side (M4, M5, and M6). Transistors

M7 and M8 are used to bias the feedback circuit. The layout view is shown in Figure 4.9.

The same layout techniques used in the pixel are employed here to improve transistor

matching. The current mirror transistors are composed of single-sized unit transistors,

with interdigitated fingers. The minimum gate length used is 0.5µm.

The HSPICE simulation results are shown in Figures 4.10 and 4.11. Simular to the


Figure 4.9: Layout view of the column current mirror.


Figure 4.10: Simulated pixel current output I column.

Figure 4.11: Simulated pixel current amplification I column/I pixel.


pixel case, the current amplification is constant at medium current input ranges, and

increases drastically at low I pixel value. This performance is adequate for application at

hand, since I pixel is expected to be in the range of 20pA ∼ 20nA.

4.4 Sample-and-Hold Circuit(S/H)

Figure 4.12: Sample-and-Hold.

Once the current signal has been amplified by the column current mirror, its output

is then suitable for any subsequent current mode image processing, either in continuous

time or integration mode. This prototype chip, however, is mainly designed to make

pixel responsivity, noise, and uniformity measurements, the output of the column current

mirror is therefore connected to a sample-and-hold circuit with output buffer. Strictly

speaking, the S/H circuit is not necessary, but because there is not a reliable way of accu-

rately measuring output current with presently available lab equipments, the S/H circuit

essentially performs current-voltage conversion. Alternatively, for real-time continuous-

mode operations, a transresistance amplifier can be used at the output (either on-chip or

off-chip). In the sample-and-hold circuit (Figure 4.12), Vcap is first reset to VDD through


Figure 4.13: Layout view of the sample-and-hold.


reset transistor M3. When sample is on, current I column discharges Vcap through M2 for

a sampling period τint. After τint, sample is switched off, I column is discharged through

M1, and Vcap remains constant. Transistors M4-M9 make up a differential unity gain

amplifier. When column select is on, Vcap is read out as Vout.

The S/H layout is shown in Figure 4.13. A metal-to-metal capacitor (MiM capacitor)

is created in the layout. Since each column has its own S/H, capacitor matching between

columns is essential for good output uniformity. In this design, the capacitor is composed

of eight smaller unit-sized capacitors, with equal perimeter-to-area ratio. Also to ensure

that the boundary conditions around the unit-sized capacitors match, additional dummy

top-plate metal is added around the outside edge of the capacitor array.

4.5 Readout Control Circuits

Figure 4.14: Shift register used to generate row select signal.

This section briefly discuss the implementation of readout control signals. Two struc-

tures commonly used to generate row select or column select control signals are shift reg-

isters and decoders. In this design, shift registers are used for its simplicity. Its imple-


mentation using D flip-flops (DFF) is shown in Figure 4.14. Inverters are included at the

output since both the row select and column select are active-low signals. Two DFFs are

used per row to allow for sufficient time period between subsequent row select calls. The

DFFs and inverters used here are part of the standard library cells supplied by Virtual

Silicon Technology.

4.6 Complete Design

Figure 4.15: Complete circuit schematic.

The complete design schematic is present in Figure 4.15. Summarizing the previous

sections, as the sensor is exposed to light, photogenerated carriers contribute to the

photocurrent I photo. In each pixel, I photo is amplified 20 times with the use of 1:20

current mirrors. When a row is selected, the amplified I pixel reaches the column bus. Each

column has an additional amplifying current mirror. Here I pixel is amplified further, so

that I column ' 400× I photo. Within S/H circuit, Vcap is initially reset to VDD. When

sample is on, I column discharges Vcap for a period τint. Finally, Vcap is readout as Vout


Figure 4.16: Layout view of 1× 1 array.


when column select is on.

For demonstration purpose, the layout of a complete 1 × 1 array is shown in Figure

4.16. In addition to the layout features discussed in the previous sections, a number

of noise reduction techniques are worth noting. Two different power-supply connections

(with separate I/O pins) are used, one for the digital shift register circuit, and the other

for analog circuits in the rest of the design. This is done to reduce the effect of digital

glitches associated with on/off states on the analog circuitry. The analog circuit is located

in the center of the layout, surrounded by digital circuit at the periphery. Guard rings

and wells connecting to power-supply voltages separate the digital and analog circuits,

preventing substrate noise from propagating through the resistive substrate, as well as

lowering noise on VDD.

Figure 4.17: Simulated voltage output.

The layout of the 1× 1 image array is simulated using HSPICE. The sampling period

of τint = 100µs is used in the sample-and-hold circuit. In Figure 4.17, the S/H capacitor

voltage as well as the output voltage are plotted as a function of photocurrent. Good

output linearity is observed, even at very low photocurrent values. The functionality


of the output buffer is also established. The output voltage tracks closely to the S/H

capacitance voltage. Slight discrepancies are seen at high photocurrent values, as Vout

reaches the full voltage swing of the output buffer unity gain amplifier.

In conclusion, a complete image sensor has been designed. It has a current readout

scheme, and can be used in the continuous-time mode. Current amplification through

1:20 current mirrors have been verified. The amplification is constant for the most part of

the applicable photocurrent range, although, some nonlinearity will be expected at very

low current values. The functionalities of all other sensor components have been verified

through HSPICE simulations.

Chapter 5

Tests and Performances

The previous section outlined a CMOS image sensor design, consisting of photodiode

and LPT image arrays, each 70× 48 in dimension, current mirrors with 1:20 amplifying

ratio are designed at the pixel and the column level, the signal is subsequently readout

through a sample-and-hold circuit. Through the Canadian Microelectronics Corporation

(CMC), the design was manufactured by TSMC using a standard 0.18µm, single poly, six

metal, salicide CMOS process. The device is then enclosed with a 68 pin PGA package.

The chip micrograph is shown in Figure 5.1, with the image sensor array located in the

center, and shift registers on the perimeter of the chip. This section begins with a brief

description of the test setup, followed by a presentation of the test results. Measurements

can be grouped into four categories: photosensitivity, dark current, spectral response,

and image acquisition. In each case, the response of both the photodiode array and the

LPT array are measured and compared.

64

CHAPTER 5. TESTS AND PERFORMANCES 65

Figure 5.1: Chip micrograph (area 3.0mm× 3.0mm).

5.1 Test Setup

The test setup is shown in 5.2. An illumination source is placed before an integrating

sphere, providing a diffused uniform illumination onto the image sensor IC. The image

sensor is then mounted on top of a test board, which also has connections to power

supplies, pattern generation and data acquisition cards on the host PC. CompuGen and

CompuScope cards, both from Gage Applied Inc., are used for pattern generation and

data acquisition. The software interface to the CompuScope data acquisition card is

created in LabVIEW.

5.2 Test Measurements

5.2.1 Photosensitivity

Photosensitivity is measured with a fixed sampling rate, and the wavelength of the il-

lumination source is set at 540nm, the light intensity is then varied from zero until the


Figure 5.2: Test setup for image sensor IC. The chip is mounted on the test board.Power supplies input bias and VDD voltages to the test board. Ribbon cables connectthe pattern generation card (on PC) to the test board. Outputs from the chip are obtainedthrough a data acquisition card (on PC).

point when the output voltage saturates. As light intensity increases, the photocurrent

increases, and the amplified current output is allowed to integrate over the capacitance

in the sample-and-hold circuit for a fixed integration time τint. After τint, the output

voltages of the 70 × 48 array is captured as an image. The average output voltage, as

well as the standard deviation are then calculated from the image.

The photosensitivity for both the photodiode and LPT arrays is shown in Figure

5.3. The approximate linear trendline with slope is included in both graphs. For the

photodiode array, τint is fixed at 0.2ms. The saturation voltage level is 0.992V . Photo-

sensitivity is calculated to be 40.5V/s ·µW/cm2, or 6.21V/lux ·s (1µW/cm2 = 6.51582lux

at λ = 540nm). Conversion efficiency (CE) can be calculated as

CE = Vsat

[PAeffQE(1−R)τint

Ephoton

]−1

where P is the light intensity when the output saturates, Aeff is photosensitive area of the

photodetector, QE is the quantum efficiency (approximated to be 40%), R is the reflection

coefficient (approximated to be 40%), τint is the integration time in the sample-and-hold

circuit, Ephoton is the photon energy, given by Ephoton=hf [48]. The conversion efficiency of


(a) Photodiode photosensitivity plot, λillumnation =540nm, τint = 0.2ms, saturation level=0.992V.

(b) LPT photosensitivity plot, λillumnation =540nm, τint = 20µs, saturation level=1.026V.

Figure 5.3: Photosensitivity curve for photodiode and LPT image sensor arrays.


the photodiode is 51.75µV/e−. In comparison, the LPT has a saturation level of 0.9616V,

its photosensitivity is 81.34V/lux · s, and conversion efficiency is 1273µV/e−. Comparing

to a sensor reported in [48], that has a photosensitivity of 0.575µV/e−, and conversion

gain of 1.05µV/lux · s, this design offers a much improved performance. Comparing to

the photodiode, because of the additional current gain in the LPT, the lateral bipolar

phototransistor has a photosensitivity improvement of 13.1, and a conversion efficiency

improvement of 24.6.

Output nonlinearity is observed in both arrays. This is attributed to the changing

modes of operation of the transistors as the photocurrent increases. When the driving

transistors reach the saturation region, gain increases, and so follows the photosensitivity

curve. When the transistors enter the linear operation region, the photosensitivity drops.

Also worth noting is that because of nonlinearity in the LPT photosensitivity plot, its

response is compressed at both low and high light intensities, giving high contrast output

images.

(a) Photodiode dark im-age.

(b) LPT dark image.

Figure 5.4: Dark image for photodiode and LPT image sensor arrays.

The image taken with zero light intensity is shown in Figure 5.4. Across the photodi-


ode image array, the standard deviation for the photodiode output voltage is calculated

to be 21mV rms (2.1% of the saturation voltage). For the LPT array, the standard devia-

tion at dark is 3.6mV rms (0.4% of the saturation voltage). These values are comparable

with the image sensors reported in [48] with FPN at 16mV rms (1.3% of saturation). It

is apparent from Figure 5.4 that FPN is dominated by column-to-column variations. The

main source of this noise is believed to be due to capacitance mismatch in the sample-

and-hold structure. If so, this is not a serious concern, since the S/H circuit is included

for testing purposes, and is not an inherent part the current-mode design. In addition,

noise cancellation techniques or correlated double sampling (CDS) can be used to help

correct mismatches.

The standard deviation across the image was measured at each light intensity, and

is plotted in Figure 5.5. An interesting signal-dependent noise pattern is observed. In

general, fixed pattern noise increases with gain. For both arrays, pattern noise peaks at

a light intensity of 40µW/cm2, beyond which NMOS driving transistors are believed to

enter the linear region of operation, with a lower gain. This mode transition occurs again

at 80µW/cm2 after which the PMOS driving transistors enter the linear region. LPTs

observe a higher FPN compared to photodiodes because of the additional current gain

involved.

5.2.2 Spectral Response

To measure spectral response of the photodetector, the wavelength of the incident light

is varied using optical filters, while both the illumination and τint are kept fixed. The

average output voltage is recorded at each wavelength.

The spectral response comparison of the photodiode and the LPT is shown in Figure

5.6. The response of the LPT is improved in the red region of the spectrum, with longer

wavelength ranging 700-800nm. Light of long wavelength has greater penetration depth


(a) Photodiode mismatch.

(b) LPT mismatch.

Figure 5.5: Photo-response non-uniformity.


Figure 5.6: Spectral response.

into the photodetector device, and because of the parasitic VPT, existing along side

the LPT, carriers, generated by long-wavelength photons, can be collected in the base-

collector depletion region between n-well and p-substrate. This result agrees with the

device simulation results presented in Chapter 3.

In the blue-green region, the response of the LPT degrades slightly. Comparing to the

photodiode, whose depletion region has a relatively large effective area (∼ 103.84µm2), the

ring-shaped collector of the LPT offers less real-estate for carrier collection (∼ 57.92µm2).

In addition, the LPT base-collector consists of p+-diffusion on n-well, and because of

its relatively higher doping concentration comparing to the n+-diffusion on p-substrate

photodiode, the depletion region depth is also reduced.

5.2.3 Dark Current

Dark signals are measured with no light, while changing integration time. Figure 5.7

shows the output for both the photodiode and LPT. Because of the current amplification

in the design, dark signal is also amplified. It is calculated to be 1.13V/ms for photodiodes


Figure 5.7: Dark signal measurement.

and 1.14V/ms for LPT. This is significantly higher than the 0.3V/s reported in [48].

5.2.4 Image Capture

To capture an image, a lens fixture is installed in front of the image sensor, and it is

focused on a sample photo of Audrey Hepburn. The default bias condition used during

image capture is summarized in Table 5.1.

VDD 2VV CMbias 0.8VV ibias1, V ibias2 1.2VV outbias 1.2VV LPTgate 2.0Vτintphotodiode 0.2msτintLPT 0.02ms

Table 5.1: Bias condition used for image capture

The acquired photodiode images are shown in Figure 5.8. The raw image output is


displayed in the first column, followed by an image of the dark background, depicting

the FPN. The third image is the subtraction of the two, in the hope that FPN would

be eliminated. As seen in Figure 5.8(a), column based noise is clearly apparent in the

output image. After noise subtraction, the processed image does have a higher contrast,

as well as a cleaner image quality especially in the dark regions. Worth noting, however,

is that FPN is signal dependent, as shown in Figure 5.5. As a result, noise subtraction

is most effective in the dark regions of the image, with similar signal values as the noise

image itself, and less effective in the brighter areas.

(a) Raw image (b) Background image (c) Processed image

Figure 5.8: Photodiode image.

The LPT images are shown in Figure 5.9. The contrast, in general, is much higher

compared to the photodiode array. This corresponds with the more contracted photo-

sensitivity plot (Figure 5.3(b)). Because of the high contrast, the effect of FPN is not

distinctive, and noise subtraction does not provide any obvious image quality improve-

ment.

In this image sensor design there are several voltage inputs that can be controlled,

namely V LPTgate controlling the gate of the LPT photodetector, V CMbias (in Figure


(a) Raw image (b) Background image (c) Processed image

Figure 5.9: LPT image.

4.3), V ibias1 and V ibias2 (in Figure 4.8), and V outbias (in Figure 4.12). In order to

examine the effect of these voltage inputs, we vary them one at a time, while keeping the

rest at the level stated in Table 5.1. V LPTgate is applied to the gate that is situated in

between the emitter and the collector of the LPT. For a PNP transistor, as V LPTgate

increases, more electrons accumulate under the gate, inhibiting the purely lateral current

flow from the emitter sidewall to collector. Instead, current flow is pushed deeper into

the device. Because of the associated trajectory path, effective base width increases,

and current gain is reduced. This can be seen in Figure 5.10. The output image is the

brightest (to the point of saturation) at V LPTgate=1.7 V, and darkens as V LPTgate

increases, indicating lower current gain.

All other bias voltages do not have a great impact on the output image. As seen

in Figure 5.11, when V CMbias is between 0.2V to 0.9V, little change is detected in the

output image. The image starts to degrade at V CMbias=1V. For V ibias (Figure 5.12) ,

image quality stays constant between 0.8 V to 1.4V. Finally for V outbias (Figure 5.13),

image quality stays constant until V outbias reaches 1.3V.


(a) V LPTgate=1.7 V (b) V LPTgate=1.8 V (c) V LPTgate=2 V

(d) V LPTgate=2.2 V (e) V LPTgate=2.3 V (f) V LPTgate=2.4 V

Figure 5.10: Image captured with different V LPTgate.


(a)V CMbias=0.2V

(b)V CMbias=0.4V

(c)V CMbias=0.9V

(d)V CMbias=1.0V

Figure 5.11: Image captured with different V CMbias.

(a) V ibias=0.8V (b) V ibias=1V (c) V ibias=1.4V (d) V ibias=1.6V

Figure 5.12: Image captured with different V ibias.

(a)V outbias=0.4V

(b)V outbias=0.8V

(c)V outbias=1.0V

(d)V outbias=1.3V

Figure 5.13: Image captured with different V outbias.


5.3 Performance Summary

In conclusion, the chip characteristics are summarized in Table 5.2.

Photodiode LPTTechnology TSMC 0.18µm CMOS, single poly six metal, salicidePackage 68-pin PGASupply voltage VDD = 2V VSS = 0V

Output analog outputChip Size 3.0mm× 3.0mm

Array size 70× 48 70× 48Pixel size 21.54µm× 18µm 21.54µm× 18µm

Fill factor 26.78% (103.84µm2) 14.94% (57.92µm2)Max. Frame Rate 24 frames/s 32 frames/sPower 152mW 200mWphotosensitivity (λ = 540nm) 6.21 V/lux · s 81.34 V/lux · sConversion Gain 51.75µV/e− 1273µV/e−

FPN(rms) 21mV(2.1% of sat.) 3.6mV(0.4% of sat.)Dark Signal 1.13V/ms 1.14 V/ms

Table 5.2: Summary of experimental results

In this design current amplification is achieved through the use of lateral bipolar

phototransistors and current mirrors. The photosensitivity and conversion efficiency have

been greatly improved. Because less integration time is required for image capture, good

frame rate can also be achieved. Due to the n-well/p-substrate depletion layer, the

spectral response of the LPT is improved in the red regions of the spectrum compared

to the photodiode. On the down side, FPN and dark signal are amplified along with the

signal itself. Power consumption is large due to the number of current sources in the

circuit. This can be partially relieved by adding switches in the circuit, which disable

power supplies when not in use. Nonlinearity in photosensitivity is observed in both

arrays, but the effect is more prominent in the LPT array, whose output image appears

more contrasted. The column-based FPN is apparent in output images–this is due to

capacitance mismatch in the sample-and-hold circuit, which is only included for testing


purposes, and therefore, it does not pose a serious problem. Finally it is worth noting

that, because of the greater layout complexity, in an equal sized pixel structure, the LPT

will always have a lower fill factor than a photodiode.

Chapter 6

Conclusion and Future Work

As the imaging market continues to expand with new emerging applications, CMOS

image system has become a major research topic because it allows a high level of on-

chip logic, memory and signal processing function integration. Significant performance

improvements and increased functionalities have been reported in the past decade. An

inherent concern for CMOS-based imaging systems comes from the low responsivity of

the photodetector. The imager performance can be further impaired by the continuing

device scaling below 0.5µm, coupled with the rapid reduction of analog voltage swing [3].

As a result, innovations in image sensor design are necessary to overcome these limitations

imposed by the technology.

Current-mode signal processing has several advantages over the conventional voltage-

mode processing, including low supply voltage, potential for high-speed operation, and

broad design techniques. Consequently a current-mode readout scheme is desired. Com-

bined with the need to improve photodetector sensitivity, as well as allowing more circuit

design freedoms, this thesis explores current amplification schemes at both the photode-

tector level and at the circuit level.

We first exploit the use of a MOS transistor as a bipolar sensor device, where cur-

79

CHAPTER 6. CONCLUSION AND FUTURE WORK 80

rent gain is achieved through its transistor action. In addition to the parasitic vertical

PNP structure, a lateral structure can be very easily implemented in a standard CMOS

technology, which adds an extra degree of design freedom. The understanding of the

LPT operation is adopted from existing models and analysis of the regular lateral bipolar

transistor, the only difference being that the base current in a LPT is provided through

photogeneration. A physics based approach is used here in order to give greater insight

into the device behaviour, including 2D effects such as current crowding and substrate

current. We conclude that the current gain is a strong function of base and emitter

doping, as well as the base width. While the base and emitter doping is dictated by the

specific fabrication technology, the base width is the only design parameter for a pixel

designer. From 2D device simulation results, using estimated process parameters, the

highest achievable current gain is around 80.

The simplest form of achieving current amplification at the circuit level is through

current mirrors. The major design issues concerning current mirrors are the finite output

impedance, and the fixed pattern noise due to device mismatch. A feedback circuit is

included to improve the output impedance, and careful layout techniques are employed

to minimize mismatch.

A prototype image sensor chip, containing a photodiode sensor array and a LPT

sensor array, has been designed that incorporates the two forms of current amplification.

It has a current-mode readout scheme, and it can be used in continuous-time applications.

From test measurements, both the photosensitivity and the conversion efficiency has been

greatly improved due to current amplification. A faster frame rate is also possible. In

addition, the LPT has an improved spectral response in the red region of the visible

spectrum. On the other hand, there are a number of drawbacks, dark current, power

consumption, and fixed pattern noise all have increased as the result of current gain. In

addition, because of layout complexities of the LPT, it has a lower fill factor compared


to the photodiode. Power consumption can potentially be reduced by disabling supplies

when not in use. Image acquisition has been successfully demonstrated with this chip.

Column-based pattern noise is apparent in the output image. This is attributed to the

capacitance mismatch in the sample-and-hold circuit, and therefore, can be corrected in

future implementations.

This prototype chip has demonstrated that the use of lateral bipolar phototransistors

and amplifying current mirrors provides simple yet practical solutions to overcome the

problems imposed by the technology. Only a few recent LPT implementations have been

reported. This thesis has illustrated that because of their inherent current gain, LPTs

offer high photosensitivity and conversion efficiency, which make them attractive alterna-

tives to the photodiodes. The current-mode readout scheme proposed in this thesis can be

included as the front end to additional image processing circuits. Unlike many reported

pixel structures, whose application is limited to the integration-mode of operation, the

readout scheme propose here can also be used for continuous-time applications, such as

the smart sensors with analog VLSI circuits.

6.1 Future Work

Fixed pattern noise is an important issue in the design of CMOS image sensors. Further

investigation into the effect of device and process variations on LPT-based sensor perfor-

mance is desired. Noise analysis needs to be performed in order to identify temporal and

spatial noise sources. FPN suppression circuits can be included in future implementations.

The analysis of lateral bipolar phototransistors performed in this thesis focuses on

steady-state conditions. The diffusion of minority carriers in the base limits the switching

speed and the transit frequency. The base storage charge, the transit time, and other

parameters of the transient behaviour, as well as their effect on the dynamic quantum


efficiency should also be addressed.

In the development of image sensors, novel photodetector devices continue to be ex-

plored in order to combat limitations imposed by the process technology. Recently, a

high gain n-well/gate-tied PMOS device has been reported [49]. While appearing similar

in structure as the LPT, it is reported to be more area efficient and offers higher cur-

rent gain. This, and other types of innovative photosensor design should continue to be

investigated as technology progresses.

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Documents

Current-Mode CMOS Image Sensor Ying HuangCurrent-Mode CMOS Image Sensor by Ying Huang A thesis presented to the University of Waterloo in fulﬁllment of the thesis requirement for