Current state and future trends of Printed Wiring Boards for space applications

October 25, 2013

Toshimi Sugimura, Yamanashi Avionics Co., Ltd.

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Contents

1．Printed Wiring Boards qualified by JAXA 2．Needs for Printed Wiring Boards 3．Road map 4．Printed Wiring Boards Under Development 4.1 Fine Pattern Printed Wiring Boards 4.2 Printed Wiring Board For High speed circuitry applications 5．Summary

Confidential

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1. Printed Wiring Boards qualified by JAXA

Appendix A PRINTED WIRING BOARDS, GLASS BASE WOVEN POLYIMIDE RESIN OR GLASS BASE WOVEN EPOXY RESIN BASE MATERIAL

Appendix B FINE PITCH PRINTED WIRING BOARDS, GLASS BASE WOVEN POLYIMIDE RESIN OR GLASS BASE WOVEN EPOXY RESIN BASE MATERIAL

Appendix C DISCRETE WIRING BOARDS,GLASS BASE WOVEN EPOXY RESIN BASE MATERIAL

Appendix D PRINTED WIRING BOARDS, FLEXIBLE, POLYIMIDE FILM BASE MATERIAL

Appendix E RIGID-FLEX PRINTED WIRING BOARDS

Appendix F PRINTED WIRING BOARDS, CIC*1 CONTROLLED THERMAL EXPANSION, GLASS BASE WOVEN POLYIMIDE RESIN BASE MATERIAL

Confidential

JAXA-QTS-2140 C Printed Wiring Boards, General Specification For

The 6 types Printed Wiring Boards qualified by JAXA.

*1 CIC : Copper-Inver-Copper

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Densification

2. Needs for Printed Wiring Boards Confidential

Refinement of pattern

Low Dielectric constant materials

High Heat sinking

Devices

Space applications

Down sizing and Weight saving

Down sizing

Increasing the number of pins and Narrowing pitch

Printed Wiring Boards

(PWB)

Increasing the generation of heat

High functionality and Speeding up

Replace from other material (ex. ceramics, etc.)

High Dielectric constant materials

Low Coefficient of linear Thermal Expansion

Improve reliability of solder joint High board thickness

and High layer numbers

Small diameter and Narrowing pitch via hole

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3. Road map Confidential

2011 2013 2015 2017

2.4mmt 16Layers

φ0.35mm 1.27mm

3.2mmt 22Layers

φ0.15mm 0.8mm

L*1=0.13mm S*2=0.18mm

0.05mm 0.05mm

CIC core

Aluminum CFRP*5

*5 CFRP: Carbon Fiber Reinforced Plastics

εr*3≧4.2

tanδ*4≧0.015

Fine pattern Other Materials

εr≧10

tanδ≧0.005

Under development

Densification

High board thickness and High layer numbers

Refinement of pattern

Small diameter and Narrowing pitch via hole

High heat sinking

*1:Conductor width *2 :Conductor spacing

εr≧3.5

tanδ≧0.005

2.1~2.3mmt 14Layers

φ0.20mm 1.0mm

0.08mm 0.08mm

Low Dielectric constant materials

High Dielectric constant materials

Low Coefficient of linear Thermal Expansion

*3 εr : Dielectric constant

*4 tan δ: Dielectric loss tangent

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Confidential 4.1 Fine Pattern PWB

Target of development

• Conductor Width and Spacing : 0.08mm

• 1.0 mm pitch Area Array Package

• Number of pins : over 600pins

• Qualification : Feb. 2014.

Elemental Technologies

Densification of pattern

Via-in-Pad structure and Via fill

Cross section of Area Array Package and Printed Wiring Board

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Confidential

Pitc

h of

via

hol

e =

1.0m

m

Conductor Spacing =0.08mm

Via hole Diameter =0.20mm

Conductor Width=0.08mm

Land Diameter=0.45mm

Land to Conductor spacing＝0.155mm

Densification of pattern : Design rule for 1.0mm pitch via hole.

Cross section of A-A’

A

A’

Via hole

1.0mm

Conductor Width and Spacing=0.08mm

Conductor width =0.13mm

Land to Conductor Spacing =0.195mm

Land Diameter =0.75mm

Via Drill Diameter =0.35mm

Pitc

h 1.

27m

m

Conventional design rule

4.1 Fine Pattern PWB

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Confidential

Via-in-Pad structure and Via fill

BGA Area array Package

BGA f

Area array Package

Cross section of Via-in-Pad structure Top view of Via-in-Pad structure

Cross section of Dog-bone structure Top view of Dog-bone structure

Filled via hole

Filled via hole

Filled via hole

Filled via hole

Via land and Soldering pad

Via land

Soldering Pad

Blind via hole

Blind via hole

Via-in-Pad structure give flexibility of Soldering pads design.

4.1 Fine Pattern PWB

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Confidential

Cross section of

Blind Via Holes

Cross section of

Via Hole

Drilled hole diameter

=0.2mm

Use for Soldering pad Via-in-Pad structure and Via fill

Via filled material

Magnifying of Via-in-Pad

Via filled material

Soldering Pad

Base material

Soldering Pads surface needs to be flat without solder voids or other soldering problem. We resolve this issue by Via fill technology.

We realized that the dimple of pads is under 0.05mm and the voids of via fill material is under 10%.

4.1 Fine Pattern PWB

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4.2 PWB for High speed circuitry applications Confidential

Target of Development

• Frequency : More than 1GHz

• Impedance control : ± 10 %

• Qualification : Oct. 2014

Elemental Technologies

Processing technology for low dielectric constant material

High accuracy conductor width control

by thin conductor thickness and High multi layers

CP

U c

lock

freq

uenc

y (M

Hz)

50

5000

2000 2010 2020

500

Transition of CPU clock

10

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

0 1 2 3 4 5 6 7 8 9 10

Ｆｒｅｑｕｅｎｃｙ（ＧＨｚ）

Loss（ｄ

Ｂ/20ｃ

ｍ）

Megtron6(HVLP銅箔) FX-Ⅱ(S)(一般銅箔) EL-230T(ﾐﾄﾞﾙﾌﾟﾛﾌｧｲﾙ銅箔)

Megtron4(一般銅箔) E-679(一般銅箔)

4.2 PWB for High speed circuitry applications Confidential

We evaluate signal loss of 5 types Low dielectric constant (Low-dk) materials and conventional material. We select good result material.

100μｍ 100μｍ

120μｍ 35μｍ

Strip line Structure

Low-dk materials

Under development

Conventional material

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4.2 PWB for High speed circuitry applications Confidential

High accuracy conductor width control for characteristic impedance control

by thin conductor thickness, low profile copper foil, and high multi layers.

Conductor width=0.07mm

Conductor spacing=0.08mm

Conductor thickness=0.018mm

Conductor thickness=0.035mm

Cross section of inner layer conductors

Cross section of Printed Wiring Board

Blind via hole

Number of Signal layers of strip line structure = 6

Total number of layers = 18

Low profile copper foil

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5. Summary Confidential

•Printed Wiring Board needs to correspond to smaller and high functional devices.

Therefore, we are developing 2 types of Printed Wiring Boards, fine pattern PWB and PWB for high speed circuitry applications.

•The development of Printed Wiring Board hereafter will be targeted not only for densification, but also for high-functional aspect.

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Thank you for your attention.

Mt. Fuji was registration in World Heritage in this year,

view from Yamanashi prefecture.

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Confidential

Detail of Specification

Attachment 1. Fine Pattern PWB

Appendix BPad pitch 1.27mm

Structure Dog-BoneVia-in-Pad

（VIP）Dog-Bone

ViaDrilled holeDiameter

0.35mm

Land Diameter 1.0mmPattern (External) Width 0.13mm

Spacing 0.18mmPattern(Internal) Width 0.13mm

Spacing 0.18mmTotal 16Blind via 8Modified Polyimide 2.4mmLow-Z CTE FR-4 -

HASL2.3mm

Surface finish

1.0mm

0.10mm0.15mm0.08mm

0.45mm

0.20mm

HASL

Appendix GItem

2.1mmMaximum BoardThickness

6LayerNumbers

0.08mm14

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Attachment 2. For High speed circuitry applications Confidential

Detail of Specification High speed application AppendixB

Base Base resin Modified PPE Modified PolyimideMaterial Dk(εr) (1GHz) 3.65 4.2

Df (tan δ) (1GHz) 0.0020 0.017Total 18 16Blind via 9 8

Minimum Conductor thickness 0.018mm 0.035mm

ViaDrilled holeDiameter

0.20mm 0.35mm

Land Diameter 0.45mm 1.0mmPattern Width 0.10mm 0.13mmExternal Space 0.12mm 0.18mmPattern Width 0.07mm 0.13mmInternal Space 0.08mm 0.18mm

3.0mm 2.4mmHASL HASL

LayerNumbers

Surface finish

Item

Muximum Board thickness