CURRICULUM VITAE

October 2017

Dr. Israel Koren

Address: Department of Electrical and Computer EngineeringUniversity of Massachusetts, Amherst, MA 01003

Telephone: Office: (413)545-2643 FAX: (413)545-1993Electronic Mail: koren@ecs.umass.eduWeb home page: http://www.ecs.umass.edu/ece/koren/Personal Data: Married, 2 sons, U.S. Citizen

Academic Degrees

B.Sc., M.Sc., D.Sc. - All in Electrical Engineering, from the Technion - Israel Instituteof Technology

Academic Positions

1986 – Professor, Department of Electrical and Computer Engineering,University of Massachusetts at Amherst.

1985 – 1986 Head, VLSI Systems Research Center, Technion, Haifa, Israel.1982 – 1983 On Sabbatical leave at the Computer Science Division,

University of California at Berkeley.1979 – 1986 Senior Lecturer, Dept. of Electrical Engineering, Technion, Haifa, Israel.1978 – 1979 Assistant Professor, Dept. of Electrical Engineering–Systems,

University of Southern California, Los Angeles.1976 – 1978 Assistant Professor, Department of Electrical and Computer

Engineering, University of California, Santa Barbara.

Honors

1991 Fellow, IEEE, “For contributions to the field of fault-tolerant VLSI systems.”1991 Fellow, Japan Society for Promotion of Science.1995 Best Paper Award, IEEE Transactions on Semiconductor Manufacturing.2013 Master, Beijing DeTao Masters Academy.

Industrial Positions

Consultant to AMD, Analog Devices, Digital Equipment Corporation, ELTA, IBM,Intel Corporation, National Semiconductor, Tolerant Systems, and Tadiran.Member of the Advisory Board: Ponte Solutions, Adapteva.

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Professional Activities

1. Invited presentation, “Monitoring the State of the Physical Plant in a CPS to Detectand Counter Benign Faults and Malicious Attacks,” CPS Ed Workshop, July 17-18,2017.

2. Keynote Address, ”Detecting and counteracting benign faults and malicious attacksin cyber physical systems,” RESCUE 2017 - Workshop on Reliability, Security andQuality, ETS 2017, May 2017.

3. Keynote Address, ”Green Computing through Adaptive Multi-core Architectures,”International Conference on Green Computing and Internet of Things (ICGCIoT),Noida, India, October 8-10, 2015.

4. Invited Talk, ”Defect Reduction and Fault Tolerance in VLSI Integrated Circuits,”7th IEEE Latin America Symposium on Circuits and Systems (LASCAS’16), Brazil,Feb.28-Mar. 2, 2016.

5. Highlight presentation, “Exploring Heterogeneity within a Core for Improved PowerEfficiency,” 8th ACM International Systems and Storage Conference (SYSTOR’15),May 2015.

6. Keynote Address, “Yield Modeling: Theory and Practice,” 2012 IEEE Intern. Symp.on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, Oct. 2012.

7. Associate editor of Sustainable Computing: Informatics and Systems, since 2010.8. Associate editor of VLSI Design Journal, 2006-2016.9. Guest Editor (with D. Mosse) of a Special Issue of the Sustainable Computing: Infor-

matics and Systems Journal on the IEEE Green Computing Conference (IGCC 2011),July 2012.

10. Associate editor of IEEE Computer Architecture Letters, 2006-2010.11. Associate editor of IEEE Trans. on VLSI Systems, 2001-2006.12. Guest Editor (with L. Breveglieri) of a Special Issue of the IEEE Trans. on Computers

on Fault Diagnosis and Tolerance in Cryptography, Sept. 2006.13. Editorial Board member - book series “Sustainable Energy Developments,” CRC Press.14. Steering Committee member - IGSC - International Green and Sustainable Computing

Conference.15. Steering Committee member - ARITH - International IEEE Computer Arithmetic

Symposium.16. Steering Committee member - DFT - International IEEE Fault Tolerance in VLSI &

Nanotechnology Systems Symposium.17. General Chair - The 25th IEEE Symposium on Computer Arithmetic, June 2018.18. Co-Program Chair, IGCC 2011 - International Green Computing Conference.19. Co-General Chair, FDTC 2004-2016 - Fault Diagnosis & Tolerance in Cryptography.20. Co-General Chair, the 2013-2017 Workshops on Cryptography and Security in Com-

puting Systems.21. General Chair - The 17th IEEE Symposium on Computer Arithmetic, June 2005.22. Member of the Advisory Board - Conference on Innovative Computing Techniques,

ICICT.23. Program Committee member - IGSC 2017 - International Green and Sustainable Com-

puting Conference, October 2017.

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24. Program Committee member - DFT - International IEEE Fault Tolerance in VLSI &Nanotechnology Systems Symposium, 1989-2017.

25. Program Committee member - 6th Conference on IT Convergence and Security - IC-ITCS, Sept. 2016.

26. Program Committee member - 2nd International Conference on Information Scienceand Security, Dec. 2015.

27. Program Committee member - 11th IEEE International Conference on Green Com-puting and Communication, Sydney, Australia, Dec. 2015.

28. Program Committee member - 4th IEEE International Conference on SustainableComputing and Communication, Dec. 2014.

29. Program Committee member - HotChips 2013.30. Program Committee member - 2nd & 3rd Workshops on Manufacturable and Depend-

able Multicore Architectures at Nanoscale (MEDIAN’14-’15), Mar. 2014, 2015.31. Program Committee member - IGSC 2013 - International Green Computing Confer-

ence, June 2013.32. Program Committee member - 43rd IEEE/IFIP International Conference on Depend-

able Systems and Networks (DSN), June 2013.33. Program Committee member - ACM 2013-2015 Research in Adaptive and Convergent

Systems (RACS 2013-2015, 2017), October 2013, 2014, 2015 and 2017.34. Program Committee member - ACM 2012 Research in Applied Computation Sympo-

sium (RACS 2012), October 2012.35. Program Committee member - IEEE Workshop on Dependable Many-Core Computing

(DMCC 2012-2013), July 2012, July 2013.36. Program Committee member - AICCSA-2011, 9th ACS/IEEE International Confer-

ence on Computer Systems and Applications, Dec. 2011.37. Program Committee member - WCST 2011, 2017, World Congress on Sustainable

Technologies, Nov. 2011 and Dec. 2017.38. Program Committee member - HPCC-2010, 12th IEEE International Conference on

High Performance Computing and Communications, Sept. 2010.39. Program Committee member - 4th Workshop on Dependable Architectures (WDA),

HPCA 2010, January 2010.40. Program Committee member - DEPEND 2009-2017, The International Conference on

Dependability, June 2009 - Aug. 2017.41. Program Committee member - Systor 2009, The Israel Experimental Systems Confer-

ence, May 2009.42. Program Committee member - EUROMICRO DSD 2008 - 2012, 11 - 15 Euromicro

Conference on Digital System Design, Sept. 2008, Aug. 2009, Sept. 2010, Sept. 2011,Sept. 2012.

43. Program Committee member - ICINCO 2005-2017, International Conference on In-formatics in Control, Automation and Robotics.

44. Program Committee member - WAR 2005 and 2007, Workshop on Architectural Reli-ability.

45. Program Committee member - The 1993 - 2013, 11th through 21st IEEE Symposiumson Computer Arithmetic.

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46. Program Committee member - The Intern. Conference on Application-specific Sys-tems, Architectures and Processors (ASAP’00 - ’12), July 2000 - 2012.

47. Program Committee member - The 2000 - 2003, 2005, 2006 Pacific Rim InternationalSymposium on Dependable Computing (PRDC 6,7,8,9, 11 and 12).

48. Member of NSF Research Proposals Review Panels, Jan. 2002, Feb. 2002, March 2003,Dec. 2004, May 2009 and July 2014.

49. Presenting a tutorial on “Optimizing the Yield of VLSI Circuits,” during the Interna-tional Symposium on Quality of Electronic Design (ISQED’03), March 2003.

50. Invited presentation: “Application-Level Fault Tolerance,” at the Workshop on High-Performance, Fault-Adaptive Real-Time Systems, Nashville, Nov. 2002.

51. Guest Editor (with P. Kornerup) of a Special Issue of the IEEE Trans. on Computerson Computer Arithmetic, July 2000.

52. Co-General Chair - Yield Optimization and Test Workshop, Nov. 2001.53. Program Committee member - The 2000 and 2001 IEEE International Workshop on

Memory Technology, Design, and Testing, San Jose, August 2000 and July 2001.54. Member of an NSF Computer Architecture Research Review Panel, Feb. 1999.55. Program Committee co-chair - The 14th IEEE Symposium on Computer Arithmetic,

Australia, April 1999.56. Program Committee member - The 1997 - 2014 IEEE Symposium on Defect and Fault

Tolerance in VLSI Systems.57. Program Committee member - The 13th International Parallel Processing Symposium,

IPPS/SPDP ’99, Puerto Rico, April 1999.58. Associate editor of IEEE Trans. on Computers 1992 - 1997.59. General Chair - 1996 International Conference on Parallel Architectures and Compi-

lation Techniques (PACT96), Boston, October 1996.60. General Chair - 1996 IEEE Symposium on Defect and Fault Tolerance in VLSI Systems

(DFT96), Boston, MA, November 1996.61. Program Committee Chair - 1995 IEEE Workshop on Defect and Fault Tolerance

in VLSI Systems, Lafayette, LA, November 1995.62. Program Committee member - ASAP 92, 93, 94, 95, 96 and 97 - the Intern. Confer-

ences on Application-Specific Array Processors.63. Program Committee member - ISIS 96 and 97 - the IEEE International Conferences

on Innovative Systems in Silicon.64. Program Committee member and Panelist - The 94 and 95 Intern. Workshops on

Massively Parallel Processing using Optical Interconnections (MPPOI).65. Program Committee member - PACT 93, 94, 95 and 98, the IFIP WG 10.3 Confer-

ences on Parallel Architectures and Compilation Techniques.66. Program Committee member - XV International Conference of the Chilean Computer

Science Society, Arica, Chile, Nov. 1995 (SCCC’95).67. Program Committee member - IEEE Workshop on Fault-Tolerant Parallel and Dis-

tributed Systems, June, 1994.68. Program Committee member - The 1989, 1990, 1991 and 1992 IEEE Workshops on

Defect and Fault Tolerance in VLSI Systems.69. Program Committee Vice-Chair - 22-nd International Symposium on Fault-

Tolerant Computing, Boston, July 1992.

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70. Member of the NSF Research Initiation Awards committee, 1990.71. Co-organizer, ACM/SIGARCH workshop on “Fault-Tolerant Real-Time Systems,”

Seattle, May 1990.72. Guest Editor (with C.H. Stapper, IBM) of a Special Issue of the IEEE Trans. on

Computers on High Yield VLSI Systems, April 1989.73. Member of the Advisory Board of Frontiers in Computing Systems Research, Plenum

Annual Review Book Series.74. Program Committee member, Session Chairman and Panel participant - 16-th Inter-

national Symposium on Computer Architecture, Jerusalem, Israel, 1989.75. Presenting a tutorial on “High Yield VLSI Systems,” 16-th International Symposium

on Computer Architecture, 1989.76. Program Committee member - 19-th International Symposium on Fault-Tolerant

Computing, Chicago, Illinois, 1989.77. General and Program Committee Chairman - International Workshop on Defect

and Fault Tolerance in VLSI Systems, Amherst, Massachusetts, October 1988.78. Program Committee member and Panel participant - ASAP 93 - International Con-

ference on Application-Specific Array Processors, October 1993.79. Program Committee member and Session Chairman - International Workshop on Hard-

ware Fault Tolerance in Multiprocessors, Urbana, Illinois, 1989.80. Program Committee member and Session Chairman - International Workshop on De-

signing for Yield, Oxford, England, 1987.

Membership

Fellow of IEEE and the Computer Society of IEEE, member of ACM.

Current Research Topics

Fault–tolerance techniques, Power-efficient and Reliable Multi-cores, Secure cryp-tography, VLSI yield and reliability, and computer arithmetic.Current grants:

1. Thermal-Aware Management of Cyber-Physical Systems, supported by NSF (with C.M. Krishna), 2013-2016.

2. On-line Adaptability of Multi-Core Processors to Increase Energy Efficiency and Reli-ability, supported by the Science Without Borders Program of CAPES - the BrazilianFederal Agency for the support of graduate education (with P. Navaux, UFRGS),2014-2017.

Research Students Supervised

Supervised over 60 M.Sc and Ph.D students in the areas of Computer Architec-ture, Performance and Reliability Evaluation, VLSI Architectures, Fault-tolerantComputing, Secure cryptography, Computer Arithmetic and Floor-planning ofVLSI circuits.

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Patents:

1. US Patent 7,278,136: Reducing processor energy consumption using compile-timeinformation, Oct. 2007.

2. US Patent 6,934,865: Controlling a processor resource based on a compile-timeprediction of number of instructions-per-cycle that will be executed across pluralcycles by the processor, Aug. 2005.

3. US Patent 7,408,578: Active pixel with built in self-repair and redundancy,Aug. 2008.

Invited Seminars

Bell Labs, Murray Hill and Holmdel; Chalmers University, Sweden; Digital Equip-ment Corp., Hudson; Ecole Normale Superieure, Paris; Fairchild, Palo Alto; Hi-tachi Research Lab., Tokyo; Hughes Research Labs, Malibu; IBM - T.J. WatsonResearch Center, Yorktown Heights; IBM - Endicot; ICT, Beijing; ICT, Suzhou;Imperial College, London; Institute National Polytechnique de Grenoble, France;Intel - Haifa; Intel - Santa Clara; JPL, Pasadena; Mitre, Bedford; McGill Uni-versity, Montreal; Nippon Telephone and Telegraph Lab., Tokyo; Northern Tele-com, Ottawa; Peking University, Beijing; Politecnico di Milano; Sharp Corpo-ration, Tenri, Japan; Stanford University; Swiss Federal Institute of Technol-ogy (ETH), Zurich; Tsinghua University, Beijing; Tonji University. Shanghai;Universitat Politecnica de Catalunia, Barcelona; Technion, Haifa; Texas A&MUniversity; Tokyo Institute of Technology; Universidade Federal do Rio Grandede Sol (UFRGS), Porto Alegre, Brazil; Universidade Federal do Rio de Janeiro(UFRJ); University of Bar-Ilan, Tel-Aviv; University of Bologna, Italy; Univer-sity of California, Berkeley, Davis, Irvine and Santa Barbara; University of Haifa;University of Siena, Italy; University of Rome, Italy; University of Southern Cali-fornia; University of Texas at Austin, University of Tel-Aviv; University of Tokyo;University of Utah, Salt Lake City; Xidian University, Xian; Zhejiang University,Hangzhou.

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List of Publications – Israel Koren

Books and Book Chapters

1. Textbook: Computer Arithmetic Algorithms, 2nd edition, A K Peters, Natick, MA,2002.

2. Textbook: Fault Tolerant Systems, I. Koren and C. M. Krishna, Morgan-KaufmanPublishers, March 2007.

3. F. Regazzoni, L. Breveglieri, P. Ienne and I. Koren, “Interaction between Fault At-tack Countermeasures and the Resistance against Power Analysis Attacks,” in FaultAnalysis in Cryptography, M. Joye and M. Tunstall (Eds.), Chapter 15, pp. 257-273,Information Security and Cryptography Series, Vol. XVI, Springer-Verlag, 2012.

4. L. Breveglieri, S. Guilley, I. Koren, D. Naccache and J. Takahashi (Eds), Fault Diag-nosis and Tolerance in Cryptography, Proc. of FDTC 2011, IEEE Computer SciencePress, Sept. 2011.

5. L. Breveglieri, M. Joye, I. Koren, D. Naccache and I. Verbauwhede (Eds), Fault Diag-nosis and Tolerance in Cryptography, Proc. of FDTC 2010, IEEE Computer SciencePress, Aug. 2010.

6. L. Breveglieri, I. Koren, D. Naccache, E. Oswald and J-P. Seifert (Eds), Fault Diagnosisand Tolerance in Cryptography, Proc. of FDTC 2009, IEEE Computer Science Press,Sept. 2009.

7. L. Breveglieri, S. Gueron, I. Koren, D. Naccache and J-P. Seifert (Eds), Fault Diagnosisand Tolerance in Cryptography, Proc. of FDTC 2008, IEEE Computer Science Press,Sept. 2008.

8. L. Breveglieri, S. Gueron, I. Koren, D. Naccache and J-P. Seifert (Eds), Fault Diagnosisand Tolerance in Cryptography, Proc. of FDTC 2007, IEEE Computer Science Press,Sept. 2007.

9. L. Breveglieri, I. Koren, D. Naccache and J-P. Seifert (Eds), Fault Diagnosis andTolerance in Cryptography, Proc. of FDTC 2006, Lecture Notes in Computer Science,Vol. 4236, Springer-Verlag, Oct. 2006.

10. O.S. Unsal, Z. Wang, I. Koren, C.M. Krishna and C. A. Moritz, “An Analysis of ScalarMemory Accesses in Embedded and Multimedia Systems,” High Performance MemorySystems, Hadimioglu et al. (Eds.) Chapter 13, Springer-Verlag, 2003.

11. Two articles (Carry Look Ahead Addition, and Floating-Point) in the Encyclopediaof Computers and Computer History, R. Rojas (Editor), MosGroup, New York, 2000(Invited).

12. M. Allalouf, J. Chang, G. Durairaj, J. Haines, V.R. Lakamraju, K. Toutireddy, O.S.Unsal, K. Yu, I. Koren and C.M. Krishna, “The RAPIDS Simulator: A Testbed forEvaluating Scheduling. Allocation, and Fault-Recovery in Distributed Real-Time Sys-tems,” Dependable Network Computing, D. Avresky (Editor), pp. 413-431, KluwerAcademic Publishers, MA, 2000.

13. P. Lalwaney and I. Koren, “Fault-Tolerance in Optically Interconnected Multiproces-sor Networks,” Fault-Tolerant Parallel and Distributed Systems, D. Pradhan and D.Avresky (Editors), pp. 91-98, IEEE Comp. Society Press, Los Alamitos, CA, 1995.

14. K. Yu and I. Koren, “Reliability Enhancement of Real-Time Multiprocessor Systemsthrough Dynamic Reconfiguration,” Fault-Tolerant Parallel and Distributed Systems,D. Pradhan and D. Avresky (Editors), pp. 161-168, IEEE Computer Society Press,Los Alamitos, CA, 1995.

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15. S. Wimer, I. Koren and I. Cederbaum, “Optimal Determination of Block Dimensionsin General Floorplans,” Routing, Placement and Partitioning, G.W. Zobrist (ed.), Ch.7, pp. 237-286, Ablex Publishing Corp., 1994.

16. B. Mendelson, B. Patel and I. Koren, “Designing Special-purpose Co-processors Usingthe Data Flow Paradigm,” Advanced Topics in Data Flow Computing, L. Bic and J-L.Gaudiot (eds.), Ch. 21, pp. 547-570, Prentice-Hall, 1991.

17. Z. Koren and I. Koren, “A Unified Approach for Yield Analysis of Defect TolerantCircuits,” Defect and Fault Tolerance in VLSI Systems, Vol. 2, C.H. Stapper, V.K.Jain and G. Saucier (eds.), pp. 33-45, Plenum, 1990.

18. I. Koren (ed.), Defect and Fault Tolerance in VLSI Systems, Vol. 1, Plenum, 1989.19. I. Koren and C.H. Stapper, “Yield Models for Defect Tolerant VLSI Circuits: A Re-

view,” Defect and Fault Tolerance in VLSI Systems, Vol. 1, I. Koren (ed.), pp. 1-21,Plenum, 1989.1

20. I. Koren, “The Effect of Scaling on the Yield of VLSI Circuits,” Yield Modelling andDefect Tolerance in VLSI, W.R. Moore, W. Maly and A. Strojwas (Eds.), pp. 91-99,Adam Hillger Ltd., 1988.1

21. I. Koren and Z. Koren, “Analyzing the Connectivity and Bandwidth of Multi-processorswith Multi-stage Interconnection Networks,” Concurrent Computations: Algorithms,Architecture and Technology, S.K. Tewksbury, B.W. Dickinson and S.C. Schwartz(eds.), Chapter 26, pp. 525-540, Plenum, 1988.

22. I. Koren and I. Pomeranz, “Distributed Structuring of Processor Arrays in the Presenceof Faulty Processors,” Systolic Arrays, W.R. Moore, A. McCabe and R. Urquhart(Eds.), pp. 239-248, Adam Hillger Ltd., 1987.

23. Textbook (in Hebrew): Introduction to Digital Computers and Fortran IV Program-ming Language, 1971.

Journal Papers

24. C. M. Krishna and I. Koren, “Thermal-Aware Management Techniques for Cyber-Physical Systems,” Sustainable Computing: Informatics and Systems, pp. 39-51, Sept.2017.

25. Y. Xu, I. Koren and C.M. Krishna, “AdaFT: A Framework for Adaptive Fault Toler-ance for Cyber-Physical Systems,” ACM Transactions on Embedded Computing Sys-tems (TECS), pp. 79.1-79.25, April 2017.

26. M. Diener, E. Cruz, M. Alves, P. Navaux and I. Koren, ”Affinity-Based Thread andData Mapping in Shared Memory Systems,” ACM Computing Surveys, Vol. 49, pp.64.1-64.38, Jan. 2017.

27. M. Chhablani, I. Koren and C. Krishna, ”Online Inertia-based Temperature Estimationfor Reliability Enhancement” ASP Journal of Low Power Electronics - JOLPE, Vol.12, No. 3, pp. 159-171, Sept. 2016.

28. F. Moreira, M. Alves, M. Diener, P. Navaux and I. Koren, “A Dynamic Block-LevelExecution Profiler,” Parallel Computing, pp. 15-28, May 2016.

29. S. Srinivasan, N. Kurella, I. Koren and S. Kundu, ”Exploring Heterogeneity within aCore for Improved Power Efficiency,” IEEE Transactions on Parallel and DistributedSystems, pp. 1057-1069, April 2016.

1Reprints of these six papers appear in Manufacturing Yield Evaluation of VLSI/WSI Systems, B. Ciciani(editor), IEEE Computer Society Press, Los Alamitos, 1995.

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30. S. Wimer, A. Albeck and I. Koren, “A Low Energy Dual-Mode Adder,” Computers &Electrical Engineering Journal, Elsevier, Vol. 40, pp. 1524-1537, July 2014.

31. A. Barenghi, C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni and I. Koren, “A Com-bined Design-Time/Test-Time Study of the Vulnerability of Sub-Threshold Devices toLow Voltage Fault Attacks,” IEEE Transactions on Emerging Topics in Computing,pp. 107-118, June 2014.

32. R. Rodrigues, I. Koren and S. Kundu,“Does the Sharing of Execution Units ImprovePerformance/Power of Multicores?,” ACM Transactions on Embedded Computing Sys-tems (TECS), Vol. 14, Issue 1, pp.17.1-17.24, Jan. 2014.

33. N. Prakash, I. Koren and C.M. Krishna, “Low Cost Dynamic Architecture AdaptationSchemes for Drowsy Cache Management,” ASP Journal of Low Power Electronics -JOLPE, Vol. 9, pp. 373-388, Dec. 2013.

34. R. Ravindran, C.M. Krishna, I. Koren and Z. Koren, “Scheduling Imprecise TaskGraphs for Real-Time Applications” International Journal of Embedded Systems, Vol.6, No. 1, pp. 73-85, Jan. 2014.

35. R. Rodrigues, A. Annamalai, I. Koren and S. Kundu,“A Study on the use of Per-formance Counters to Estimate Power in Microprocessors,” IEEE Transactions onCircuits and Systems II, Vol. 60, pp. 882-886, Dec. 2013.

36. S. Wimer and I. Koren, “Design Flow for Flip-Flop Grouping in Data-Driven ClockGating,” IEEE Trans. on VLSI Systems, pp. 771-778, April 2014.

37. R. Rodrigues, A. Annamalai, I. Koren and S. Kundu, “Improving Performance perWatt of Asymmetric Multicore Processors via Online Program Phase Classificationand Adaptive Core Morphing,” ACM Transactions on Design Automation of ElectronicSystems (TODAES), Vol. 18, pp. 1-23, Jan. 2013.

38. A. Sreedhar, S. Kundu and I. Koren, “On Reliability Trojans Injection and Detection,”ASP Journal of Low Power Electronics - JOLPE, Vol. 8, No. 5, pp. 674-683, Dec.2012.

39. A. Barenghi, L. Breveglieri, I. Koren and D. Naccache, “Fault Injection Attacks onCryptographic Devices: Theory, Practice and Countermeasures,” Proceedings of theIEEE, pp. 3056-3076, November 2012.

40. S. Wimer and I. Koren, “The Optimal Fan-Out of Clock Network for Power Minimiza-tion by Adaptive Gating,” IEEE Trans. on VLSI Systems, pp. 1772-1780, Oct. 2012.

41. I. Koren and C. M. Krishna, “Temperature-Aware Computing,” (Invited Paper), Sus-tainable Computing: Informatics and Systems, Vol. 1, No. 1, pp. 46-56, Mar. 2011.

42. H. Wang, I. Koren and C.M. Krishna, “Utilization-Based Resource Partitioning forPower-Performance Efficiency in SMT Processors,” pp. 1150-1163, IEEE Trans. onParallel and Distributed Systems, July 2011 (DOI: 10.1109/TPDS.2010.199).

43. S. Sundaresan, I. Koren, Z. Koren and C. M. Krishna, “Event-Driven Adaptive Duty-Cycling in Sensor Networks,” International Journal of Sensor Networks (IJSNet), vol.6, No. 2, pp. 89-100, 2009.

44. Y. Zhou, V. Lakamraju, I. Koren and C.M. Krishna, “Software-Based Failure Detectionand Recovery in Programmable Network Interfaces,” IEEE Trans. on Parallel andDistributed Systems, pp. 1539-1550, Nov. 2007.

45. Y. Han and I. Koren, “Simulated Annealing Based Temperature Aware Floorplanning,”Journal of Low-Power Electronics, pp. 141-155, Vol. 3, No. 2, Sept. 2007.

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46. Y. Han, I. Koren and C. M. Krishna, “TILTS: A Fast Architectural-Level TransientThermal Simulation Method,” Journal of Low-Power Electronics, pp. 13-21, Vol. 3,No. 1, April 2007.

47. L. Breveglieri, I. Koren and P. Maistri, “An Operation-Centered Approach to FaultDetection in Symmetric Cryptography Ciphers,” IEEE Trans. on Computers, pp. 635-649, May 2007.

48. L. Breveglieri and I. Koren, “Guest Editors’ Introduction: Special Section on FaultDiagnosis and Tolerance in Cryptography,” IEEE Trans. on Computers, Vol. 55, pp.1073-1074, September 2006.

49. G. Chapman, Y. Audet, S. Djaja, D. Cheung, I. Koren and Z. Koren, “Self-CorrectingActive Pixel Sensor using Hardware and Software Correction,” IEEE Design & Testof Computers, pp. 544-551, Nov. 2004.

50. M. Singh and I. Koren, “Fault Sensitivity Analysis and Reliability Enhancement ofAnalog-to-Digital Converters,” IEEE Trans. on VLSI Systems, pp. 839-852, Nov.2003.

51. O.S. Unsal, R. Ashok, I. Koren, C.M. Krishna and C. A. Moritz, “Cool-Cache: ACompiler-Enabled Energy Efficient Data Caching Framework for Embedded/MultimediaProcessors,” ACM Transactions on Embedded Computing Systems, Special Issue onPower-Aware Systems, pp. 373-392, August 2003.

52. O.S. Unsal and I. Koren, “System-Level Power-Aware Design Techniques in Real-Time Systems,” (Invited paper) Proceedings of the IEEE, Special Issue on Real-TimeSystems, Vol. 91, pp. 1055-1069, July 2003.

53. M. Singh and I. Koren, “Fault Sensitivity and Tolerance of the Successive Approxima-tion and Delta-Sigma Analog-to-Digital Converters,” International Journal of AnalogIntegrated Circuits and Signal Processing, Vol. 35, Special Issue on Quality ElectronicDesign, pp. 189-197, May 2003.

54. G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, “Error Analysis andDetection Procedures for a Hardware Implementation of the Advanced EncryptionStandard,” IEEE Trans. on Computers, Special Issue on Cryptographic Hardwareand Embedded Systems, pp. 492-505, April 2003.

55. V. Lakamraju, I. Koren and C.M. Krishna, “Filtering Random Networks to SynthesizeInterconnection Networks with Multiple Objectives,” IEEE Trans. on Parallel andDistributed Systems, pp. 1139-1149, October 2002.

56. R. Karri, B. Iyer and I. Koren, “Phantom Redundancy: A Register Transfer Level Tech-nique for Gracefully Degradable Data Path Synthesis,” IEEE Trans. on Computer-Aided Design, pp. 877-888, August 2002.

57. O.S. Unsal, I. Koren, C.M. Krishna and C. A. Moritz, “Cool-Fetch: Compiler-EnabledPower-Aware Fetch Throttling,” Computer Architecture Letters, Vol. 1, pp. 6-9, July2002.

58. D.S. Phatak, T. Goff and I. Koren, “Constant-time Addition and Simultaneous FormatConversion Based on Redundant Binary Representations,” IEEE Trans. on Comput-ers, pp. 1267-1278, Nov. 2001.

59. G. Durairaj, I. Koren and C.M. Krishna, “Importance Sampling to Evaluate Real-TimeSystem Reliability: A Case Study,” Simulation, vol. 76, no. 3, pp. 172-183, March2001.

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60. I. Koren and P. Kornerup (Guest Editors), “Introduction - Special Issue on ComputerArithmetic,” IEEE Trans. on Computers, Vol. 49, pp. 625-627, July 2000.

61. I. Koren and Z. Koren, “Incorporating Yield Enhancement into the FloorplanningProcess,” IEEE Trans. on Computers, Special Issue on Defect Tolerance in DigitalSystems, Vol. 49, pp. 532-541, June 2000.

62. J. Haines, V.R. Lakamraju, I. Koren and C.M. Krishna, “Application-Level FaultTolerance as a Complement to System-Level Fault Tolerance,” The Journal of Super-computing, Special Issue on “Embedded Fault-Tolerant Computing Systems,” Vol. 16,pp. 53-68, Kluwer Academic Publishers, MA, 2000.

63. K. Yu, K. Toutireddy, I. Koren and C.M. Krishna, “Introduction to a Fault-TolerantDistributed Real-Time System Simulator,” Intern. Journal of Modeling and Simula-tion, Vol. 19, No. 1, pp. 7-10, 1999.

64. D. H. Albonesi and I. Koren, “STATS: A Framework for Microprocessor and System-Level Design Space Exploration,” Journal of System Architecture, Vol. 45, pp. 1097-1110, 1999.

65. I. Koren and Z. Koren, “Defect Tolerant VLSI Circuits: Techniques and Yield Analy-sis,” Proceedings of the IEEE, Vol. 86, pp. 1817-1836, Sept. 1998.

66. Z. Chen and I. Koren, “Three Layer Routing for Reliability Enhancement,” Interna-tional Journal on Microelectronics Systems Integration, Vol 5, No 4, pp. 209-219, Dec.1997.

67. Z. Koren and I. Koren, “On the Effect of Floorplanning on the Yield of Large AreaIntegrated Circuits,” IEEE Trans. on VLSI Systems, Vol. 5, pp. 3-14, March 1997.

68. D. H. Albonesi and I. Koren, “A Mean Value Analysis Multiprocessor Model Incor-porating Superscaler Processors and Latency Tolerating Techniques,” InternationalJournal of Parallel Programming, Vol. 24, Number 3, pp. 235-263, 1996.

69. I. A. Wagner and I. Koren, “An Interactive VLSI CAD Tool for Yield Estimation,”IEEE Trans. on Semiconductor Manufacturing, Vol. 8, Special Issue on Defect, Fault,and Yield Modeling, pp. 130-138, May 1995.

70. V.K.R. Chiluvuri and I. Koren, “Layout Synthesis Techniques for Yield Enhancement,”IEEE Trans. on Semiconductor Manufacturing, Vol. 8, Special Issue on Defect, Fault,and Yield Modeling, pp. 178-187, May 1995.2

71. D.S. Phatak and I. Koren, “Complete and Partial Fault Tolerance of FeedforwardNeural Nets,” IEEE Trans. on Neural Nets, Vol. 6, pp. 446-456, March 1995.

72. R. Leveugle, Z. Koren, I. Koren, G. Saucier and N. Wehn, “The HYETI Defect TolerantMicroprocessor: A Practical Experiment and a Cost-Effectiveness Analysis,” IEEETrans. on Computers, Vol. 43, pp. 1398-1406, Dec. 1994.

73. D.S. Phatak and I. Koren, “Connectivity and Performance Tradeoffs in the CascadeCorrelation Learning Architecture,” IEEE Trans. on Neural Nets, Vol. 5, pp. 930-935,Nov. 1994.

74. D.S. Phatak and I. Koren, “Hybrid Signed-Digit Number Systems: A Unified Frame-work for Redundant Number Representations with Bounded Carry PropagationChains,” IEEE Trans. on Computers, Special Issue on Computer Arithmetic, Vol.43, pp. 880-891, August 1994.

75. K. Yu, I. Koren and Y. Guo, “Generalized Multistate Monotone Coherent Systems,”IEEE Trans. on Reliability, Vol. 43, pp. 242-250, June 1994.

2Won the 1995 Best Paper Award of the IEEE Trans. on Semiconductor Manufacturing.

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76. I. Koren, Z. Koren and C.H. Stapper, “A Statistical Study of Defect Maps of LargeArea VLSI ICs,” IEEE Trans. on VLSI Systems, Vol. 2, pp. 249-256, June 1994.

77. I. Koren, Z. Koren and C.H. Stapper, “A Unified Negative Binomial Distribution forYield Analysis of Defect Tolerant Circuits,” IEEE Trans. on Computers, Vol. 42, pp.724-734, June 1993.1

78. D.S. Phatak, H. Choi and I. Koren, “Construction of Minimal n-2-n Encoders for anyn,” Neural Computation, no. 5, pp. 783-794, 1993.

79. S. Wimer, I. Koren and I. Cederbaum, “On Paths with the Shortest Average ArcLength in Weighted Graphs,” Discrete Applied Math., Vol. 45, pp. 169-179, 1993.

80. I. Cederbaum, I. Koren and S. Wimer, “Balanced Block Spacing for VLSI Layout,”Discrete Applied Mathematics, Vol. 40, Special Issue on “Graphs and Electrical Engi-neering,” pp. 303-318, 1992.

81. B. Mendelson and I. Koren, “Estimating the Potential Parallelism and Pipelining ofAlgorithms for Data Flow Machines,” Journal of Parallel and Distributed Computing,Vol. 14, pp. 15-28, Jan. 1992.

82. I. Koren and Z. Koren, “Discrete and Continuous Models for the Performance of Re-configurable Multistage Systems,” pp. 1024-1033, IEEE Trans. on Computers, Vol.40, Sept. 1991.

83. D. Sitaram, I. Koren and C.M. Krishna, “A Random, Distributed Algorithm to Em-bed Trees in Partially Faulty Processor Arrays,” Journal of Parallel and DistributedComputing, Vol. 12, pp. 1-11, May 1991.

84. I. Koren and O. Zinaty, “Evaluating Elementary Functions in a Numerical Co-ProcessorBased on Rational Approximations,” IEEE Trans. on Computers, Special Issue onComputer Arithmetic, Vol. 39, pp. 1030-1037, August 1990.

85. I. Koren and A.D. Singh, “Fault Tolerance in VLSI Circuits,” Computer, Special Issueon Fault-Tolerant Systems, Vol. 23, pp. 73-83, July 1990.1

86. I. Koren and D.K. Pradhan, “Comment on – Nonplanar VLSI Arrays with High Fault-Tolerance Capabilities,” IEEE Trans. on Reliability, Vol. 38, pp. 527, 532, Dec. 1989.

87. I. Koren and C.H. Stapper (Guest Editors), “Introduction - Special Section on High-Yield VLSI Systems,” IEEE Trans. on Computers, Vol. 38, pp. 481-482, April 1989.

88. I. Koren and Z. Koren, “On Gracefully Degrading Multi-processors with Multi-stageInterconnection Networks,” IEEE Trans. on Reliability, Special Issue on “Reliabilityof Parallel and Distributed Computing Networks,” Vol. 38, pp. 82-89, April 1989.

89. S. Wimer, I. Koren and I. Cederbaum, “Optimal Aspect Ratios of Building Blocks inVLSI,” IEEE Trans. on Computer-Aided Design, Vol. 8, pp. 139-145, Feb. 1989.

90. P. Erdos, I. Koren, S. Moran, G.M. Silberman and S. Zaks, “Minimum– DiameterCyclic Arrangements in Mapping Data–Flow Graphs onto VLSI Arrays,” MathematicalSystems Theory, Vol. 21, No. 2, pp. 85-98, 1988.

91. I. Koren, B. Mendelson, I. Peled and G.M. Silberman, “A Data-Driven VLSI Array forArbitrary Algorithms,” Computer, Vol. 21, pp. 30-43, October 1988.

92. I. Koren, Z. Koren and D.K. Pradhan, “Designing Interconnection Buses in VLSI andWSI for Maximum Yield and Minimum Delay,” IEEE Journal of Solid-state Circuits,Vol. 23, pp. 859-866, June 1988.

93. S. Wimer, I. Koren and I. Cederbaum, “Floorplans, Planar Graphs and Layouts,”IEEE Trans. on Circuits and Systems, Special Issue on “Computational Graph Theory:Algorithms and Applications,” Vol. 35, pp. 267-278, March 1988.

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94. S. Wimer and I. Koren, “Analysis of Strategies for Constructive General Block Place-ment,” IEEE Trans. on Computer-Aided Design, Vol. 7, pp. 371-377, March 1988.

95. M. Granski, I. Koren, and G.M. Silberman, “The Effect of Operations Scheduling onthe Performance of Data Flow Computers,” IEEE Trans. on Computers, Vol. C-36,pp. 1019-1029, Sept. 1987.

96. M. Berg and I. Koren, “On Switching Policies for Modular Fault–Tolerant ComputingSystems,” IEEE Trans. on Computers, Vol. C-36, pp. 1052-1062, Sept. 1987.

97. I. Koren and I. Peled, “The Concept and Implementation of Data-Driven ProcessorArrays,” Computer, Vol. 20, pp.102-103, July 1987.

98. I. Koren and D. Pradhan, “Modeling the Effect of Redundancy on Yield and Perfor-mance of VLSI Systems,” IEEE Trans. on Comp., Vol. C-36, pp. 344-355, Mar. 1987.1

99. D. Gordon, I. Koren and G.M. Silberman, “Restructuring Hexagonal Arrays of Pro-cessors in the Presence of Faults,” Journal of VLSI and Computer Systems, Vol. 2,No. 1, pp. 23-35, 1987.

100. I. Koren, Z. Koren and S.Y.H. Su, “Analysis of a Class of Recovery Procedures,” IEEETrans. on Computers, Vol. C-35, pp. 703–712, August 1986.

101. I. Koren and D.K. Pradhan, “Yield and Performance Enhancement Through Redun-dancy in VLSI and WSI Multi–processor Systems,” Proc. of IEEE, Special Issue onFault–Tolerance in VLSI, Vol. 74, No. 5, pp. 699–711, May 1986.

102. I. Koren, “Comments on – The Diogenes Approach to Testable Fault– Tolerant Arraysof Processors,” IEEE Trans. on Computers, Vol. C–35, p. 93, January 1986.

103. I. Koren and M.A. Breuer, “On Area and Yield Considerations for Fault–TolerantVLSI Processor Arrays,” IEEE Trans. on Comp., Vol. C–33, pp. 21-27, Jan. 1984.1

104. D. Gordon, I. Koren and G.M. Silberman, “Embedding Tree Structures in VLSI Hexag-onal Arrays,” IEEE Trans. on Computers, Vol. C-33, pp. 104–107, Jan. 1984.

105. I. Koren and E. Shalev, “Reliability Analysis of Hybrid Redundancy Systems,” IEEProc., Computer and Digital Techniques, Vol. 131, No. 1, pp. 31–36, January 1984.

106. I. Koren and Y. Maliniak, “On Classes of Positive, Negative and Imaginary RadixNumber Systems,” IEEE Trans. on Computers, Vol. C–30, pp. 312–317, May 1981.

107. I. Koren and E. Sadeh, “A New Approach to the Evaluation of the Reliability of DigitalSystems,” IEEE Trans. on Computers, Vol. C–29, pp. 261–267, March 1980.

108. I. Koren and E. Sadeh, “On the Convergence of the Signal Reliability of Iterative andSequential Systems,” Digital Processes, 6, pp. 21–33, 1980.

109. I. Koren and S.Y.H. Su, “Reliability Analysis of N–Modular Systems with Intermittentand Permanent Faults,” IEEE Trans. on Comp., Vol. C–28, pp. 514–520, July 1979.

110. I. Koren, “Analysis of the Signal Reliability Measure and an Evaluation Procedure,”IEEE Trans. on Computers, Vol. C–28, pp. 244–249, March 1979.

111. I. Koren and Z. Kohavi, “On the Properties of Sensitized Paths,” IEEE Trans. onComputers, Vol. C–28, pp. 268–269, March 1979.

112. S.Y.H. Su, I. Koren and Y.K. Malaiya, “A Continuous Parameter Markov Model andDetection Procedures for Intermittent Faults,” IEEE Trans. on Computers, Vol. C–27,pp. 567–570, June 1978.

113. I. Koren and Z. Kohavi, “Diagnosis of Intermittent Faults in Combinational Networks,”IEEE Trans. on Computers, Vol.C–26, pp. 1154–1158, Nov. 1977.

114. I. Koren and Z. Kohavi, “Sequential Fault Diagnosis in Combinational Networks,”IEEE Trans. on Computers, Vol. C–26, pp. 334–342, April 1977.

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115. I. Koren and Z. Kohavi, “Adaptive Fault Locating Tests for Digital Systems,” DigitalProcesses, 2, 3, pp. 209–223, 1976.

Refereed Conference Papers

116. G. Chapman, I. Koren, Z. Koren, P. Pourbakht and P. Le, ”Exploring Soft Errors(SEUs) with Digital Imager Pixels ranging from 7 to 1.2um,” to appear, Proc. of the2017 IEEE Internl. Symp. on Defect and Fault Tolerance in VLSI & NanotechnologySystems, 4 pp, Oct. 2017.

117. D. Oliveira, L. Pilla, N. Bardeleben, S. Blanchard, H. Quinn, I. Koren P. Navaux andP. Rech, “Experimental and Analytical Study of Xeon Phis Reliability,” to appear,Proc. of the IEEE/ACM Intern. Conf. on High Performance Computing, (SC’15),Nov. 2017.

118. F. Moreira, M. Diener, P. Navaux and I. Koren, “Data Mining the Memory AccessStream to Detect Anomalous Application Behavior,” Proc. of the 2017 ACM Intern.Conf. on Computing Frontiers, pp. 45-52, May 2017.

119. D. Oliveira, V. F. Netto, P. Navaux, I. Koren and P. Rech, “CAROL-FI: An efficientFault-Injection Tool for Vulnerability Evaluation of Modern HPC Parallel Accelera-tors,” Proc. of the 2017 ACM Intern. Conf. on Computing Frontiers, pp. 295-298,May 2017.

120. Keynote, “Detecting and Counteracting Benign and Malicious Faults (Attacks) in Em-bedded Systems,” RESCUE 2017 - Workshop on Reliability, Security and Quality, 22ndIEEE European Test Symposium, May 2017.

121. G. Chapman, R. Thomas, R. Thomas, I. Koren and Z. Koren, ”Experimental Study andAnalysis of Soft and Permanent Errors in Digital Cameras,” Proc. of the 2016 IEEEInternl. Symp. on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, 4pp, Sept. 2016.

122. D. Oliveira, L. Pilla, F. Fernandes, C. Lunardi, I. Koren, P. Navaux, L. Carro and P.Rech, ”Input Size Effects on the Radiation-Sensitivity of Modern Parallel Processors,”Proc. of the Radiation Effects Data workshop, 6 pp., July 2016.

123. S. Wimer and I. Koren, “Energy Efficient Deeply Fused Dot-Product MultiplicationArchitecture,” Proc. of ASAP’16 - the Internl. Conf. on Application-Specific Systems,Architectures and Processors, pp. 115-122, July 2016.

124. S. Xu, I. Koren and C. Krishna, “Thermal-Aware Task Allocation and Scheduling forHeterogeneous Multi-Core Cyber-Physical Systems,” Proc. of the Internl. Conf. onEmbedded Systems and Cyber-physical Systems (ESCS’16), 6pp., July 2016.

125. G. Chapman, R. Thomas, R. Thomas, K. Meneses, T. Yang, I. Koren and Z. Koren,“Increases in Hot Pixel Development Rates for Small Digital Pixel Sizes,” Proc. of the2016 Symposium on Electronic Imaging, 5 pp., Feb. 2016.

126. S. Xu, I. Koren and C. Krishna, “Improving Processor Lifespan and Energy Consump-tion Using DVFS Based on ILP Monitoring,” Proc. of the Workshop on Low-PowerDependable Computing (LPDC 2015), 6 pp., Dec. 2015.

127. S. Srinivasan, I. Koren, S. Kundu, ”Online Mechanism for Reliability and Power-Efficiency Management of a Dynamically Reconfigurable Core,” Proc. of the 33rdIEEE Conferencg on Computer Design (ICCD 2015), pp. 356-363, Oct. 2015.

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128. G. Chapman, R. Thomas, R. Thomas, K. Meneses, T. Yang, I. Koren and Z. Koren,”Single Event Upsets and Hot Pixels in Digital Imagers,” Proc. of the 2015 IEEEIntern. Symp. on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, pp1-10., Oct. 2015.

129. G. Chapman, R. Thomas, R. Thomas, I. Koren and Z. Koren, “Enhanced CorrectionMethods for High Density Hot Pixel defects in Digital Imagers,” Proc. of the 27thSPIE Electronic Imaging Symp., Vol. 9403, 10 pp, Mar. 2015.

130. G. Chapman, R. Thomas, R. Thomas, I. Koren and Z. Koren, “Improved Correctionfor Hot Pixels in Digital Imagers,” Proc. of the 2014 IEEE Intern. Symp. on Defectand Fault Tolerance in VLSI & Nanotechnology Systems, pp. 116-121, Oct. 2014.

131. F. Moreira, M. Alves, M. Diener, P. Navaux and I. Koren, “Profiling and Optimiz-ing Micro-Architecture Bottlenecks at the Hardware Level,” Proc. of the 26th In-ternational Symposium on Computer Architecture and High Performance Computing(SBAC-PAD), 8 pp., Oct. 2014.

132. S. Srinivasan, N. Kurella, I. Koren, S. Kundu and R. Rodrigues, ”A Runtime Sup-port Mechanism for Fast Mode Switching of a Self-Morphing Core for Power Effi-ciency,” Proc. of the 2014 Conf. on Parallel Architectures and Compilation Techniques(PACT’14), pp. 491-492, Aug. 2014.

133. R. Rodrigues, A. Annamalai, I. Koren and S. Kundu, “Reducing Energy per Instructionvia Dynamic Resource Allocation and Voltage and Frequency Adaptation in Asymmet-ric Multicores,” IEEE Symposium on VLSI (ISVLSI), pp. 436-441, July 2014.

134. R. Rodrigues, I. Koren and S. Kundu, “Performance and Power Benefits of SharingExecution Units between a High Performance Core and a Low Power Core,” Proc. ofthe International IEEE Conference on VLSI Design, pp. 204-209, Jan. 2014.

135. P. Maistri, S. Tiran, P. Maurine, I. Koren, and R. Leveugle, “Countermeasures againstEM Analysis for a Secured FPGA-based AES Implementation,” Proc. of the Inter-national Conference on ReConfigurable Computing and FPGAS (ReConfig 2013), pp.1-6, Dec. 2013.

136. G. Chapman, R. Thomas, I. Koren and Z. Koren, “Improved Image Accuracy in HotPixel Degraded Digital Cameras,” Proc. of the 2013 IEEE Intern. Symp. on Defectand Fault Tolerance in VLSI & Nanotechnology Systems, pp. 172-177, Oct. 2013.

137. S. Srinivasan, R. Rodrigues, A. Annamalai, I. Koren and S. Kundu, “On DynamicPolymorphing of a Superscalar Core for Improving Energy Efficiency,” Proc. of the31st IEEE Conference on Computer Design (ICCD 2013), pp. 495-499, Oct. 2013.

138. A. Annamalai, R. Rodrigues, I. Koren and S. Kundu,“An Opportunistic Prediction-based Thread Scheduling to Maximize Throughput/Watt in AMPs,” Proc. of the 2013Conf. on Parallel Architectures and Compilation Techniques (PACT’13), pp. 63-72,Oct. 2013.

139. S. Srinivasan, R. Rodrigues, A. Annamalai, I. Koren and S. Kundu, “A study onPolymorphing Superscalar Processor Dynamically to Improve Power Efficiency,” IEEESymposium on VLSI (ISVLSI), pp. 46-51, Aug. 2013.

140. P. Maistri, S. Tiran, P. Maurine, I. Koren and R. Leveugle, “An Evaluation of anAES Implementation Protected against EM Analysis,” Proc. of the 23rd GLSVLSIconference, pp. 317-318, May 2013.

141. G. Chapman, R. Thomas, Z. Koren and I. Koren, “Empirical Formula for Rates ofHot Pixel Defects based on Pixel Size, Sensor Area, and ISO,” Proc. of the 25th SPIEElectronic Imaging Symp., Vol. 8659, pp. C1-C11, Feb. 2013.

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142. C.M. Krishna and I. Koren, “Adaptive Fault-Tolerance for Cyber-Physical Systems,”Proc. of ICNC 2013 International Workshop on Cyber-Physical System and Its Com-puting and Networking Design, 5 pp., January 2013.

143. R. Rodrigues, A. Annamalai, I. Koren and S. Kundu, “Scalable Thread Scheduling inAsymmetric Multicores for Power Efficiency,” Proc. of the 24th International Sympo-sium on Computer Architecture and High Performance Computing (SBAC-PAD), pp.59-66, October 2012.

144. R. Rodrigues, I. Koren and S. Kundu, “A Mechanism to Verify Cache CoherenceTransactions in Multicore Systems,” Proc. of the 2012 IEEE Intern. Symp. on Defectand Fault Tolerance in VLSI & Nanotechnology Systems, pp. 211-216, Oct. 2012.

145. G. Chapman, R. Thomas, Z. Koren and I. Koren, “Relating digital imager defect ratesto pixel size, sensor area and ISO,” Proc. of the 2012 IEEE Intern. Symp. on Defectand Fault Tolerance in VLSI & Nanotechnology Systems, pp. 164-169, Oct. 2012.

146. Y. Xu, I. Koren and C.M. Krishna, “A Study of the Impact of Computational Delays inMissile Interception Systems,” 9th International Conference on Informatics in Control,Automation and Robotics (ICINCO), pp. 585-588, July 2012.

147. A. Jain, C.M. Krishna, I. Koren and Z. Koren, “Cost Functions for Scheduling Tasksin Cyber-Physical Systems,” 9th International Conference on Informatics in Control,Automation and Robotics (ICINCO), pp. 412-421, July 2012.

148. H. Wang, I. Koren and C.M. Krishna, “Runtime Architecture Adaptation for EnergyManagement in Embedded Real-Time Systems,” 3rd IEEE International Green Com-puting Conference (IGCC’12), pp. 1-9, June 2012.

149. A. Annamalai, R. Rodrigues, I. Koren and S. Kundu, “Dynamic Thread Scheduling inAsymmetric Multicores to Maximize Performance-per-Watt,” 8th Workshop on High-Performance, Power-Aware Computing (HPPAC/IPDPS), pp. 958-965, May 2012.

150. G. Chapman, J. Leung, R. Thomas, A. Namburete, Z. Koren and I. Koren, “Projectingthe rate of in-field pixel defects based on pixel size, sensor area, and ISO,” Proc. ofthe 24nd SPIE Electronic Imaging Symp., Vol. 8298, pp. 82980E1-11, Jan. 2012.

151. M. U. Khan, P. Narayanan, P. Vijayakumar, I. Koren, C. M. Krishna and C. A. Moritz,“Biased Voting for Improved Yield in Nanoscale Fabrics,” Proc. of the 2011 IEEEIntern. Symp. on Defect and Fault Tolerance in VLSI & Nanotechnology Systems, pp.79-85, Oct. 2011.

152. G. Chapman, J. Leung, A. Namburete, Z. Koren and I. Koren, “Predicting pixel defectrates based on image sensor parameters,” Proc. of the 2011 IEEE Symp. on Defectand Fault Tolerance in VLSI & Nanotechnology Systems, pp. 408-416, Oct. 2011.

153. R. Rodrigues, I. Koren and S. Kundu, “An Architecture to enable Life Cycle Testingof CMPs,” Proc. of the 2011 IEEE Intern. Symp. on Defect and Fault Tolerance inVLSI & Nanotechnology Systems, pp. 341-348, Oct. 2011.

154. A. Annamalai, R. Rodrigues, I. Koren, S. Kundu and O. Khan, “Performance perWatt Benefits of Dynamic Core Morphing in Asymmetric Multicores,” Proc. of the2011 Conf. on Parallel Architectures and Compilation Techniques (PACT’11), pp.121-130, Oct. 2011.

155. P. Panchapakeshan, P. Vijayakumar, P. Narayanan, C-O. Chui, I. Koren and C. A.Moritz, “3-D Integration Requirements of Hybrid Nanoscale-CMOS Fabrics,” Proc. of2011 IEEE NANO Conference, August 2011.

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156. A. Barenghi, C. Hocquet, D. Bol, F-X. Standaert, F. Regazzoni and I. Koren, “Ex-ploring the Feasibility of Low Cost Fault Injection Attacks on Sub-Threshold Devicesthrough an example of a 65nm AES implementation,” Proc. of the 7th Workshop ofRFID Security and Privacy, pp. 48-60, June 2011.

157. P. Vijayakumar, P. Narayanan, I. Koren, C. M. Krishna and C. A. Moritz, “Impactof Nanomanufacturing Flow on Systematic Yield Losses in Nanoscale Fabrics,” Proc.of the IEEE/ACM Intern. Symp. on NanoScale Architectures (NanoArch’11), pp.181-188, June 2011.

158. P. Narayanan, J. Kina, P. Panchapakeshan, P. Vijayakumar, K-S. Shin, M. Rahman,M. Leuchtenburg, I. Koren, C-O. Chui and C. A. Moritz, “Nanoscale ApplicationSpecific Integrated Circuits,” Proc. of the IEEE/ACM Intern. Symp. on NanoScaleArchitectures (NanoArch’11), pp. 99-106, June 2011.

159. G. Chapman, J. Leung, R. Thomas, Z. Koren, and I. Koren, “Tradeoffs in ImagerDesign Parameters for Sensor Reliability,” Proc. of the 23nd SPIE Electronic ImagingSymp., vol. 7875, pp. 78750I1-12, Jan. 2011.

160. S. Wimer, I. Koren and I. Cohen, “Adaptive Clock Gating for Shift Register BasedCircuits,” Proc. of the 26-th IEEE Convention of Electrical and Electronics Engineersin Israel, pp. 374-378, Nov. 2010.

161. A. Barenghi, G. Pelosi, L. Breveglieri, I. Koren and F. Regazzoni, “Low-cost SoftwareCountermeasures Against Fault Attacks: Implementation and Performances Tradeoffs,” Proc. of the 5th workshop on Embedded Security, WESS’2010, pp. 7.1-7.10,Oct. 2010.

162. A. Das, R. Rodrigues, I. Koren, and S. Kundu, “A Study on the Performance Benefitsof Core Morphing in an Asymmetric Multicore Processor,” Proc. of the IEEE Internl.Conference on Computer Design, ICCD’10, pp. 17-22, Oct. 2010.

163. P. Vijayakumar, P. Narayanan, I. Koren, C.M. Krishna and C. A. Moritz, “Incorpo-rating Heterogeneous Redundancy in a Nanoprocessor for Improved Yield and Perfor-mance,” Proc. of the 2010 IEEE Intern. Symp. on Defect and Fault Tolerance inVLSI Systems, pp. 273-279, Oct. 2010.

164. G. Chapman, J. Leung, I. Koren, and Z. Koren, “Tradeoffs in Imager Design withrespect to Pixel Defect Rates,” Proc. of the 2010 IEEE Intern. Symp. on Defect andFault Tolerance in VLSI Systems, pp. 231-239, Oct. 2010.

165. P. Shabadi, A. Khitun, P. Narayanan, M. Bao, I. Koren, K. L. Wang and C. A. Moritz,“Towards Logic Functions as the Device,” Proc. of the IEEE/ACM Intern. Symp. onNanoScale Architectures (NanoArch’10), pp. 11-16, June 2010.

166. J. Leung, G. Chapman, Y. Choi, R. Thomas, I. Koren, and Z. Koren, “Analyzing theImpact of ISO on Digital Imager Defects with an Automated Defect Trace Algorithm,”Proc. of the 22nd SPIE Electronic Imaging Symp., vol. 7536, pp. 75360F1-F12, Jan.2010.

167. J. Leung, G. Chapman, I. Koren, and Z. Koren, “Characterization of Gain EnhancedIn-Field Defects in Digital Imagers,” Proc. of the 2009 IEEE Intern. Symp. on Defectand Fault Tolerance in VLSI Systems, pp. 155-163, Oct. 2009.

168. J. Leung, G. Chapman, I. Koren, and Z. Koren, “Statistical Identification and Analysisof Defect Development in Digital Imagers,” Proc. of the 21th SPIE Electronic ImagingSymp., vol. 7250, pp. 7250W1-W12, Jan. 2009.

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169. F. Regazzoni, T. Eisenbarth, L. Breveglieri, P. Ienne, and I. Koren, “Can KnowledgeRegarding the Presence of Countermeasures Against Fault Attacks Simplify PowerAttacks on Cryptographic Devices?” Proc. of the 2008 IEEE Intern. Symp. on Defectand Fault Tolerance in VLSI Systems, pp. 202-210, Oct. 2008.

170. J. Leung, G. Chapman, I. Koren, and Z. Koren, “Automatic Detection of In-fieldDefect Growth in Image Sensors,” Proc. of the 2008 IEEE Intern. Symp. on Defectand Fault Tolerance in VLSI Systems, pp. 220-228, Oct. 2008.

171. H. Wang, I. Koren and C. M. Krishna, “An Adaptive Resource Partitioning Algo-rithm for SMT Processors,” Proc. of the 2008 Conf. on Parallel Architectures andCompilation Techniques (PACT’08), pp. 230-239, October 2008.

172. J. Leung, J. Dudas, G. Chapman, I. Koren, and Z. Koren, “Characterization of pixeldefect development during digital imager lifetime,” Proc. of the 20th SPIE ElectronicImaging Symp., vol. 6816, pp. 68160A1-A12, Jan. 2008.

173. F. Regazzoni, T. Eisenbarth, J. Groszschaedl, L. Breveglieri, P. Ienne, I. Koren andC. Paar, “Power Attacks Resistance of Cryptographic S-boxes in presence of ErrorDetection Procedures,” Proc. of the 2007 IEEE Intern. Symp. on Defect and FaultTolerance in VLSI Systems, pp. 508-516, Sept. 2007.

174. J. Leung, J. Dudas, G. Chapman, I. Koren, and Z. Koren, “Quantitative Analysis ofIn-Field Defects in Image Sensor Arrays,” Proc. of the 2007 IEEE Intern. Symp. onDefect and Fault Tolerance in VLSI Systems, pp. 526-534, Sept. 2007.

175. G. Agosta, L. Breveglieri, G. Pelosi and I. Koren, “Countermeasures Against BranchTarget Buffer Attacks,” Proc. of FDTC 2007 - Fault Diagnosis and Tolerance inCryptography, pp. 75-79, Sept. 2007.

176. M. Gregoire and I. Koren, “An Adaptive Algorithm for Fault Tolerant Re-Routing inWireless Sensor Networks,” Proc. of PWN 2007 - Third IEEE PerCom Workshop onPervasive Wireless Networking, pp. 542-547, March 2007.

177. J. Dudas, L. Wu, C. Jung, G. Chapman, Z. Koren and I. Koren, “Identification of in-field Defect Development in Digital Image Sensors,” Proc. of the 19th SPIE ElectronicImaging Symp., Vol. 6502, pp. 65020Y1-12, Jan. 2007.

178. L. Breveglieri, I. Koren and P. Maistri, “A Fault Attack Against the FOX Cipher Fam-ily,” Proc. of FDTC 2006 - Fault Diagnosis and Tolerance in Cryptography, LectureNotes in Computer Science, Vol. 4236, pp. 98–105, Springer-Verlag, Oct. 2006.

179. J. Dudas, C. Jung, L. Wu, G. Chapman, I. Koren and Z. Koren, “On-Line Mapping ofIn-Field Defects in Image Sensor Arrays,” Proc. of the 2006 IEEE Intern. Symp. onDefect and Fault Tolerance in VLSI Systems, pp. 439-447, Oct. 2006.

180. H. Adamyan, H. Mkrtchyan and I. Koren, “Computing Critical Area for VLSI Layouts:Analysis Techniques and Tools,” Invited paper, Proc. of the 23rd VLSI MultilevelInterconnection (VMIC) Conf., pp. 10.B.1-10.B.8, Sept. 2006.

181. A. Bekkerman, V. Lakamraju, I. Koren and C.M. Krishna, “Testing and Validation ofthe CASA DCAs System,” Proc. of the 2006 IEEE International Geoscience & RemoteSensing Symp. (IGARSS), pp. 1902-1906, Aug. 2006.

182. Y. Zhou, V. Lakamraju, I. Koren and C.M. Krishna, “Software-Based Adaptive andConcurrent Self-Testing in Programmable Network Interfaces,” Proc. of ICPADS’06 -12th Intern. Conf. on Parallel and Distributed Systems, pp. 525-532, July 2006.

183. Y. Han, I. Koren and C. M. Krishna, “Temptor: A Lightweight Runtime TemperatureMonitoring Tool Using Performance Counters,” Proc. of the 3rd Temperature AwareComputer Systems Workshop, ISCA-2006, June 2006.

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184. G. Ellis, S. Wodin-Schwartz, B. Andam, I. Koren, C. M. Krishna and C. A. Moritz,“Integration of Low-Power Digital Circuitry into Undergraduate Curricula,” Proc. ofASEE’06 - American Society for Engineering Eduction Conference, pp. 874.1-874.6,June 2006.

185. L. Breveglieri, I. Koren and P. Maistri, “A Note on Error Detection in an RSA Ar-chitecture by means of Residue Codes,” Proc. of IOLTS06, pp. 176-177, July 2006.

186. V. Lakamraju, I. Koren and C.M. Krishna, “ RAPIDS 4.0: A Simulation/EmulationTool for Dependability Analysis,” pp. 253-259, Proc. of HPC’2006, April 2006.

187. H. Wang, Y. Guo, I. Koren and C. M. Krishna, “Compiler-Based Adaptive FetchThrottling for Energy Efficiency,” Proc. of ISPASS’06 - IEEE International Symp. onPerformance Analysis of Systems and Software, pp. 112-119, Mar. 2006.

188. J. Dudas, C. Jung, G. Chapman, I. Koren and Z. Koren, “Robust Detection of Defectsin Imaging Arrays,” Proc. of the 18th SPIE Electronic Imaging Symp., Vol. 6059, pp.60590X1-12, Jan. 2006.

189. L. Breveglieri, I. Koren and P. Maistri, “Incorporating Error Detection and OnlineReconfiguration into a Regular Architecture for the Advanced Encryption Standard,”Proc. of the 2005 IEEE Intern. Symp. on Defect and Fault Tolerance in VLSI Systems,pp. 72-80, Oct. 2005.

190. Z. Wo, I. Koren and M. Ciesielski, “An ILP Formulation for Yield-driven Architecturalsynthesis,” Proc. of the 2005 IEEE Intern. Symp. on Defect and Fault Tolerance inVLSI Systems, pp. 12-20, Oct. 2005.

191. G. Chapman, I. Koren, Z. Koren, J. Dudas and C. Jung, “On-Line Fault Identificationin Fault-Tolerant Imagers,” Proc. of the 2005 IEEE Intern. Symp. on Defect andFault Tolerance in VLSI Systems, pp. 149-157, Oct. 2005.

192. A. Goel, I. Koren and C. M. Krishna, “Energy Aware Kernel for Hard Real-TimeSystems,” Proc. of the IEEE Conf. on Compilers, Architectures for Embedded Systems- CASES 2005, pp. 185-190, Sept. 2005.

193. L. Breveglieri, I. Koren, P. Maistri and M. Ravasio, “Incorporating Error Detectionin an RSA Architecture,” Proc. of FDTC 2005 - Fault Diagnosis and Tolerance inCryptography, August 2005. Also appears in Lecture Notes in Computer Science, Vol.4236, pp. 71–79, Springer-Verlag, Oct. 2006.

194. Z. Wo and I. Koren, “Synthesis of Saturating Counters Using Traditional and Non-traditional Basic Counters,” Proc. of the 17th IEEE Symp. on Computer Arithmetic,pp. 114-121, June 2005.

195. Y. Han, I. Koren and C. A. Moritz, “Temperature Aware Floorplanning,” Proc. of the2nd Temperature Aware Computer Systems Workshop, ISCA-2005, pp. 37-45, June2005.

196. Z. Wo and I. Koren, “Technology Mapping for Reliability Enhancement in Logic Syn-thesis,” Proc. of the International Symp. on Quality of Electronic Design (ISQED’05),pp. 137-142, March 2005.

197. Z. Wo and I. Koren, “Effective Analytical Delay Model for Transistor Sizing,” Proc.of the ASP-DAC 2005 Conf., pp. 387-392, Jan. 2005.

198. Y. Guo, S. Chheda, I. Koren, C. M. Krishna, and C. A. Moritz, “Energy-Aware DataPrefetching for General-Purpose Programs,” Proc. of PACS’04 Workshop on Power-Aware Computer Systems, Micro-37, pp. 51-59, Dec. 2004. Also in Lecture Notes inComputer Science: Power Aware Computer Systems, Vol. 3471, pp. 78-94, 2005.

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199. Y. Guo, S. Chheda, I. Koren, C. M. Krishna, and C. A. Moritz, “Energy Characteri-zation of Hardware-Based Data Prefetching,” Proc. of the IEEE Internl. Conferenceon Computer Design, ICCD’04, pp. 518-523, Oct. 2004.

200. G. Bertoni, L. Breveglieri, I. Koren and P. Maistri, “An Efficient Hardware-Based FaultDiagnosis Scheme for AES: Performances and Cost,” Proc. of the 2004 IEEE Intern.Symp. on Defect and Fault Tolerance in VLSI Systems, pp. 130-138, Oct. 2004.

201. A. Maheshwari, I. Koren and W. Burleson, “Accurate Estimation of Soft Error Rate(SER) in VLSI Circuits,” Proc. of the 2004 IEEE International Symp. on Defect andFault Tolerance in VLSI Systems, pp. 377-385, October 2004.

202. L. Breveglieri, I. Koren and P. Maistri, “Detecting Faults in Four Symmetric Key BlockCiphers,” Proc. of ASAP’04 - the Internl. Conf. on Application-Specific Systems,Architectures and Processors, pp. 258-268, Sept. 2004.

203. L. Breveglieri, I. Koren and P. Maistri, “Detecting Faults in Integer and Finite FieldArithmetic Operations for Cryptography,” Proc. of FDTC 2004 - Fault Diagnosis andTolerance in Cryptography, DSN’04, pp. 361-367, June 2004.

204. O. S. Unsal, I. Koren, C.M. Krishna, C.A. Moritz, “Cool-Fetch: A Compiler-EnabledIPC Estimation Based Framework for Energy Reduction”, Proc. of INTERACT-8organized in conjunction with HPCA-10, February 2004.

205. S. Chheda, O. S. Unsal, I. Koren, C.M. Krishna, C.A. Moritz, “Combining Runtimeand Static IPC Prediction for Energy Efficiency,” Proc. of ACM Computing Frontiers,pp. 240-254, April 2004.

206. E. Ciocca, I. Koren, Z. Koren, C.M. Krishna and D. Katz, “Application-Level FaultTolerance and Detection in the Orbital Thermal Imaging Spectrometer,” Proc. of the10th IEEE Pacific Rim International Symp. Dependable Computing (PRDC 2004),pp. 43-48, March 2004.

207. H. Yang, I. Koren, C.M. Krishna, “Incorporating Application-Level Fault Toleranceand Detection into Radar Angular Super-Resolution,” Proc. of the 10th IEEE PacificRim International Symp. on Dependable Computing (PRDC 2004), pp. S:1-2, March2004.

208. G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, “Detecting and LocatingFaults in VLSI Implementations of the Advanced Encryption Standard,” Proc. of the2003 IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, pp.105-113, November 2003.

209. A. Maheshwari, I. Koren and W. Burleson, “Techniques for Transient Fault SensitivityAnalysis and Reduction in VLSI Circuits,” Proc. of the 2003 IEEE Intern. Symp. onDefect and Fault Tolerance in VLSI Systems, pp. 597-604, Nov. 2003.

210. G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, “Concurrent Fault De-tection in a Hardware Implementation of the RC5 Encryption Algorithm,” Proc. ofASAP’03 - the Internl. Conference on Application-Specific Systems, Architectures andProcessors, pp. 423-432, June 2003.

211. D. Roychowdhury, I. Koren, C.M. Krishna and Y.-H. Lee, “A Voltage SchedulingHeuristic for Real-Time Task Graphs,” Proc. of the Performance and DependabilitySymp. (IPDS), pp. 741-750, June 2003.

212. J. Nair, Z. Koren, I. Koren and C.M. Krishna, “Pre-Processing Input Data to AugmentFault Tolerance in Space Applications,” Proc. of the Performance and DependabilitySymp. (IPDS), pp. 491-500, June 2003.

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213. V. Lakamraju, I. Koren and C.M. Krishna, “Low Overhead Fault Tolerant Networkingin Myrinet,” Proc. of the Dependable Computing and Communication Symp. (DSN),pp. 193-202, June 2003.

214. I. Koren, Y. Koren and B. Oomman, “Saturating counters: Application and DesignAlternatives,” Proc. of the 16th IEEE Symp. on Computer Arithmetic, pp. 228-235,June 2003.

215. G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, “A Parity Code BasedConcurrent Fault Detection for an Implementation of the Advanced Encryption Stan-dard,” Proc. of the 2002 IEEE International Symp. on Defect and Fault Tolerance inVLSI Systems, pp. 51-59, November 2002.

216. E. Ciocca, I. Koren, C.M. Krishna, “Determining Acceptance Tests for Application-Level Fault Detection,” Proc. of the 2nd ASPLOS Workshop on Evaluating and Ar-chitecting System Dependability, pp. 47-53, October 2002.

217. O.S. Unsal, I. Koren and C.M. Krishna, “Towards Energy-Aware Software-Based Fault-Tolerance in Real-Time Systems,” Proc. of the 2002 IEEE International Symp. on LowPower Electronics and Design (ISLPED’02), pp. 124-129, August 2002.

218. G. Bertoni, L. Breveglieri, I. Koren, P. Maistri and V. Piuri, “On the Propagation ofFaults and Their Detection in a Hardware Implementation of the Advanced Encryp-tion Standard,” Proc. of ASAP’02 - the Internl. Conference on Application-SpecificSystems, Architectures and Processors, pp. 303-312, July 2002.

219. Z. Koren and I. Koren, “Analysis of a Flexible Redundancy Technique for Multi-BankMemory ICs,” Proc. of the European Test Workshop (ETW 2002), May 2002.

220. G. Bertoni, L. Breveglieri, I. Koren and V. Piuri, “Fault Detection in the AdvancedEncryption Standard,” Proc. of MPCS’02, the 4th Intern. Conf. on Massively ParallelComputing Systems, pp. 92-97, April 2002.

221. Z. Koren, J. Rajagopal, C. M. Krishna, I. Koren, W. Wang and J. Loman, “UsingRational Approximations For Evaluating The Reliability of Highly Reliable Systems,”Proc. of the PMEO-PDS’02 workshop, IPDPS, pp. 258-263, April 2002.

222. S. Morin, I. Koren and C.M. Krishna, “JMPI: Implementing the Message PassingStandard in JAVA,” Proc. of the International Workshop on Java for Parallel andDistributed Computing, IPDPS, pp. 118-123, April 2002.

223. M. Singh and I. Koren, “Incorporating Fault Tolerance in Analog-to-Digital Con-verters (ADCs),” Proc. of the International Symp. on Quality of Electronic Design(ISQED’02), pp. 286-291, March 2002.

224. O.S. Unsal, I. Koren, C.M. Krishna and C. A. Moritz, “The Minimax Cache: AnEnergy-Efficient Framework for Media Processors,” Proc. of the 2002 InternationalSymp. on High Performance Computer Architecture (HPCA 2002), pp. 131-140, Feb.2002.

225. O. Unsal, R. Ashok, I. Koren, C. M. Krishna, and C.A. Moritz, ”Cool Cache for HotMultimedia,” Proc. of MICRO’34, The International Symp. on Microarchitecture, pp.274-283, Dec. 2001.

226. E. Ciocca, I. Koren and C.M. Krishna, “Application Level Fault Tolerance and Detec-tion,” Proc. of HPEC’01, Annual Workshop on High Performance Embedded Comput-ing, Lincoln Lab, Nov. 2001.

227. M. Singh and I. Koren, “Reliability Enhancement of Analog-to-Digital Converters(ADCs),” Proc. of the 2001 IEEE Intern. Symp. on Defect and Fault Tolerancein VLSI Systems, pp. 347-353, October 2001.

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228. I. Koren, G. Chapman and Z. Koren, “Advanced fault-tolerance techniques for a colordigital camera-on-a-chip,” Proc. of the 2001 IEEE International Symp. on Defect andFault Tolerance in VLSI Systems, pp. 3-10, October 2001.

229. E. Asai, I. Koren and C. M. Krishna, ”A Web/DVD-Based Multimedia ArchitectureSimulator,” Proc. of Frontiers in Education, FIE 2001, pp. T3F.14-19, October 2001.

230. O.S. Unsal, Z. Wang, I. Koren, C.M. Krishna and C. A. Moritz, “On Memory behaviorof Scalars in Embedded Multimedia Systems,” Proc. of the 2001 WMPI, ISCA2001,June 2001.

231. M. Singh, R. Rachala and I. Koren, “Transient Fault Sensitivity Analysis of Analog-to-Digital Converters,” Proc. of WVLSI 2001, pp. 140-145, Orlando, April 2001.

232. R. K. Prasad and I. Koren, “Constructive Floorplanning with a Yield Objective,” Proc.of the International Symp. on Quality of Electronic Design (ISQED’01), pp. 261-266,San Jose, March 2001.

233. I. Koren, G. Chapman and Z. Koren, “A Self-Correcting Active Pixel Camera,” Proc.of the 2000 IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems,pp. 56-64, October 2000.

234. R. K. Prasad and I. Koren, “The Effect of Placement on Yield for Standard CellDesigns,” Proc. of the 2000 IEEE International Symp. on Defect and Fault Tolerancein VLSI Systems, pp. 3-11, October 2000.

235. O.S. Unsal, I. Koren and C.M. Krishna, “High-Level Power Reduction Heuristics forEmbedded Real-Time Systems,” Proc. of EFTS’00, IEEE Workshop On EmbeddedFault-Tolerant Systems, Washington DC, Sept. 2000.

236. D.S. Phatak, T. Goff and I. Koren, “Efficient Arithmetic Implementations Based onCarry-Save Representations,” Proc. of the SPIE’s 45th International Symp. on OpticalScience and Technology, pp. 258-266, August, 2000.

237. V. Lakamraju, I. Koren and C.M. Krishna, “Synthesis of Interconnection Networks: ANovel Approach,” Proc. of the 2000 International Conference on Dependable Systemsand Networks, pp. 501-509, June 2000.

238. O.S. Unsal, I. Koren and C.M. Krishna, “Power-Aware Replication of Data Structuresin Distributed Embedded Real-Time Systems,” Proc. of the IPDPS’00 workshop, onEmbedded/Distributed HPC Systems and Applications, J. Rolim (Ed.), Lecture Notesin Computer Science 1800, Springer, May 2000, pp. 839-846.

239. I. Koren, “Should Yield be a Design Objective?,” invited paper, Proc. of the Intern.Symp. on Quality of Electronic Design, pp. 115-120, March 2000.

240. A. Venkataraman and I. Koren, “Determination of Yield Bounds Prior to Routing,”Proc. of the 1999 IEEE International Symp. on Defect and Fault Tolerance in VLSISystems, pp. 4-13, November 1999.

241. D.S. Phatak, T. Goff and I. Koren, “Redundancy Management in Arithmetic Process-ing via Redundant Binary Representations,” invited paper, Proc. of the 33rd AsilomarConference on Signals, Systems and Computers, pp. 1475-1479, October 1999.

242. I. Koren and Z. Koren, “Incorporating Fault-Tolerance into a Digital Camera-On-A-Chip,” Proc. of the 1999 Microelectronics Reliability and Qualification Workshop, pp.1-3, Oct. 1999.

243. V.R. Lakamraju, I. Koren and C.M. Krishna, “A Randomized Approach to the Syn-thesis of Interconnection Networks,” Proc. of HPEC’99, Annual Workshop on HighPerformance Embedded Computing, Lincoln Lab, pp. 43-44, Sept. 1999.

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244. I. Koren and Z. Koren, “Floorplanning of Memory ICs: Routing Complexity vs. Yield,”Proc. of the International Symp. on Microelectronic Manufacturing Technologies -Yield, Reliability and Failure Analysis (MMT04), May 1999.

245. D.S. Phatak and I. Koren, “Intermediate Variable Encodings that Enable Multiplexor-based Implementations of Two Operand Addition,” Proc. of the 14th IEEE Symp. onComputer Arithmetic, pp. 22-29, April 1999.

246. I. Koren and Z. Koren, “Yield and Routing Objectives in Floorplanning,” Proc. of the1998 IEEE International Symp. on Defect and Fault Tolerance in VLSI Systems, pp.28-36, November 1998.

247. J. Haines, V.R. Lakamraju, I. Koren and C.M. Krishna, “Application-Level FaultTolerance as a Complement to System-Level Fault Tolerance,” Proc. of HPEC’98,Annual Workshop on High Performance Embedded Computing, Sept. 1998.

248. J. Haines, V.R. Lakamraju, I. Koren and C.M. Krishna, “Development of Application-Level Fault Tolerance in a Real-Time Benchmark,” Proc. of EFTS’98, IEEE WorkshopOn Embedded Fault-Tolerant Systems, Boston, May 1998.

249. M. Allalouf, J. Chang, G. Durairaj, V.R. Lakamraju, O.S. Unsal, I. Koren and C.M.Krishna, “RAPIDS: A Simulator Testbed for Fault- Tolerant Real-Time Systems,”Proc. of HPC’98, Grand Challenges in Computer Simulation, pp. 191-196, Boston,April 1998.

250. Z. Koren, I. Koren and C.M. Krishna, “Surge Handling as a Measure of Real-TimeSystem Dependability,” Proc. of the IPPS/SPDP’98 workshop, on Parallel and Dis-tributed Real-Time Systems, J. Rolim (Ed.), Lecture Notes in Computer Science 1388,Springer 1998, pp. 1106-1116.

251. V. Lakamraju, Z. Koren, I. Koren and C.M. Krishna, “Measuring the Vulnerabilityof Interconnection Networks in Embedded Systems,” Proc. of the IPPS/SPDP’98workshop, on Embedded HPC Systems and Applications, J. Rolim (Ed.), Lecture Notesin Computer Science 1388, Springer 1998, pp. 919-924.

252. I. Koren and Z. Koren, “Analysis of a Hybrid Defect-Tolerance Scheme for High-Density Memory ICs,” Proc. of the 1997 IEEE International Symp. on Defect andFault Tolerance in VLSI Systems, pp. 166-174, October 1997.

253. Z. Chen and I. Koren, “Crosstalk Minimization in Three-Layer HVH Channel Rout-ing,” Proc. of the 1997 IEEE International Symp. on Defect and Fault Tolerance inVLSI Systems, pp. 38-42, October 1997.

254. A. Venkataraman, H. Chen and I. Koren, “Yield Enhanced Routing for High-PerformanceVLSI Designs,” Proc. of the Microelectronics Manufacturing Yield, Reliability andFailure Analysis, SPIE’97, pp. 50-60, Austin, Texas, October 1997.

255. Z. Chen and I. Koren, “Technology Mapping for Hot-Carrier Reliability Enhancement,”Proc. of the Microelectronics Manufacturing Yield, Reliability and Failure Analysis,SPIE’97, pp. 42-50, Austin, Texas, October 1997.

256. D. H. Albonesi and I. Koren, “Improving the Memory Bandwidth of Highly-Integrated,Wide-Issue, Microprocessor-Based Systems,” Proc. of the 1997 Conf. on ParallelArchitectures and Compilation Techniques (PACT’97), pp. 126-135, November 1997.

257. D. H. Albonesi and I. Koren, “An Automated and Flexible Framework for IntegratedMicroprocessor and System-Level Design Space Exploration,” Proc. of the 1997 Work-shop on Performance Analysis and its Impact on Design (PAID’97), pp. 25-34, Denver,Colorado, June 1997.

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258. Z. Chen and I. Koren, “Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing,” Proc. of the 1996 IEEE International Symp. on Defect andFault Tolerance in VLSI Systems, pp. 76-84, November 1996.

259. A. Venkataraman and I. Koren, “Trade-offs between Yield and Reliability Enhance-ment,” Proc. of the 1996 IEEE International Symp. on Defect and Fault Tolerance inVLSI Systems, pp. 67-75, November 1996.

260. V.K.R. Chiluvuri and I. Koren, “Wire Length and Via Reduction for Yield Enhance-ment,” Proc. of the 1996 SPIE Microelectronics Manufacturing Conference, pp. 103-111, Austin, Texas, Oct. 1996.

261. I. Koren and Z. Koren, “Yield Analysis of a Novel Scheme for Defect-Tolerant Mem-ories,” Proc. of the 1996 IEEE International Conference on Innovative Systems inSilicon, pp. 269-278, Austin, Texas, October 1996.

262. I. Koren, “Catastrophic Yield, Parametric Yield and Reliability: Can We Still ViewThem as Disjoint Issues?,” invited paper, Proc. of the 5th ACM/SIGDA PhysicalDesign Workshop, pp. 207-209, April 1996.

263. B. Iyer, R. Karri and I. Koren, “Phantom Redundancy: A High-Level Synthesis Tech-nique for Manufacturability,” Proc. of ICCAD-95, The Internl. Conference on CAD,pp. 658-661, Nov. 1995.

264. I. A. Wagner and I. Koren, “The Effect of Spot Defects on the Parametric Yield ofLong Interconnection Lines,” Proc. of the 1995 IEEE Internl. Workshop on Defectand Fault Tolerance in VLSI Systems, pp. 46-54, November 1995.

265. Z. Chen and I. Koren, “Layer Assignment for Yield Enhancement,” Proc. of the 1995IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 173-180,November 1995.

266. D. H. Albonesi and I. Koren, “Architecture and Technology Tradeoffs in the Design ofNext-Generation Multiprocessor Servers,” Proc. of the 7th IEEE Symp. on Paralleland Distributed Processing, pp. 174-181, Oct. 1995.

267. P. Lalwaney and I. Koren, “Fault-Tolerance Schemes for WDM-Based MultiprocessorNetworks,” Proc. of the 2nd Intern. Conference on Massively Parallel Processing usingOptical Interconnections, pp. 90-97, Oct. 1995.

268. V.K.R. Chiluvuri and I. Koren, “Yield Enhancement vs. Performance Improvementin VLSI Circuits,” Proc. of ISSM-95, The Intern. Symp. on Semiconductor Manufac-turing, pp. 28-31, Austin, Sept. 1995.

269. Z. Chen and I. Koren, “Techniques for Yield Enhancement of VLSI Adders,” Proc.of ASAP 95 - the Internl. Conference on Application-Specific Array Processors, pp.222-229, July 1995.

270. D. H. Albonesi and I. Koren, “An Analytical Model of High Performance Superscaler-Based Multiprocessors,” Proc. of the 1995 Internl. Conf. on Parallel Architecturesand Compilation Techniques (PACT’95), pp. 194-203, Limassol, Cyprus, June 1995.

271. Z. Koren and I. Koren, “The Impact of Floorplanning on the Yield of Fault-TolerantICs,” Proc. of Internl. Conf. on Wafer Scale Integration, pp. 329-338, Jan. 1995.

272. Z. Chen and I. Koren, “A Yield Study of VLSI Adders,” Proc. of the 1994 IEEEInternl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 239-245, Oct.1994.

273. V.K.R. Chiluvuri, I. Koren and J. L. Burns, “The Effect of Wire Length Minimizationon Yield,” Proc. of the 1994 IEEE Internl. Workshop on Defect and Fault Tolerancein VLSI Systems, pp. 97-105, October 1994.

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274. D. H. Albonesi and I. Koren, “Tradeoffs in the Design of Single Chip Multiprocessors,”Proc. of the 1994 IFIP WG 10.3 Workshop on Parallel Architectures and CompilationTechniques (PACT’94), pp. 25-34, Montreal, Canada, August 1994.

275. P. Lalwaney and I. Koren, “Reconfigurable Optical Interconnects for Computer VisionApplications,” Proc. of the 1st Intern. Workshop on Massively Parallel Processingusing Optical Interconnections, pp. 224-236, April 1994.

276. A. Dasgupta and I. Koren, “An Algorithm for Area and Delay Optimization of Sequen-tial Machines through Decomposition,” Proc. of HICSS-27, Hawaii Internl. Conf. onSystem Sciences, vol. I, pp.36-45, Jan. 1994.

277. I. A. Wagner and I. Koren, “An Interactive Yield Estimator as a VLSI CAD tool,”Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSISystems, pp. 167-174, October 1993.

278. V.K.R. Chiluvuri and I. Koren, “Topological Optimization of PLAs for Yield Enhance-ment,” Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance inVLSI Systems, pp. 175-182, October 1993.

279. Z. Koren and I. Koren, “Does the Floorplan of a Chip Affect Its Yield?” Proc. of the1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp.159-166, October 1993.

280. B. Mendelson and I. Koren, “Mapping Algorithms onto a Multiple-Chip Data-DrivenArray,” Proc. of ASAP 93 - the Internl. Conference on Application-Specific ArrayProcessors, pp. 41-52, October 1993.

281. D.S. Phatak, I. Koren and H. Choi, “Hybrid Number Representations with BoundedCarry Propagation Chains,” Proc. of ICCD’93 - the Internl. Conf. on ComputerDesign, pp. 272-275, Oct. 1993.

282. D. Eisig, J. Rotstain and I. Koren, “The Design of a 64-bit Integer Multiplier/DividerUnit,” Proc. of the 11th IEEE Symp. on Computer Arithmetic, pp. 171–178, June1993.

283. V.K.R. Chiluvuri and I. Koren, “New Routing and Compaction Strategies for YieldEnhancement,” Proc. of the 1992 IEEE Internl. Workshop on Defect and Fault Tol-erance in VLSI Systems, pp. 325-334, November 1992.

284. W. Che and I. Koren, “Fault Spectrum Analysis for Fast Spare Allocation in Recon-figurable Arrays,” Proc. of the 1992 IEEE Internl. Workshop on Defect and FaultTolerance in VLSI Systems, pp. 60-69, November 1992.

285. I. Koren, Z. Koren and C.H. Stapper, “Analysis of Defect Maps of Large Area VLSIICs,” Proc. of the 1992 IEEE Internl. Workshop on Defect and Fault Tolerance inVLSI Systems, pp. 267-276, November 1992.

286. P. Lalwaney, L. Zenou, A. Ganz and I. Koren, “Optical Interconnects for Multiproces-sors: Cost Performance Trade-Offs,” Proc. of Frontiers ’92: The 4th Symp. on TheFrontiers of Massively Parallel Computation, pp. 278-285, Oct. 1992.

287. V.K.R. Chiluvuri and I. Koren, “Reliability Analysis of a Highly Integrated Multipro-cessor System,” Proc. of the IEEE Workshop on Fault Tolerant Parallel and DistributedSystems, pp. 54-61, July 1992.

288. D.S. Phatak and I. Koren, “Fault Tolerance of Feedforward Neural Nets for Classifi-cation Tasks,” Proc. of the IEEE International Joint Conf. on Neural Networks, pp.II.386-II.391, June 1992.

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289. Z. Koren and I. Koren, “A Model for Enhanced Manufacturability of Defect TolerantIntegrated Circuits,” Proc. of the 1991 IEEE Internl. Workshop on Defect and FaultTolerance in VLSI Systems, pp. 81-92, November 1991.

290. I. Koren, “Projecting the Yield of Defect Tolerant ICs,” invited paper, Proc. of theIEICE Fault Tolerant Systems Workshop in Japan, Vol. 91, No. 122, FTCS 91-25, pp.47-54, July 1991.

291. B. Mendelson and I. Koren, “Using Simulated Annealing for Mapping Algorithmsonto Data Driven Arrays,” Proc. of the 1991 Internl. Conf. on Parallel Processing,pp. I.123-127, August 1991.

292. B. Patel, D.K. Pradhan and I. Koren, “High Level Synthesis of Data Driven ASICs,”Proc. of ASIC91, IEEE Internl. Application-Specific ICs Conf., pp. 13-3.1-3.4, Sept.1991.

293. I. Koren, Z. Koren and C.H. Stapper, “Employing the Unified Negative BinomialDistribution for Yield Analysis of Empirical Data,” Proc. of the 1990 IEEE Internl.Workshop on Defect and Fault Tolerance in VLSI Systems, Grenoble, Nov. 1990.

294. J. A. Feldman and I. Koren, “On Generating Two Dimensional CMOS Cells,” Proc.of the IEEE Int’l Conf. on CAD/CAM, Dec. 1989.

295. I. Koren and Z. Koren, “Discrete and Continuous Models for the Performance of Multi-stage Systems in the Presence of Faulty Components,” Proc. of HICSS-22, HawaiiInternl. Conf. on System Sciences, pp. 724-732, Jan. 1989.

296. J-J. Shen and I. Koren, “Yield Enhancement Designs for WSI Cube Connected Cycles,”Proc. of Internl. Conf. on Wafer Scale Integration, pp. 289-298, Jan. 1989.

297. S. Wimer, I. Koren and I. Cederbaum, “Optimal Aspect Ratios of Building Blocks inVLSI,” Proc. of the 25th Design Automation Conf., pp. 66-72, June 1988.

298. I. Koren and Z. Koren, “On the Bandwidth of a Multi-stage Network in the Presenceof Faulty Components,” Proc. of the 8th Internl. Conf. on Distributed ComputingSystems, pp. 26-32, June 1988.

299. I. Koren, Z. Koren and D.K. Pradhan, “Wafer–Scale Integration of Multi–processorSystems,” Proc. of HICSS-20, Hawaii Internl. Conf. on System Sciences, pp. 13-20,Jan. 1987.

300. S. Wimer and I. Koren, “Constructive Placement of General Blocks in VLSI underUncertainties in the Position of Ports,” Proc. of the 1986 Internl. Conf. on Computer–Aided Design, 4pp., Nov. 1986.

301. H. Mizhrahi and I. Koren, “Evaluating the Cost–Effectiveness of Switches in ProcessorArrays Architectures,” Proc. of the 1985 Internl. Conf. on Parallel Processing, pp.480–487, August 1985.

302. I. Koren and D.K. Pradhan, “Introducing Redundancy into VLSI Designs for Yieldand Performance Enhancement,” Proc. of the 15th Internl. Symp. on Fault–TolerantComputing, pp. 330–335, June 1985.

303. I. Koren and G.M. Silberman, “A Direct Mapping of Algorithms onto VLSI ProcessorArrays Based on the Data Flow Approach,” Proc. of the 1983 Internl. Conf. onParallel Processing, pp. 335–337, August 1983.

304. D. Aljadeff and I. Koren, “A Microprocessor–based Hardware Monitor for PerformanceEvaluation of Computer Systems,” Microsystems: Architecture and Integration, EU-ROMICRO 82, C.J. van Spronsen and L. Richter (eds.), North–Holland, pp. 123–130,1982.

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305. I. Koren and M. Berg, “A Module Replacement Policy for Dynamic Fault–TolerantComputing Systems,” Proc. of the 11th Internl. Symp. on Fault–Tolerant Computing,pp. 90–95, June 1981.

306. I. Koren, “A Reconfigurable and Fault–Tolerant VLSI Multiprocessor Array,” Proc. ofthe 8th Annual Symp. on Computer Architecture, pp. 425–441, May 1981.

307. I. Koren and Y. Maliniak, “A Unified Approach to a Class of Number Systems,” Proc.of the 4th IEEE Symp. on Computer Arithmetic, pp. 25–28, October 1978.

308. I. Koren “Signal Reliability of Combinational and Sequential Circuits,” Proc. of the7th Internl. Symp. on Fault–Tolerant Computing, pp. 162–177, June 1977.

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