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Proceedings of theIEEE 1985

CUSTOM INTEGRATED CIRCUITSCONFERENCE

The Portland Hilton

Portland, Oregon May 20-23, 1985

UNIVERSITATS818U0THEKHANNOVER

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The CICC '85 is sponsored by the IEEE Electron Devices Society, the IEEE Rochester Section,and the IEEE Solid-State Circuits Council. Its aim is to bring together designers, producers, andusers of custom IC's to discuss recent developments and future directions in custom integratedcircuits.

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CONTENTS

MONDAY MORNING Pavilion

2:00 Incremental Design Rule Checking

P. A. Swartz, K. Mednick, SDA Systems, Santa Clara, CA

PAGE

10:35 A Custom Interconnect Using Tape Carrier Approach 38N. Kim, R. F. Cooley, Gould AMI Semiconductors, Santa Clara, CA

11:00 An Inexpensive High Frequency, High Power, VLSI Chip Carrier 42K. Smith, Tektronix, Inc., Beaverton, OR

11:25 New Generation of High Pin Count Packages 45G. Fehr, J. Long, A. Tippets, LSI Logic Corp. Milpitas, CA

11:50 Thermomechanical Analysis and Testing of Leadless Ceramic Chip Carriers for VLSI Packaging 50G. V. Clatterbaugh, H. K. Charles, Jr., The Johns Hopkins University, Laurel, MD

12:15 The Wafer Transmission Module—Wafer Scale Integration Packaging 55G. Taylor, B. Donlan, J. F. McDonald, A. Bergendahl, R. Steinvorth, Rensselaer Polytechnic Institute, Troy, NY

MONDAY AFTERNOON State Room PAGE

NEW APPROACHES FOR BOTH ANALOG AND DIGITAL LAYOUT GENERATION 59

Chairman: Daniel F. Daly

Co-chairman: Joshua Alspector

60

2:25 SYMBAD: A Tool for a New Layout Methodology6*

D. Devecchi, A. Montrezza, M. Morganti, L. Sturlese, G. Torelli, SGS-ATES Component!Elettroroct S.pA Mrtano. Italy

2:50 An Automatic Routing System for General Cell VLSI Circuits

H. Cai, H. Th. Verheyen, R. Nouta, P. Dewilde, Delft Univ. of Technology, Delft,The Netherlands

68

3:15 Autorouted Analog VLSI _„72

K. J. Stern*, C. D. Kimble*, G. F. Gross", E. J. Swanson*. M. Y. Luong*,A. E. Dunlop'*, AT&T Bei Labs, Fteadmg PA ,

AT&T Bell Labs, Murray Hill, NJ**

3:40 Automated Design of Analog LSI

G. I. Serhan, Micro Linear Corp., San Jose, CA

79

CONTENTS

MONDAY AFTERNOON Rose Room PAGE

TELECOMMUNICATION APPLICATIONS 83Chairman: Harold L. Scalf

Co-chairman: Sidney Shapiro

2:00 A Controller for the Cellular Mobile Radio System 'C-Netz' 84P. Picard, H. Kramer, H. v.d.Neyen, Siemens AG, Munchen, W. Germany

2:25 A Digital Multipoint Telecommunication Conferencer VLSI 88J-M Liu*, L. Baranyai**, AT&T Bell Labs, Allentown, PA*, AT&T Bell Labs, Holmdel, NJ**

2:50 A Digital Multlfrequency Detector for PCM Systems 92J. M. Laraia, A,LP. Janzon, L.O.F. Goncalves, Telecommunicacoes Braslleiras S/A, Campinas, Brazil

3:15 Integrated Loop Signalling Repeater Chip 96P, S. Kasbia, J. C. Ghelani, Y. L Li, P. Jacobs, Bell-Northern Research, Ottawa, Ont., Canada

3:40 A Monolithic 70 V Subscriber Line Interface Circuit 101

J. F. Pieters, E. Moons, E. Willocx, S, Beckes, Bell Telephone Mfg. Co., Antwerp, Belgium

4:05 LATE PAPER 105

Experimental Single Chip PABXM. Cooperman, R, Sieber, R. Moolenbeek, J. E. Rathke, S. B. Couch, A. Paige, J. Fried, GTE Laboratories, Waltham,MA

MONDAY AFTERNOON Pavilion PAGE

CIRCUITS FOR IMAGING AND SENSING 111

Chairman: Bernd HoefflingerCo-chairman: Jagdish C. Tandon

1:45 TUTORIAL 112

Technology Progress and Trends in Solid-State Silicon Image SensorsS. G. Chamberlain*, J. H. Broughton**, University of Waterloo, Waterloo, Ont.*, Dalsa Inc., Waterloo, Ont.**

2:25 INVITED 119

A Three-Dimensional Computer for Image and Signal ProcessingM, J. Little, J. G. Nash, R. D. Etchells, J. Grinberg, G. R, Nudd, Hughes Labs, Malibu, CA

2:50 Deep Depletion CCD's for U.V. and X-Ray Imaging for Astronomy 124N. Saks*, M. Peckerar*, D. Mlchels*, D, McCarthy*, J. Bosiers**, Naval Research Lab, Washington, DC*, Sachs-Free¬man Associates, Inc., Bowie, MD**

3:15 A Novel CCD Output Structure for Picture Processing Applications 128

J. P, Vermeiren, G. J. DeClerck, IMEC, Heverlee, Belgium

CONTENTS

MONDAY AFTERNOON PavilionPAGE

132

3:40 Contact Type High Speed Image Sensor by Bipolar IC'sK. Yamaguchi, T. Murata, Y. Yamamoto, Matsushita Electric Industrial Co., Ltd., Osaka, Japan

4:05 Phomat-2000: A NMOS Photosensor with Binary Output Pattern136P. Deleuze, J. D. Legat, P. DeMuelenaere, P. Jespers, Univ. Catholique De Louvain, Louvain-La-Neuve, Belgium

4:30 A Custom Analog IC for a Smart Pressure Sensor140M.J.S. Smith, L. Bowman, M. A. Prisbe, J. D. Meindl, Stanford University, Stanford, CA

4:55 A Dedicated Processing and Control IC for Pressure Telemetry 144B. Puers, W. Sansen, Univ. of Leuven, Heverlee, Belgium

TUESDAY MORNING State Room PAGE

ECONOMIC ASPECTS OF LSI DESIGN 147Chairman; David M. Lewis

Co-chairman: Richard N. Bryant

9:10 Selection of Cost Effective LSI Design Methodologies 148C. F. Fey, D. Paraskevopoulos, Xerox Corp., El Segundo, CA

9:35 Design Productivity Study 153E. J. Kuuttila*, R. C. Anderson**, P. Matlock**, ZK Consulting, San Jose, CA*, R. C. Anderson, Inc., Los Altos, CA**

TUESDAY MORNING Rose Room PAGE

DATA ACQUISITION & SIGNAL PROCESSING 155

Chairman: Robert H. Dawson

Co-chairman: T. H. Lee

9:10 A High-Speed 8-Bit Current Steering CMOS OAC 15,BK. R. Lakshmi Kumar*, R. A. Hadaway**, M, A. Copeland*. M.I.H. King**, Carleton University, Ottawa, Canada*, NorthernTelecom Electronics, Ottawa, Canada**

9:35 A 20 MHz Flash A/D Converter Macro Cell 16t>

S. T. Chu, J. L. Garrett, G. E. Company, Schenectady, NY

10:00 A Power-Saving Technique for Flash Analog-to-Digital Converters 16^

P. H. Saul, A. K. Joy, T. C. Leslie, Plessey Research (Caswell) Ltd., Caswell, England

CONTENTS

TUESDAY MORNING Rose Room PAGE

10:25 A 32K Bit High Speed on-chip DRAM for Digital Signal Processor 166L. V. Tran, AT&T Bell Labs, Allentown, PA

10:50 A Bi-CMOS Analog/Digital LSI with the Programmable 280bit SRAM 170Y. Kowase*, Y. Yanagawa*, T. Inaba*, J. Mameda*, N. Horie*, S. Ueda*, M. Nagata**, Hitachi, Gunma, Japan*, Hitachi,Tokyo, Japan**

11:15 80 MHz Low Offset CMOS Fully Differential and Single-Ended OP AMPS 174D. B. Ribner*, M. A. Copeland*, M. Milkovic**, Carleton Univ., Ottawa, Ont., Canada*, General Electric Co., Schenectady,NY**

TUESDAY MORNING Pavilion PAGE

WAFER FABRICATION TECHNOLOGIES 179

Chairman: James L. DunkleyCo-chairman: Peter M. Zeitzoff

9:10 INVITED 180

Advances in Bipolar IC TechnologiesD. D. Tang, T. H. Ning, IBM, Yorktown Heights, NY

9:35 A High-Speed, High Density Single Poly ECL Technology for Linear/Digital Applications 184

A. K. Kapoor, N. Bhandari, L. H. Jones, R. Kovacs, H. Hingarh, Fairchild, Palo Alto, CA

10:00 An Advanced Dual Metal CMOS Technology for High Density Semicustom Products 188

S. Huang, M. Khan, Y. Strunk, T. Batra, Gould AMI Semiconductors, Santa Clara, CA

10:25 An Enchanced Fully Scaled 1.2n.m CMOS Process for Analog Applications 192

R. K. Reich, C. Rahn, M. Holt, J. W. Schrankler, D. H. Ju, G. D. Kirchner, Honeywell Inc., Plymouth, MN

10:50 A High Performance 1^m CMOS Process for VLSI Applications 196

R. R. Doering, M. P. Duane, J. M. McDavid, D. A. Baglee, D. Ciark, S. Crank, G. J. Armstrong, Texas Instruments Inc.,Houston, TX

11:15 Optimized Retrograde N-well for One Micron CMOS Technology 199

R. A. Martin, J. Y. Chen, Xerox, Palo Alto, CA

11:40 Application of 1.75p,m CMOS for Custom Logic VLSI 203

D. M. Wroge, M. E. Potter, R. C. Sun, B. Keramati, AT&T Beil Labs, Allentown, PA

12:05 LATE PAPER 206

AI/Si02/WSi2/Si Double-Level Metallization for CCD ImagersH. L Babbar, C. N. Anagnosopoulos, J. R. Fischer, Eastman Kodak Co., Rochester, NY

CONTENTS

TUESDAY MORNING Music Box Theatre

8:50 TUTORIAL

Silicon Compilation EnvironmentsM. R. Buric, T. G. Matheson, Silicon Design Labs, Inc., Basking Ridge, NJ

PAGE

SYNTHESIS OF SPECIAL IC DESIGNS FROM OPTIMIZED FUNCTIONAL SPECIFICATIONS 207Chairman; Jonathan Allen

Co-chairman: David E. Brown

208

9:35 A High-Level Language and Silicon Compiler for Digital Signal Processing 213-'' P. N. Hilfinger, University of California, Berkeley, CA

10:00 An Integrated Automated Layout Generation System for Digital Signal Processing Circuits 217J. M. Rabaey, S. P. Pope, R. W. Broderserr, Univ. of California, Berkeley, CA

10:25 INVITED 221

An Overview of Synthesis SystemsA. Sangiovanni-Vincentelli, Univ. of California, Berkeley, CA

10:50 PLASCO: A Procedural Silicon Compiler for PLA Based Systems 226M. Bartholomeus, L. Reynders, M. Pauwels, H. DeMan, Univ. of Leuven, Heverlee, Belgium

11:15 Espresso-MV: Algorithms for Multiple-Valued Logic Minization 230

R. L. Rudel, A.L.M. Sangiovanni-Vincentelli, Univ. of California, Berkeley, CA

11:40 Logic Minimization, Placement and Routing in SWAMI 235

C. Rowen, J. L. Hennessey, Stanford University, Stanford, CA

TUESDAY AFTERNOON State RoomPAGE

MACROBASED DESIGNS239

Chairman: Don Soderman

Co-chairman: Allan L. Goodman

2:00 Configurable On-Chip RAM Incorporated Into High Speed Logic Array240

R. Masumoto, Applied Micro Circuits Corp., San Diego, CA

2:25 2fi,m Double Level Metal CMOS Gate Array withFlexible Memory 244

J. Desuche, B. Beyron, M. Briet, P-H Ferme, Matra Harris Semiconductors, Cedex,France

2:50 A Composite CMOS Gate Array with 4K RAM and128K ROM 248

N. Miyahara, S. Hamaguchi, K. Ishikawa, S. Horiguchi, M. Aoki, Nippon Telegraph& Telephone Public Corp., Atsugi,

Japan

3:15 Structured Arrays—A New ASIC Concept Provides theBest of Gate Arrays and Cell Based Custom

25*

R. Walker, P. Yin, K. Lobo, Y. Chang, P. Tsao, A. Yuen, J. Hsue,LSI Logic Corp., Milpitas, CA

CONTENTS

TUESDAY AFTERNOON State Room PAGE

3:40 A Modular Memory Building Block Approach for VLSI 258

M. Mazine, J-l Sano, D. Montrone, N. Cserhalmi, Raytheon Co., Andover, MA

4:05 2901/2910 Core Microprocessor Cells Bring 'Systems-On-A-Chip' to Semicustom Standard Cells 264L. F. Parisoe, G. W. Knapp, General Electric Semiconductor, Research Triangle Park, NC

4:30 Super Integration 267K. Nagao, Y. Shiotari, A. Sueda, T. Saito, T. Yamamoto, K. Uchida, S. Takeda, Y. Fukushima, M. Hirasawa, Toshiba

Corp., Kawasaki, Japan

4:55 LATE PAPER 272

A One-Day Chip: An innovative IC Construction Approach Using Electrically Reconfigurable Logic VLSIY. Ikawa, K. Uri, M. Wada, T. Takada, M. Kawamura, M, Miyata, N. Amano, T. Shibata Toshiba, Kawasaki, Japan

TUESDAY AFTERNOON Rose Room PAGE

DIGITAL SIGNAL PROCESSING 273

Chairman: Sanjeev RenjenCo-chairman: David M. Lewis

2:00 INVITED 274

Custom Digital Signal Processor Architecture and ImplementationY. Bouterfa, A. Meraghni, C. Trullemans, P. Jespers, Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium

2:25 A High Performance 1.25 Micron CMOS Floating Point Multiply/Accumulate Chip 278C. Y. Ho, K. Molnar, D. Staver, R. Jerdonek, General Electric Co., Schenectady, NY

2:50 A 1.0 Micron CMOS 32 Bit IEEE Format Floating Point Chip Set for Digital Signal Processing 281T. Tran, A. Kuo, C. Yasha, R. Cria"do, M. Siddique, D. D. Hsu, S. Renjen, TRW-LSI Products, La Jolla, CA

3:15 A Single Chip CMOS Floating Point Signal Processor 285M. Kasai, K. Narita, N. Furuno, K. Sakamoto, G. Onodera, NEC Corp., Kawasaki, Japan

3:40 A 24x24 Bit Parallel Multiplier Based on a Further Modified Booth's Algorithm 289N. Zafar, M. N. Konar, T. Oseth, Honeywell Inc., Minneapolis, MN

4:05 A High Performance Microprogrammed IC for Signal Processing Applications 292G. P. Powell, A. M. Smith, M. W. Stebnisky, K. Prost, RCA Corp., Moorestown, NJ

4:30 A VLSI for 32kbps ADPCM Transcoding 296M. S. Song, S. Narasimha, Granger Associates, Santa Clara, CA

CONTENTS

TUESDAY AFTERNOON Pavilion PAGE

TESTING AND RELIABILITY 301

Chairman: Stephen R. QuigleyCo-chairman: Thomas M. Kelly

2:00 A Memory and Testability Cell for 1.25 Micron CMOS Gate Arrays 302

J. D. Milner, J. J. Watters, General Electric Co., Research Triangle Park, NC

2:25 On-Chip Testing of Embedded PLAs 306

P. Varma*, A. Ambler**, K. Baker***, Tokyo Inst, of Tech., Tokyo, Japan*, Brunei Univ., Middlesex, Eng.**, GEC Re¬

search Labs, London, Eng.***

2:50 CMOS Circuit Testability 311

P. S. Moritz, L M. Thorsen, IBM, Essex Junction, VT

3:15 Test Derivation for CMOS Iterative Logic Arrays 315

R. Sharma, D. Radhakrishnan, Old Dominion Univ., Norfolk, VA

3:40 Latch-up Characterization Using Specially Designed Test Structures 319

S. Boyd, M. Faucher, Mitel S.C.C, Bromont, Quebec, Canada

4:05 Reliability Considerations in High Voltage Custom IC Operation 324

D. Gibson, Harris Semiconductor, Melbourne, FL

4:30 Incorporation of the BILBO Technique Within an Existing Chip Design 328

J. Beausang, A. Albicki, Univ. of Rochester, Rochester, NY

TUESDAY AFTERNOON Music Box Theatre PAGE

MODELING 333

Chairman: Donald L. Scharfetter

Co-chairman: David E. Brown

2:00 Design-Performance Trade-Offs in CMOS Domino Logic 334V. G. Oklobdzija, R. K. Montoye, IBM, Yorktown Heights, NY

2:25 High Speed Circuit Simulation of Million Transistor Circuits 338

R. L. Manning, A. P. Ambler, Brunei Univ., Uxbridge, Middlesex, U.K.

2:50 An Efficient Approach to RC Path Signal Delay Calculation for CMOS Semicustom Integrated Circuits 342

S. A. Huss, AEG-TELEFUNKEN, Ulm, West Germany

3:15 Modeling MOS Circuits for Timing Simulation 346

P. Subramaniam, AT&T Bell Labs, Murray Hill, NJ

CONTENTS

TUESDAY AFTERNOON Music Box Theatre PAGE

3:40 A Simplified Accurate Three-dimensional Table Look-Up MOSFET Model for VLSI Circuit Simulation 347K. Sakui*, T. Shima*, Y. Hayashi**, F. Horiguchi*, M. Ogura**, Toshiba Corp., Tokyo, Japan*, Toshiba Corp., Kawasaki,

Japan**

4:05 Automatic Timing Characterization for Large Regular Structures 352T. P. Moore, A. J. deGeus, General Electric, Research Triangle Park, NC

4:30 A Cost-Effective Custom CAD System 356R. C. Burton, D. G. Brewer, R. E. Penman, R. Schilmoeller, Brigham Young Univ., Provo, UT

TUESDAY EVENING State Room PAGE

8:00 TUESDAY EVENING PANEL 363"Silicon Compilers"

Moderator: Graham Shenton, V.P. Business Development, I.M.P.

Panelists: Hal Alles, President, Silicon Design LabsBob Brayton, Senior Scientist, IBM Research, Yorktown HeightsFrank Garofalo, President, Metalogic Inc.John Gray, M.D.,Lattice Logic LimitedPhil Kaufman, President, Silicon Compilers Inc.Richard Oettel, V.P., Seattle Silicon Technology

TUESDAY EVENING Rose Room PAGE

8:00 TUESDAY EVENING PANEL 365"Custom Technologies of the Future: Bipolar, CMOS, GaAs"

Moderator: Marc D. Hartranft, Senior Development Engineer, Cypress Semiconductor Corporation

Panelists: Tom Ainisle, Manager, Product Development, IBMDick Bryant, Vice-President of Development, Ford MicroelectronicsDick Eden, Senior Vice-President of Research & Development, GigaBit Logic, Inc.Tom Hendrickson, President, VTC, Inc.Jack Huang, Chief Fellow, SSCL, Honeywell, Inc.Susumu Kohyama, Manager, CMOS Technology, Toshiba Corp.

CONTENTS

TUESDAY EVENING Pavilion PAGE

8:00 TUESDAY EVENING PANEL 367

"Design Alternatives: Custom/Semi-Custom vs Off-the-Shelf IC's"

Moderator: Allan L. Goodman, ATEQ Corporation

Panelists: Edmund Cheng, Vice-President of Custom Design & Applications Engineering, Silicon Compilers, Inc.James Giddings, PAL Project Manager.Texas InstrumentsClive McCarthy, Director of Applications, Altera CorporationJustin Rattner, Program Manager, Intel Development Operation

James Rowson, Manager of Software Development, VLSI Technology IncorporatedRobert M. Walker, Vice President of Engineering, LSI LOGIC, Inc.Peter Wilson, Microcomputer Applications Manager, INMOS Corporation

WEDNESDAY MORNING State Room PAGE

PROCEDURAL TECHNIQUES AND DATABASE REPRESENTATIONS FOR IC DESIGN 369

Chairman: Alberto Sangiovanni-VincentelliCo-chairman: Constantine N. Anagnostopoulos

8:50 TUTORIAL 370

The Design and Implementation of Data Base Management Systems for VLSI DesignR. Newton, Univ, of California, Berkeley, CA

9:35 INVITED 371

Experiences With Using a Relational DMBS for Storing Layout Data

R. Raghavan, D. Stevens, R. Swanson, Mentor Graphics, Beaverton, OR

10:00 INVITED 372

Data-Base Management Systems: A Designer's PerspectiveS. Law, SDA Systems, Santa Clara, CA

10:25 INVITED 375

Module Generation Tools for Physical Design EngineersK. C. Chu, Microelectronics & Computer Technology Corp., Austin, TX

10:50 INVITED 379

RUBICC—A Rule Based Expert System for VLSI Integrated Circuit CritiqueC. Lob*, A. R. Newton**, Hewlett-Packard, Corvallis, OR*, University of California, Berkeley, CA**

11:15 Circuit Synthesis for the Silc Silicon Compiler384

C. Rosebrugh, J. Vellenga, GTE Laboratories Inc., Waltham, MA

CONTENTS

WEDNESDAY MORNING State Room PAGE

11:40 Parameterized Buffer Cells Integrated Into an Automated Layout System 389E. Friedman, W. Marking, E. lodice, S. Powell, Hughes Aircraft Co., Carlsbad, CA

WEDNESDAY MORNING Rose Room PAGE

CUSTOM APPLICATIONS 393

Chairman: Gregory W. LedenbachCo-chairman: Wesley A. Vincent

9:10 A Custom Precision Power Supply IC for Cost Effective Automotive Applications 394D. Valente*, R. Lanoue**, Ford Motor Co., Dearborn, Ml*, Cherry Semiconductor Corp., East Greenwich, Rl**

9:35 A High Speed Arbiter for Resource Management in Distributed Processor Systems 395J. Caraballo, D. Bondurant, L. Jack, D. Wick, Honeywell, Inc., Colorado Springs, CO

10:00 A Self-Adjusting Paper Path Sensor Using Charge Rundown A/D Conversion 399M. Zomorrodi, L-F Cheung, Xerox Corp., E! Segundo, CA

10:25 A 28 MHz Modified CMOS Standard Cell Video Attribute Chip 403

D. K. Guilboard, M. L Kyle, A. F. Medsker, R. E. Mikkelson, D. E. Schrope, P. F. Walch, AT&T Teletype Corp., Skokie,IL

10:50 Subsystem ICs for Winchester Disk Driver 407H. Sato, T. Okabe, K. Michii, R. Sakano, Mitsubishi Electric Corp. Itami, Japan

WEDNESDAY MORNING Pavilion PAGE

GaAs DIGITAL INTEGRATED CIRCUITS 413Chairman: Richard N. BryantCo-chairman: Raymond A. Milano

9:10 GaAs Based Electronic Technology for Space Applications 414S. A. Roosiid, Defense Advanced Research Projects Agency, Arlington, VA

9:35 Commercial Availability of High Speed GaAs IC's: An Overview 417F. S. Lee, R. M. Hickling, R. C. Eden, Gigabit Logic, Inc. Newbury Park, CA

10:00 Design Considerations for Commercial GaAs Digital Integrated Circuits 421D. Laude, G. Noufer, Ford Microelectronics Inc., Colorado Springs, CO

CONTENTS

WEDNESDAY MORNING Pavilion PAGE

10:25 Super-Buffer FET Logic (SBFL) for GaAs Gate Arrays 425/K. Tanaka, H. Nakamura, Y. Kawakami, M. Akiyama, T. Ishida, K. Kaminishi, Oki Electric Industry Co., Ltd., Tokyo,

Japan

10:50 Low Power Logic Gate with Active Pull-Down Push-Pull Output for GaAs SDFL Circuits 429T. Vu*, R. Nelson*, G. Lee*, K. Lee*, S. Swanson*, A. Peczalski*. W. Betten*, S. Hanka**, M. Helix**, Honeywell, Minne¬

apolis, MN*, Honeywell, Bloomington, MN**

11:15 GaAs JFET Custom IC Development 434T. P. Nicalek, J. K. Notthoff, McDonnell Douglas, Huntington Beach, CA

11:40 LATE PAPER 436

Design Analysis of GaAs Direct-Coupled Field Effect Transistor LogicA. Peczalski*, M. Shur**, C. H. Hyun**, K. Lee**, T. Vu*, Honeywell, Inc.*, Univ. of Minn.**, Minneapolis, MN

WEDNESDAY AFTERNOON State Room PAGE

DESIGN SYSTEMS 437

Chairman: Ronald T. Jerdonek

Co-chairman: Bob Markle

1:45 Characterization of Standard Cell Libraries 438

I. Jones, International Microelectronic Products, San Jose, CA

2:10 ASIC Design with Microcontroller in INTEL'S ICEL Design System 442H. Amini, S. Hunt, R. Rebello, M. Schuelein, INTEL Corp., Chandler, AZ

2:35 Advances in HCMOS Array Development 447D. Soderman, LSI Logic Corp., Milpitas, CA

3:00 A Highly-Automated Top-down Layout Design System for Hierarchical Custom VLSIs 452

K. Ueda, H. Kitazawa, T. Adachi, Nippon Telegraph & Telephone Public Corp., Kanagawa, Japan

3:25 SCUIDS: A Semi-Custom Integrated Design System 456W. H. Kao, K. H. Wu, Xerox Corp., El Segundo, CA

3:50 The Semi-Custom System Design ProcessS. H. Cravens, R. D. Weir, NCR Corp., Fort Collins, CO

460

4:15 Design Methodology for Reconfigurable Module-Structured VLSI 464

K. Iwasaki, N. Yamaguchi, Y. Hagiwara, T. Shimura, T. Funabashi, K. Minorikawa, Hitachi, Ltd., Tokyo, Japan

CONTENTS

WEDNESDAY AFTERNOON Rose Room PAGE

ANALOG SEMICUSTOM TECHNIQUES 469

Chairman: David M. Lewis

Co-chairman: Alan B. Grebene

1:45 Subcircuits on Linear Arrays—A New Array Topology 470P. J. King, Linear Technology Inc., Burlington, Ont., Canada

2:10 An Advanced Analog Array for Rapid Implementation of Semi-Custom Integrated Circuit Designs 475P. A. Crolla, D. Culmer, Micro Linear Corp., San Jose, CA

2:35 Analog LSI Design with CMOS Standard Cells 479T. Pletersek*, J. Trontelj*, L. Trontelj*, Y-J Sun**, I. Jones**, G. Shenton**, Univ. of Ljubljana, Ljubljana, Yugoslavia*, Intl.

Microelectronic Prods., San Jose, CA**

3:00 A Standard Cell Approach to Analog IC Design Utilizing Subthreshold Building Blocks 484T. A. Teel, D. A. Wayne, Medtronic/Micro-Rel, Inc., Tempe, AZ

3:25 Combining Analog and Digital Using Standard Cells 491

D. G. Maeding, M. Negahban-Hagh, B. Klein, Silicon Systems, Inc., Tustin, CA

3:50 Design of an Analog Data Acquisition System Using Silicon Compiler Techniques 495G. H. Allwine, Gonzaga University Spokane, WA

4:15 AIDE2: An Automated Analog IC Design System 498P. E. Allen*, E. R. Macaluso**, S. F. Bily***, A. Nedungadi***, Georgia Inst, of Tech., Atlanta, GA*, VRIS, Austin TX**,Texas A&M Univ., College Station, TX***

WEDNESDAY AFTERNOON Pavilion PAGE

CAD-DEVICE LEVEL MODELING 503

Chairman: Peter LloydCo-chairman: Savvas G. Chamberlain

1:45 Latchup-Free Substrate Bias Generators in CMOS 504R. A. Piro, F. R. Sporck, M. P. DuPasquier, IBM, Essex Junction, VT

2:10 A One-Dimensional Approach to the Analysis of Short-Channel Enhancement-Mode MOSFET's 505C. Turchetti, G. Masetti, Univ. of Ancona, Ancona, Italy

35 Modeling the Effects of Mobility Degradation on the Intrinsic Internodal Capacitances of Short-Channel 509MOSFETs

J. S. Kueng, Univ. of Minnesota, Minneapolis, MN

3:00 MOSFET Parameter Optimization for Accurate Output Conductance Modeling 512J. L. D'Arcy, R. C. Rennick, AT&T Bell Labs, Allentown, PA

CONTENTS

WEDNESDAY AFTERNOON Pavilion PAGE

3:25 A Highly Automated Integrated Modeling System: MECCA 516

E. J. Prendergast, P. Lloyd, AT&T Bell Labs, Allentown, PA

3:50 A Methodology for Optimal Test Structure Design 520

I. Chen, A. J. Strojwas, Carnegie-Mellon Univ., Pittsburgh, PA

+