D DR DRAFT RAFT AFT UM D DRAFT P89LPC9331/9341… · 2009. 2. 24. · P89LPC9331/9341/9351 User manual 1. Introduction The P89LPC9331/9341/9351 are single-chip microcontrollers

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UMP89LPC9331/9341/9351 User manualRev. 01.xx — 5 February 2009 User manual

Document informationInfo ContentKeywords P89LPC9331/9341/9351Abstract Technical information for the P89LPC9331/9341/9351 device

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NXP Semiconductors UMP89LPC9331/9341/9351 User manual

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Revision historyRev Date Description

01 20081118 Initial version.

© NXP B.V. 2009. All rights reserved.

User manual Rev. 01.xx — 5 February 2009 2 of 172

Contact informationFor more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

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1. Introduction

The P89LPC9331/9341/9351 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC9331/9341/9351 are based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC9331/9341/9351 in order to reduce component count, board space, and system cost.

Product Comparison Overview

1.1 Pin configuration

Table 1. Product comparison overviewDevice Flash

MemorySector size

ADC1 ADC0 PGA0 PGA1 Temp Sensor

CCU DATA EEPROM

P89LPC9331 4 kB 1 kB X X - - X - -

P89LPC9341 4 kB 1 kB X X - - X - -

P89LPC9351 8 kB 1 kB X X X X X X X

Fig 1. P89LPC9331/9341 TSSOP28 pin configuration

P89LPC9331FDH/P89LPC9341FDH

002aae462

1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

15

18

17

20

19

22

21

24

23

26

25

28

27

P2.0/AD03/DAC0

P2.1/AD02

P0.0/CMP2/KBI0/AD01

P1.7/AD00

P1.6

P1.5/RST

VSS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

P2.7

P2.6

P0.1/CIN2B/KBI1/AD10

P0.2/CIN2A/KBI2/AD11


P0.4/CIN1A/KBI4/DAC1/AD13

P0.5/CMPREF/KBI5

VDD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS



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Fig 2. P89LPC9351 TSSOP28 pin configuration

Fig 3. PLCC28 pin configuration

P89LPC9351FDH

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

15

18

17

20

19

22

21

24

23

26

25

28

27

P2.0/ICB/DAC0/AD03

P2.1/OCD/AD02

P0.0/CMP2/KBI0/AD01

P1.7/OCC/AD00

P1.6/OCB

P1.5/RST

VSS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

P2.7/ICA

P2.6/OCA





P0.5/CMPREF/KBI5

VDD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS

P89LPC9351FA

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5

6

7

8

9

10

11

25

24

23

22

21

20

19

12 13 14 15 16 17 18

4 3 2 1 28 27 26

P1.6/OCB

P1.5/RST

VSS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.

7/O

CC

/AD

00

P0.

0/C

MP

2/K

BI0

/AD

01

P2.

1/O

CD

/AD

02

P2.

0/IC

B/D

AC

0/A

D03

P2.

7/IC

A

P2.

6/O

CA

P0.

1/C

IN2B

/KB

I1/A

D10




P0.5/CMPREF/KBI5

VDD

P0.6/CMP1/KBI6

P0.7/T1/KBI7

P1.

2/T

0/S

CL

P2.

2/M

OS

I

P2.

3/M

ISO

P2.

4/S

S

P2.

5/S

PIC

LK

P1.

1/R

XD

P1.

0/T

XD



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1.2 Pin description

Table 2. Pin descriptionSymbol Pin Type Description

PLCC28, TSSOP28

P0.0 to P0.7 I/O Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 “Port configurations” for details.The Keypad Interrupt feature operates with Port 0 pins.All pins have Schmitt trigger inputs.Port 0 also provides various special functions as described below:

P0.0/CMP2/KBI0/AD01

3 I/O P0.0 — Port 0 bit 0.O CMP2 — Comparator 2 outputI KBI0 — Keyboard input 0.I AD01 — ADC0 channel 1 analog input.


26 I/O P0.1 — Port 0 bit 1.I CIN2B — Comparator 2 positive input B.I KBI1 — Keyboard input 1.I AD10 — ADC1 channel 0 analog input.


25 I/O P0.2 — Port 0 bit 2.I CIN2A — Comparator 2 positive input A.I KBI2 — Keyboard input 2.I AD11 — ADC1 channel 1 analog input.


24 I/O P0.3 — Port 0 bit 3. High current source.I CIN1B — Comparator 1 positive input B.I KBI3 — Keyboard input 3.I AD12 — ADC1 channel 2 analog input.


23 I/O P0.4 — Port 0 bit 4. High current source.I CIN1A — Comparator 1 positive input A.I KBI4 — Keyboard input 4.O DAC1 — Digital-to-analog converter output 1.I AD13 — ADC1 channel 3 analog input.

P0.5/CMPREF/ KBI5

22 I/O P0.5 — Port 0 bit 5. High current source.I CMPREF — Comparator reference (negative) input.I KBI5 — Keyboard input 5.

P0.6/CMP1/KBI6 20 I/O P0.6 — Port 0 bit 6. High current source.O CMP1 — Comparator 1 output.I KBI6 — Keyboard input 6.

P0.7/T1/KBI7 19 I/O P0.7 — Port 0 bit 7. High current source.I/O T1 — Timer/counter 1 external count input or overflow output.I KBI7 — Keyboard input 7.



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[1]Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected. Each of the configurable port pins are programmed independently. Refer to Section 5.1 “Port configurations” for details. P1.2 to P1.3 are open drain when used as outputs. P1.5 is input only.All pins have Schmitt trigger inputs.Port 1 also provides various special functions as described below:

P1.0/TXD 18 I/O P1.0 — Port 1 bit 0.O TXD — Transmitter output for serial port.

P1.1/RXD 17 I/O P1.1 — Port 1 bit 1.I RXD — Receiver input for serial port.

P1.2/T0/SCL 12 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).I/O T0 — Timer/counter 0 external count input or overflow output (open-drain when

used as output).

I/O SCL — I2C-bus serial clock input/output.P1.3/INT0/SDA 11 I/O P1.3 — Port 1 bit 3 (open-drain when used as output).

I INT0 — External interrupt 0 input.I/O SDA — I2C-bus serial data input/output.

P1.4/INT1 10 I/O P1.4 — Port 1 bit 4. High current source.I INT1 — External interrupt 1 input.

P1.5/RST 6 I P1.5 — Port 1 bit 5 (input only).I RST — External Reset input during power-on or if selected via UCFG1. When

functioning as a reset input, a LOW on this pin resets the microcontroller, causing I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode.

P1.6/OCB 5 I/O P1.6 — Port 1 bit 6. High current source.O OCB — Output Compare B.(P89LPC9351)

P1.7/OCC/AD00 4 I/O P1.7 — Port 1 bit 7. High current source.O OCC — Output Compare C.(P89LPC9351)I AD00 — ADC0 channel 0 analog input.

P2.0 to P2.7 I/O Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset Port 2 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 “Port configurations” for details.All pins have Schmitt trigger inputs.Port 2 also provides various special functions as described below:

P2.0/ICB/DAC0/AD03

1 I/O P2.0 — Port 2 bit 0.I ICB — Input Capture B.(P89LPC9351)O DAC0 — Digital-to-analog converter output.I AD03 — ADC0 channel 3 analog input.

Table 2. Pin description …continuedSymbol Pin Type Description

PLCC28, TSSOP28



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[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

P2.1/OCD/AD02 2 I/O P2.1 — Port 2 bit 1.O OCD — Output Compare D.(P89LPC9351)I AD02 — ADC0 channel 2 analog input.

P2.2/MOSI 13 I/O P2.2 — Port 2 bit 2.I/O MOSI — SPI master out slave in. When configured as master, this pin is output;

when configured as slave, this pin is input.

P2.3/MISO 14 I/O P2.3 — Port 2 bit 3.I/O MISO — When configured as master, this pin is input, when configured as slave,

this pin is output.

P2.4/SS 15 I/O P2.4 — Port 2 bit 4.I SS — SPI Slave select.

P2.5/SPICLK 16 I/O P2.5 — Port 2 bit 5.I/O SPICLK — SPI clock. When configured as master, this pin is output; when

configured as slave, this pin is input.

P2.6/OCA 27 I/O P2.6 — Port 2 bit 6.O OCA — Output Compare A.(P89LPC9351)

P2.7/ICA 28 I/O P2.7 — Port 2 bit 7.I ICA — Input Capture A.(P89LPC9351)

P3.0 to P3.1 I/O Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset Port 3 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to Section 5.1 “Port configurations” for details.All pins have Schmitt trigger inputs.Port 3 also provides various special functions as described below:

P3.0/XTAL2/ CLKOUT

9 I/O P3.0 — Port 3 bit 0.O XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is

selected via the flash configuration.

O CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6). It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer.

P3.1/XTAL1 8 I/O P3.1 — Port 3 bit 1.I XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when

selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer.

VSS 7 I Ground: 0 V reference. VDD 21 I Power supply: This is the power supply voltage for normal operation as well as

Idle and Power-down modes.

Table 2. Pin description …continuedSymbol Pin Type Description

PLCC28, TSSOP28



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1.3 Logic symbols

Fig 4. P89LPC9331/9341 logic symbol

VDD VSS

PORT 0

PORT 3

TXDRXDT0INT0INT1RST

SCLSDA

002aae461

CMP2CIN2BCIN2ACIN1BCIN1A

CMPREFCMP1

T1

XTAL2

XTAL1

KBI0KBI1KBI2KBI3KBI4KBI5KBI6KBI7

DAC1

MOSIMISOSSSPICLK

AD10AD11AD12AD13

AD01

PORT 1

AD00

PORT 2

P89LPC9331/P89LPC9341 AD03

AD02DAC0CLKOUT

Fig 5. P89LPC9351 logic symbol

VDD VSS

PORT 0

PORT 3

TXDRXDT0INT0INT1RST

SCLSDA

002aad556

CMP2CIN2BCIN2ACIN1BCIN1A

CMPREFCMP1

T1

XTAL2

XTAL1

KBI0KBI1KBI2KBI3KBI4KBI5KBI6KBI7

DAC1

MOSIMISOSSSPICLK

AD10AD11AD12AD13

AD01

PORT 1

PORT 2

P89LPC9351

OCBOCC

ICBOCD

OCAICA

AD00

AD03AD02

DAC0CLKOUT



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1.4 Block diagram

(1) P89LPC9351(2) PGA1 on P89LPC9351(3) PGA0 on P89LPC9351

Fig 6. Block diagram

ACCELERATED 2-CLOCK 80C51 CPU

4 kB/8 kBCODE FLASH

256-BYTEDATA RAM

PORT 2CONFIGURABLE I/Os



KEYPADINTERRUPT

PROGRAMMABLEOSCILLATOR DIVIDER

CPUclock

CONFIGURABLEOSCILLATOR

ON-CHIP RCOSCILLATOR WITH CLOCK

DOUBLER

internal bus

POWER MONITOR(POWER-ON RESET, BROWNOUT RESET)

002aad555

UART

ANALOGCOMPARATORS

512-BYTEAUXILIARY RAM(1)

I2C-BUS

512-BYTEDATA EEPROM(1)


CCU (CAPTURE/COMPARE UNIT)(1)

P89LPC9331/9341/9351

WATCHDOG TIMERAND OSCILLATOR

TIMER 0TIMER 1

REAL-TIME CLOCK/SYSTEM TIMER

SPI

ADC1/DAC1(2)

ADC0/TEMPSENSOR/DAC0(3)

P3[1:0]

P2[7:0]

P1[7:0]

P0[7:0]

TXDRXD

SCLSDA

T0T1

CMP2CIN2BCIN2ACMP1CIN1ACIN1B

OCAOCBOCCOCDICA

AD10AD11AD12AD13DAC1

AD00AD01AD02AD03DAC0

ICB

SPICLKMOSIMISOSS

CRYSTALOR

RESONATOR XTAL2

XTAL1



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1.5 Special function registersRemark: SFR accesses are restricted in the following ways:

• User must not attempt to access any SFR locations not defined.• Accesses to any defined SFR locations must be strictly for the functions for the SFRs.• SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.



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Table 3. Special function registers-P89LPC9331/9341* indicates SFRs that are bit addressable.

Name Description SFR Bit functions and addresses Reset valueLSB Hex BinaryE0

00 0000 0000

ADCS00 00 0000 0000

ADCS10 00 0000 0000

ADI00 00 0000 0000

SCAN0 00 0000 0000

BSA0 00 000x 0000

FF 1111 1111

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

FF 1111 1111

00 0000 0000

00 0000 0000

© N

XP B.V. 2009. All rights reserved.

addr. MSBBit address E7 E6 E5 E4 E3 E2 E1

ACC* Accumulator E0H

ADCON0 A/D control register 0

8EH ENBI0 ENADCI0 TMM0 EDGE0 ADCI0 ENADC0 ADCS01


97H ENBI1 ENADCI1 TMM1 EDGE1 ADCI1 ENADC1 ADCS11

ADINS A/D input select

A3H ADI13 ADI12 ADI11 ADI10 ADI03 ADI02 ADI01

ADMODA A/D mode register A

C0H BNDI1 BURST1 SCC1 SCAN1 BNDI0 BURST0 SCC0

ADMODB A/D mode register B

A1H CLK2 CLK1 CLK0 INBND0 ENDAC1 ENDAC0 BSA1

AD0BH A/D_0 boundary high register

BBH

AD0BL A/D_0 boundary low register

A6H

AD0DAT0 A/D_0 data register 0

C5H


C6H


C7H


F4H


C4H


BCH


D5H

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00 0000 0000

00 0000 0000

00 0000 0000

DPS 00 0000 00x0

F000 0000 0000

00 0000 0000

00 0000 0000

BRGEN 00[2] xxxx xx00

CMF1 00[1] xx00 0000

CMF2 00[1] xx00 0000

00 0000 0000

00 0000 0000

00 0000 0000

Table 3. Special function registers-P89LPC9331/9341 …continued* indicates SFRs that are bit addressable.

Name Description SFR Bit functions and addresses Reset valueLSB Hex Binary

© N



D6H


D7H


F5H

AUXR1 Auxiliary function register

A2H CLKLP EBRR ENT1 ENT0 SRST 0 -

Bit address F7 F6 F5 F4 F3 F2 F1B* B register F0H

BRGR0[2] Baud rate generator 0 rate low

BEH

BRGR1[2] Baud rate generator 0 rate high

BFH

BRGCON Baud rate generator 0 control

BDH - - - - - - SBRGS

CMP1 Comparator 1 control register

ACH - - CE1 CP1 CN1 OE1 CO1


ADH - - CE2 CP2 CN2 OE2 CO2

DIVM CPU clock divide-by-M control

95H

DPTR Data pointer (2 bytes)

DPH Data pointer high

83H

DPL Data pointer low

82H

addr. MSB

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00 0000 0000

00 0000 0000

OI 70 0111 0000

FMCMD.0

00 0000 0000

GC 00 0000 0000

D8CRSEL 00 x000 00x0

00 0000 0000

00 0000 0000

0 F8 1111 1000

A8EX0 00 0000 0000

E8



© N


FMADRH Program flash address high

E7H

FMADRL Program flash address low

E6H

FMCON Program flash control (Read)

E4H BUSY - - - HVA HVE SV

Program flash control (Write)

E4H FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.1

FMDATA Program flash data

E5H

I2ADR I2C-bus slave address register

DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0

Bit address DF DE DD DC DB DA D9I2CON* I2C-bus control

registerD8H - I2EN STA STO SI AA -

I2DAT I2C-bus data register

DAH

I2SCLH Serial clock generator/SCL duty cycle register high

DDH

I2SCLL Serial clock generator/SCL duty cycle register low

DCH

I2STAT I2C-bus status register

D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0

Bit address AF AE AD AC AB AA A9IEN0* Interrupt

enable 0A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0

Bit address EF EE ED EC EB EA E9

addr. MSB

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EI2C 00[1] 00x0 0000

B8PX0 00[1] x000 0000

PX0H 00[1] x000 0000

F8PI2C 00[1] 00x0 0000

PI2CH 00[1] 00x0 0000

KBIF 00[1] xxxx xx00

00 0000 0000

FF 1111 1111

80CMP2/KB0

[1]

90TXD [1]

A0- [1]

B0XTAL2 [1]

(P0M1.0) FF[1] 1111 1111

(P0M2.0) 00[1] 0000 0000



© N


IEN1* Interrupt enable 1

E8H EAD EST - - ESPI EC EKBI

Bit address BF BE BD BC BB BA B9IP0* Interrupt

priority 0B8H - PWDRT PBO PS/PSR PT1 PX1 PT0

IP0H Interrupt priority 0 high

B7H - PWDRTH PBOH PSH/ PSRH

PT1H PX1H PT0H

Bit address FF FE FD FC FB FA F9IP1* Interrupt

priority 1F8H PAD PST - - PSPI PC PKBI


F7H PADH PSTH - - PSPIH PCH PKBIH

KBCON Keypad control register

94H - - - - - - PATN_SEL

KBMASK Keypad interrupt mask register

86H

KBPATN Keypad pattern register

93H

Bit address 87 86 85 84 83 82 81P0* Port 0 80H T1/KB7 CMP1

/KB6CMPREF

/KB5CIN1A/KB4

CIN1B/KB3

CIN2A/KB2

CIN2B/KB1

Bit address 97 96 95 94 93 92 91P1* Port 1 90H - - RST INT1 INT0/SDA T0/SCL RXD

Bit address A7 A6 A5 A4 A3 A2 A1P2* Port 2 A0H - - SPICLK SS MISO MOSI -

Bit address B7 B6 B5 B4 B3 B2 B1P3* Port 3 B0H - - - - - - XTAL1

P0M1 Port 0 output mode 1

84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1)


85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1)

addr. MSB

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(P1M1.0) D3[1] 11x1 xx11

(P1M2.0) 00[1] 00x0 xx00

(P2M1.0) FF[1] 1111 1111

(P2M2.0) 00[1] 0000 0000

(P3M1.0) 03[1] xxxx xx11

(P3M2.0) 00[1] xxxx xx00

PMOD0 00 0000 0000

- 00[1] 0000 0000

D0P 00 0000 0000

- 00 xx00 000x

R_EX [3]

RTCEN 60[1][6] 011x xx00

00[6] 0000 0000

00[6] 0000 0000

00 0000 0000

00 0000 0000



© N



91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1)


92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1)


A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1)


A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1)


B1H - - - - - - (P3M1.1)


B2H - - - - - - (P3M2.1)

PCON Power control register

87H SMOD1 SMOD0 - BOI GF1 GF0 PMOD1

PCONA Power control register A

B5H RTCPD - VCPD ADPD I2PD SPPD SPD

Bit address D7 D6 D5 D4 D3 D2 D1PSW* Program status

wordD0H CY AC F0 RS1 RS0 OV F1

PT0AD Port 0 digital input disable

F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1

RSTSRC Reset source register

DFH - BOIF BOF POF R_BK R_WD R_SF

RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC

RTCH RTC register high

D2H

RTCL RTC register low

D3H

SADDR Serial port address register

A9H

SADEN Serial port address enable

B9H

addr. MSB

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xx xxxx xxxx

98RI 00 0000 0000

STINT 00 0000 0000

07 0000 0111

SPR0 04 0000 0100

- 00 00xx xxxx

00 0000 0000

T0M2 00 xxx0 xxx0

88IT0 00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

T0M0 00 0000 0000

TRIM.0 [5][6]

WDCLK [4][6]



© N


SBUF Serial Port data buffer register

99H

Bit address 9F 9E 9D 9C 9B 9A 99SCON* Serial port

control98H SM0/FE SM1 SM2 REN TB8 RB8 TI

SSTAT Serial port extended status register

BAH DBMOD INTLO CIDIS DBISEL FE BR OE

SP Stack pointer 81H

SPCTL SPI control register

E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1

SPSTAT SPI status register

E1H SPIF WCOL - - - - -

SPDAT SPI data register

E3H

TAMOD Timer 0 and 1 auxiliary mode

8FH - - - T1M2 - - -

Bit address 8F 8E 8D 8C 8B 8A 89TCON* Timer 0 and 1

control88H TF1 TR1 TF0 TR0 IE1 IT1 IE0

TH0 Timer 0 high 8CH

TH1 Timer 1 high 8DH

TL0 Timer 0 low 8AH

TL1 Timer 1 low 8BH

TMOD Timer 0 and 1 mode

89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1

TRIM Internal oscillator trim register

96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1

WDCON Watchdog control register

A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF

addr. MSB

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table.

e cleared except POF and BOF; the

eset and is logic 0 after power-on reset.

ization of the TRIM register.

FF 1111 1111



© N


[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredic

[3] The RSTSRC register reflects the cause of the P89LPC9331/9341 reset except BOIF bit. Upon a power-up reset, all reset source flags arpower-on reset value is x011 0000.

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog rOther resets will not affect WDTOF.

[5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initial

[6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.

WDL Watchdog load C1H

WFEED1 Watchdog feed 1

C2H

WFEED2 Watchdog feed 2

C3H

addr. MSB

DRAFT

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and MOVX @DPTR,A instructions are

G1.0 and reset value of CLKDBL bit

Table 4. Extended special function registers-P89LPC9331/9341Name Description SFR

addr.Bit functions and addresses Reset value

LSB Hex BinaryG1 BOICFG0 [2]

1 FOSC0 [3]

- 00 0000 0000

00 0000 0000

00 0000 0000

© N


[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTRused to access these extended SFRs.

[2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset.

[3] CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFcomes from UCFG2.7.

MSBBODCFG BOD

configuration register

FFC8H - - - - - - BOICF

CLKCON CLOCK Control register

FFDEH CLKOK - - XTALWD CLKDBL FOSC2 FOSC

TPSCON Temperature sensor control register

FFCAH - - - - TSEL1 TSEL0 -

RTCDATH Real-time clock data register high

FFBFH

RTCDATL Real-time clock data register low

FFBEH

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Table 5. Special function registers-P89LPC9351* indicates SFRs that are bit addressable.

Name Description SFR Bit functions and addresses Reset valueLSB Hex BinaryE0

00 0000 0000

ADCS00 00 0000 0000

ADCS10 00 0000 0000

ADI00 00 0000 0000

SCAN0 00 0000 0000

BSA0 00 000x 0000

FF 1111 1111

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

FF 1111 1111

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

© N


addr. MSBBit address E7 E6 E5 E4 E3 E2 E1

ACC* Accumulator E0H


8EH ENBI0 ENADCI0 TMM0 EDGE0 ADCI0 ENADC0 ADCS01


97H ENBI1 ENADCI1 TMM1 EDGE1 ADCI1 ENADC1 ADCS11

ADINS A/D input select A3H ADI13 ADI12 ADI11 ADI10 ADI03 ADI02 ADI01

ADMODA A/D mode register A

C0H BNDI1 BURST1 SCC1 SCAN1 BNDI0 BURST0 SCC0

ADMODB A/D mode register B

A1H CLK2 CLK1 CLK0 INBND0 ENDAC1 ENDAC0 BSA1


BBH


A6H


C5H


C6H


C7H


F4H


C4H


BCH


D5H


D6H


D7H

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00 0000 0000

DPS 00 0000 00x0

F000 0000 0000

00 0000 0000

00 0000 0000

BRGEN 00[2] xxxx xx00

OCMA0 00 0000 0000

OCMB0 00 0000 0000

OCMC0 00 xxxx x000

OCMD0 00 xxxx x000

CMF1 00[1] xx00 0000

CMF2 00[1] xx00 0000

0 EADR8 08 00001000

00 0000 0000

00 0000 0000



© N



F5H

AUXR1 Auxiliary function register

A2H CLKLP EBRR ENT1 ENT0 SRST 0 -

Bit address F7 F6 F5 F4 F3 F2 F1B* B register F0H

BRGR0[2] Baud rate generator 0 rate low

BEH

BRGR1[2] Baud rate generator 0 rate high

BFH

BRGCON Baud rate generator 0 control

BDH - - - - - - SBRGS

CCCRA Capture compare A control register

EAH ICECA2 ICECA1 ICECA0 ICESA ICNFA FCOA OCMA1

CCCRB Capture compare B control register

EBH ICECB2 ICECB1 ICECB0 ICESB ICNFB FCOB OCMB1

CCCRC Capture compare C control register

ECH - - - - - FCOC OCMC1

CCCRD Capture compare D control register

EDH - - - - - FCOD OCMD1


ACH - - CE1 CP1 CN1 OE1 CO1


ADH - - CE2 CP2 CN2 OE2 CO2

DEECON Data EEPROM control register

F1H EEIF HVERR ECTL1 ECTL0 - EWERR1 EWERR

DEEDAT Data EEPROM data register

F2H

DEEADR Data EEPROM address register

F3H

addr. MSB

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00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

OI 70 0111 0000

1 FMCMD.0

00 0000 0000

GC 00 0000 0000

D8CRSEL 00 x000 00x0

00 0000 0000

00 0000 0000

0 F8 1111 1000



© N


DIVM CPU clock divide-by-M control

95H

DPTR Data pointer (2 bytes)

DPH Data pointer high 83H

DPL Data pointer low 82H

FMADRH Program flash address high

E7H

FMADRL Program flash address low

E6H

FMCON Program flash control (Read)

E4H BUSY - - - HVA HVE SV

Program flash control (Write)

E4H FMCMD.7 FMCMD.6 FMCMD.5 FMCMD.4 FMCMD.3 FMCMD.2 FMCMD.

FMDATA Program flash data

E5H

I2ADR I2C-bus slave address register

DBH I2ADR.6 I2ADR.5 I2ADR.4 I2ADR.3 I2ADR.2 I2ADR.1 I2ADR.0

Bit address DF DE DD DC DB DA D9I2CON* I2C-bus control

registerD8H - I2EN STA STO SI AA -

I2DAT I2C-bus data register

DAH

I2SCLH Serial clock generator/SCL duty cycle register high

DDH

I2SCLL Serial clock generator/SCL duty cycle register low

DCH

I2STAT I2C-bus status register

D9H STA.4 STA.3 STA.2 STA.1 STA.0 0 0

addr. MSB

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00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

A8EX0 00 0000 0000

E8EI2C 00[1] 00x0 0000

B8PX0 00[1] x000 0000

PX0H 00[1] x000 0000

F8PI2C 00[1] 00x0 0000

PI2CH 00[1] 00x0 0000

KBIF 00[1] xxxx xx00

00 0000 0000

FF 1111 1111

00 0000 0000

00 0000 0000

00 0000 0000



© N


ICRAH Input capture A register high

ABH

ICRAL Input capture A register low

AAH

ICRBH Input capture B register high

AFH

ICRBL Input capture B register low

AEH

Bit address AF AE AD AC AB AA A9IEN0* Interrupt enable 0 A8H EA EWDRT EBO ES/ESR ET1 EX1 ET0

Bit address EF EE ED EC EB EA E9IEN1* Interrupt enable 1 E8H EADEE EST - ECCU ESPI EC EKBI

Bit address BF BE BD BC BB BA B9IP0* Interrupt priority 0 B8H - PWDRT PBO PS/PSR PT1 PX1 PT0


B7H - PWDRTH PBOH PSH/ PSRH

PT1H PX1H PT0H

Bit address FF FE FD FC FB FA F9IP1* Interrupt priority 1 F8H PADEE PST - PCCU PSPI PC PKBI


F7H PAEEH PSTH - PCCUH PSPIH PCH PKBIH

KBCON Keypad control register

94H - - - - - - PATN_SEL

KBMASK Keypad interrupt mask register

86H

KBPATN Keypad pattern register

93H

OCRAH Output compare A register high

EFH

OCRAL Output compare A register low

EEH

OCRBH Output compare B register high

FBH

addr. MSB

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00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

00 0000 0000

80CMP2/KB0

[1]

90TXD [1]

A0ICB [1]

B0XTAL2 [1]

) (P0M1.0) FF[1] 1111 1111

) (P0M2.0) 00[1] 0000 0000

) (P1M1.0) D3[1] 11x1 xx11

) (P1M2.0) 00[1] 00x0 xx00

) (P2M1.0) FF[1] 1111 1111

) (P2M2.0) 00[1] 0000 0000



© N


OCRBL Output compare B register low

FAH

OCRCH Output compare C register high

FDH

OCRCL Output compare C register low

FCH

OCRDH Output compare D register high

FFH

OCRDL Output compare D register low

FEH

Bit address 87 86 85 84 83 82 81P0* Port 0 80H T1/KB7 CMP1

/KB6CMPREF

/KB5CIN1A/KB4

CIN1B/KB3

CIN2A/KB2

CIN2B/KB1

Bit address 97 96 95 94 93 92 91P1* Port 1 90H OCC OCB RST INT1 INT0/SDA T0/SCL RXD

Bit address A7 A6 A5 A4 A3 A2 A1P2* Port 2 A0H ICA OCA SPICLK SS MISO MOSI OCD

Bit address B7 B6 B5 B4 B3 B2 B1P3* Port 3 B0H - - - - - - XTAL1


84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1


85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1


91H (P1M1.7) (P1M1.6) - (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1


92H (P1M2.7) (P1M2.6) - (P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1


A4H (P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1


A5H (P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1

addr. MSB

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) (P3M1.0) 03[1] xxxx xx11

) (P3M2.0) 00[1] xxxx xx00

PMOD0 00 0000 0000

CCUPD 00[1] 0000 0000

D0P 00 0000 0000

- 00 xx00 000x

R_EX [3]

RTCEN 60[1][6] 011x xx00

00[6] 0000 0000

00[6] 0000 0000

00 0000 0000

00 0000 0000

xx xxxx xxxx

98RI 00 0000 0000

STINT 00 0000 0000

07 0000 0111

SPR0 04 0000 0100



© N



B1H - - - - - - (P3M1.1


B2H - - - - - - (P3M2.1

PCON Power control register

87H SMOD1 SMOD0 - BOI GF1 GF0 PMOD1

PCONA Power control register A

B5H RTCPD DEEPD VCPD ADPD I2PD SPPD SPD

Bit address D7 D6 D5 D4 D3 D2 D1PSW* Program status

wordD0H CY AC F0 RS1 RS0 OV F1

PT0AD Port 0 digital input disable

F6H - - PT0AD.5 PT0AD.4 PT0AD.3 PT0AD.2 PT0AD.1

RSTSRC Reset source register

DFH - BOIF BOF POF R_BK R_WD R_SF

RTCCON RTC control D1H RTCF RTCS1 RTCS0 - - - ERTC

RTCH RTC register high D2H

RTCL RTC register low D3H

SADDR Serial port address register

A9H

SADEN Serial port address enable

B9H

SBUF Serial Port data buffer register

99H

Bit address 9F 9E 9D 9C 9B 9A 99SCON* Serial port control 98H SM0/FE SM1 SM2 REN TB8 RB8 TI

SSTAT Serial port extended status register

BAH DBMOD INTLO CIDIS DBISEL FE BR OE

SP Stack pointer 81H

SPCTL SPI control register

E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1

addr. MSB

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- 00 00xx xxxx

00 0000 0000

T0M2 00 xxx0 xxx0

88IT0 00 0000 0000

TMOD20 00 0000 0000

PLLDV.0 00 0xxx 0000

00 0000 0000

00 0000 0000

00 0000 0000

TICIE2A 00 0000 0x00

TICF2A 00 0000 0x00

1 ENCINT.0 00 xxxx x000

00 0000 0000

00 0000 0000

00 0000 0000

T0M0 00 0000 0000

00 0000 0000

00 0000 0000

.1 TPCR2H.0 00 xxxx xx00



© N


SPSTAT SPI status register

E1H SPIF WCOL - - - - -

SPDAT SPI data register E3H

TAMOD Timer 0 and 1 auxiliary mode

8FH - - - T1M2 - - -

Bit address 8F 8E 8D 8C 8B 8A 89TCON* Timer 0 and 1

control88H TF1 TR1 TF0 TR0 IE1 IT1 IE0

TCR20* CCU control register 0

C8H PLEEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21

TCR21 CCU control register 1

F9H TCOU2 - - - PLLDV.3 PLLDV.2 PLLDV.1

TH0 Timer 0 high 8CH

TH1 Timer 1 high 8DH

TH2 CCU timer high CDH

TICR2 CCU interrupt control register

C9H TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A - TICIE2B

TIFR2 CCU interrupt flag register

E9H TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A - TICF2B

TISE2 CCU interrupt status encode register

DEH - - - - - ENCINT.2 ENCINT.

TL0 Timer 0 low 8AH

TL1 Timer 1 low 8BH

TL2 CCU timer low CCH

TMOD Timer 0 and 1 mode

89H T1GATE T1C/T T1M1 T1M0 T0GATE T0C/T T0M1

TOR2H CCU reload register high

CFH

TOR2L CCU reload register low

CEH

TPCR2H Prescaler control register high

CBH - - - - - - TPCR2H

addr. MSB

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table.

red except POF and BOF; the power-on

eset and is logic 0 after power-on reset.

ization of the TRIM register.

1 TPCR2L.0 00 0000 0000

TRIM.0 [5][6]

WDCLK [4][6]

FF 1111 1111



© N


[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredic

[3] The RSTSRC register reflects the cause of the P89LPC9351 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleareset value is x011 0000.

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog rOther resets will not affect WDTOF.

[5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initial

[6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.

TPCR2L Prescaler control register low

CAH TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.

TRIM Internal oscillator trim register

96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1

WDCON Watchdog control register

A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF

WDL Watchdog load C1H

WFEED1 Watchdog feed 1 C2H

WFEED2 Watchdog feed 2 C3H

addr. MSB

DRAFT

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G1.0 and reset value of CLKDBL bit

value. Other resets will not cause

Table 6. Extended special function registers-P89LPC9351Name Description SFR

addr.Bit functions and addresses Reset value

LSB Hex BinaryG1 BOICFG0 [2]

1 FOSC0 [3] 1000 xxxx

11 PGAG10 00 0000 0000

PGAENOFF1

00 0000 0000

M1 8XTRIM0 [4]

M1 2XTRIM0 [4]

01 PGAG00 00 0000 0000

PGAENOFF0

00 0000 0000

M1 8XTRIM0 [4]

M1 2XTRIM0 [4]

00 0000 0000

00 0000 0000

© N


[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTRused to access these extended SFRs.

[2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset.

[3] CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFcomes from UCFG2.7.

[4] On power-on reset and watchdog reset, the PGAxTRIM8X16X and PGAxTRIM2X4X registers are initialized with a factory preprogrammedinitialization.

MSBBODCFG BOD

configuration register

FFC8H - - - - - - BOICF

CLKCON CLOCK Control register

FFDEH CLKOK - - XTALWD CLKDBL FOSC2 FOSC

PGACON1 PGA1 control register

FFE1H ENPGA1 PGASEL11

PGASEL10

PGATRIM1

- - PGAG

PGACON1B PGA1 control register B

FFE4H - - - - - - -

PGA1TRIM8X16X

PGA1 trim register

FFE3H 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIM0 8XTRIM3 8XTRIM2 8XTRI

PGA1TRIM2X4X PGA1 trim register

FFE2H 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIM0 2XTRIM3 2XTRIM2 2XTRI

PGACON0 PGA0 control register

FFCAH ENPGA0 PGASEL01

PGASEL00

PGATRIM0

TSEL1 TSEL0 PGAG

PGACON0B PGA0 control register B

FFCEH - - - - - - -

PGA0TRIM8X16X

PGA0 trim register

FFCDH 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIM0 8XTRIM3 8XTRIM2 8XTRI

PGA0TRIM2X4X PGA0 trim register

FFCCH 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIM0 2XTRIM3 2XTRIM2 2XTRI

RTCDATH Real-time clock data register high

FFBFH

RTCDATL Real-time clock data register low

FFBEH

DRAFT

DRAFT DRAFT DR

DRAFT DRAFT DRAFRAF

DRAFT DRAFT DRAF

FT D

DRAFT DRAFT DRAF

DRA


T DT DRAFT DRA

T DRAFT DRAFT DRAFT

1.6 Memory organization

The various P89LPC9331/9341/9351 memory spaces are as follows:

DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.SFR — Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.XDATA — ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC9351 has 512 bytes of on-chip XDATA memory, plus extended SFRs located in XDATA.-CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9331/9341/9351 has 4 kB/8 kB of on-chip Code memory.

The P89LPC9351 also has 512 bytes of on-chip Data EEPROM that is accessed via SFRs (see Section Section 18 “Data EEPROM (P89LPC9351)”).

(1) ISP code is located at the end of sector 3 on the P89LPC9331 and at the end of sector 7 on the P89LPC9341/9351.

Fig 7. P89LPC9331/9341/9351 memory map

002aae090

0000h

03FFh0400h

07FFh0800h

0BFFh0C00h

0FFFh

SECTOR 0

SECTOR 1

SECTOR 2

SECTOR 3

1000h

13FFh1400h

17FFh1800h

1BFFh1C00h

1E00h

1FFFh

SECTOR 4

SECTOR 5

SECTOR 6

FFEFh

FF00h IAP entry-points

SECTOR 7

ISP CODE(512B)(1)

SPECIAL FUNCTIONREGISTERS

(DIRECTLY ADDRESSABLE)

128 BYTES ON-CHIPDATA MEMORY (STACK,

DIRECT AND INDIR. ADDR.)

4 REG. BANKS R[7:0]

data memory(DATA, IDATA)

data EEPROM

DATA

128 BYTES ON-CHIPDATA MEMORY (STACK

AND INDIR. ADDR.)

IDATA (incl. DATA)FFEFh FFh

80h

7Fh

00h

FF1Fh

FF00h

entry points for:-51 ASM. code-C code

IDATA routines

1FFFh

1E00h

entry points for:-UART (auto-baud)-I2C, SPI, etc.(1)

ISP serial loader

entrypoints

read-protectedIAP calls only

DATA EEPROM(512 BYTES)

[SFR ACCESS](P89LPC9351)

01FFh

0000h

EXTENDED SFRs

FFFFh

FFB0h

RESERVED

01FFh

XDATA(512 BYTES)

(P89LPC9351)0000h



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2. Clocks

2.1 Enhanced CPUThe P89LPC9331/9341/9351 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definitionsThe P89LPC9331/9341/9351 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency (see Figure 9 and Section 2.10 “CPU Clock (CCLK) modification: DIVM register”). Note: fosc is defined as the OSCCLK frequency.CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).RCCLK — The internal 7.373 MHz RC oscillator output.The clock doubler option, when enabled, provides an output frequency of 14.746 MHz.PCLK — Clock for the various peripheral devices and is CCLK⁄2.

2.2.1 Oscillator Clock (OSCCLK)The P89LPC9351 provides several user-selectable oscillator options in generating the CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source.

2.3 Crystal oscillator optionThe crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK, RTC and WDT.

2.3.1 Low speed oscillator optionThis option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration

Table 7. Data RAM arrangementType Data RAM Size (bytes)DATA Directly and indirectly addressable memory 128

IDATA Indirectly addressable memory 256

XDATA Auxiliary (‚ÄòExternal Data‚Äô) on-chip memory that is accessed using the MOVX instructions (P89LPC9351)

512



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2.3.2 Medium speed oscillator optionThis option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

2.3.3 High speed oscillator optionThis option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration.

2.4 Clock outputThe P89LPC9331/9341/9351 supports a user-selectable clock output function on the XTAL2 / CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-time Clock and Watchdog Timer are not using the crystal oscillator as their clock source. This allows external devices to synchronize to the P89LPC9331/9341/9351. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of other bits of the TRIM register. This can be done by reading the contents of the TRIM register (into the ACC for example), modifying bit 6, and writing this result back into the TRIM register. Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

2.5 On-chip RC oscillator optionThe P89LPC9331/9341/9351 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature. (Note: the initial value is better than 1 %; please refer to the P89LPC9331/9341/9351 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency. When the clock doubler option is enabled (UCFG2.7 = 1), the output frequency is doubled. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached its specified level.

Table 8. On-chip RC oscillator trim register (TRIM - address 96h) bit allocationBit 7 6 5 4 3 2 1 0Symbol RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0

Reset 0 0 Bits 5:0 loaded with factory stored value during reset.



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2.6 Watchdog oscillator optionThe watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to ± 5 % at room temperature. This oscillator can be used to save power when a high clock frequency is not needed.

2.7 External clock input optionIn this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above 12 Mhz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached its specified level.

Table 9. On-chip RC oscillator trim register (TRIM - address 96h) bit descriptionBit Symbol Description0 TRIM.0 Trim value. Determines the frequency of the internal RC oscillator. During reset,

these bits are loaded with a stored factory calibration value. When writing to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.

1 TRIM.1

2 TRIM.2

3 TRIM.3

4 TRIM.4

5 TRIM.5

6 ENCLK when = 1, CCLK⁄2 is output on the XTAL2 pin provided the crystal oscillator is not being used.

7 RCCLK when = 1, selects the RC Oscillator output as the CPU clock (CCLK). This allows for fast switching between any clock source and the internal RC oscillator without needing to go through a reset cycle.

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals (see text).

Fig 8. Using the crystal oscillator

002aad364

XTAL1

XTAL2

quartz crystal orceramic resonator

(1)



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2.8 Clock source switching on the flyP89LPC9331/9341/9351 can implement clock switching on any sources of watchdog oscillator, 7/14MHz IRC oscillator, crystal oscillator and external clock input during code is running. CLKOK bit in register CLKCON is read only and used to indicate the clock switch status. When CLKOK is ‘0’, clock switch is processing, not completed. When CLKOK is ‘1’, clock switch is completed. When start new clock source switch, CLKOK is cleared automatically. Notice that when CLKOK is ‘0’, Writing to CLKCON register is not allowed. During reset, CLKCON register value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7.

Fig 9. Block diagram of oscillator control

÷2

002aad559

RTC

ADC1

ADC0

CPU

WDT

DIVMCCLK

UART

OSCCLK

I2C-BUS

PCLK

TIMER 0 ANDTIMER 1

HIGH FREQUENCYMEDIUM FREQUENCY

LOW FREQUENCY

XTAL1

XTAL2

RC OSCILLATORWITH CLOCK DOUBLER

WATCHDOGOSCILLATOR

(7.3728 MHz/14.7456 MHz ± 1 %) PCLK

RCCLK

SPICCU

(P89LPC9351)

32 × PLL(400 kHz ± 5 %)

Table 10. Clock control register (CLKCON - address FFDEh) bit allocationBit 7 6 5 4 3 2 1 0Symbol CLKOK - - XTALWD CLKDBL FOSC2 FOSC1 FOSC0

Reset 1 0 0 0 x x x x

Table 11. Clock control register (CLKCON - address FFDEh) bit descriptionBit Symbol Description2:0 FOSC2, FOSC1,

FOSC0CPU oscillator type selection for clock switch. See Section 2 for additional information. Combinations other than those shown in Table 12 are reserved for future use and should not be used.

3 CLKDBL Clock doubler option for clock switch. When set, doubles the output frequency of the internal RC oscillator.



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2.9 Oscillator Clock (OSCCLK) wake-up delayThe P89LPC9331/9341/9351 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60 μs to 100 μs. If the clock source is the internal RC oscillator, the delay is 200 μs to 300 μs. If the clock source is watchdog oscillator or external clock, the delay is 32 OSCCLK cycles.

2.10 CPU Clock (CCLK) modification: DIVM registerThe OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

CCLK frequency = fosc / (2N)

Where: fosc is the frequency of OSCCLK, N is the value of DIVM.

Since N ranges from 0 to 255, the CCLK frequency can be in the range of fosc to fosc/510. (for N = 0, CCLK = fosc).

This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

4 XTALWD external crystal oscillator as the clock source of watchdog timer. When =0, disable external crystal oscillator as the clock source of watchdog timer.

6:5 - reserved

7 CLKOK Clock switch completed flag. When = 1, clock switch is completed. When =0, clock switch is processing and writing to register CLKCON is not allowed.

Table 11. Clock control register (CLKCON - address FFDEh) bit description …continuedBit Symbol Description

Table 12. Oscillator type selection for clock switchFOSC[2:0] Oscillator configuration111 External clock input on XTAL1.

100 Watchdog Oscillator, 400 kHz ¬± 5 %.

011 Internal RC oscillator, 7.373 MHz ¬± 1 %.

010 Low frequency crystal, 20 kHz to 100 kHz.

001 Medium frequency crystal or resonator, 100 kHz to 4 MHz.

000 High frequency crystal or resonator, 4 MHz to 18 MHz.



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2.11 Low power selectThe P89LPC9331/9341/9351 is designed to run at 18 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.

3. A/D converter

3.1 General descriptionThe P89LPC9331/9341/9351 have two 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter modules sharing common control logic. An on-chip temperature sensor is integrated with one of the ADC modules and operates over wide temperature. In P89LPC9351, two high-speed programmable gain amplifiers (PGA) are integrated. The PGAs provide selectable gains of 2x, 4x, 8x, or 16x. A block diagram of the A/D converter is shown in Figure 10 and Figure 11. Each A/D converter consists of an 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.

3.2 A/D features

• Two 8-bit, 4-channel multiplexed input, successive approximation A/D converters • Programmable Gain Amplifier (PGA) with selectable gains of 2x, 4x, 8x, or 16x

(P89LPC9351)• On-chip wide range temperature sensor• Four result registers for each A/D• Six operating modes

– Fixed channel, single conversion mode– Fixed channel, continuous conversion mode– Auto scan, single conversion mode– Auto scan, continuous conversion mode– Dual channel, continuous conversion mode– Single step mode

• Four conversion start modes– Timer triggered start– Start immediately– Edge triggered– Dual start immediately

• 8-bit conversion time of ≥ 1.61 μs at an A/D clock of 8.0 MHz• Interrupt or polled operation• High and low boundary limits interrupt• DAC output to a port pin with high output impedance



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• Clock divider• Power down mode

Fig 10. P89LPC9331/9341 ADC block diagram

compAD00Anin00Anin01Anin02Anin03

Anin10Anin11Anin12Anin13

8

CONTROLLOGIC

AD01AD02

AD03Vref(bg)

Vsen

comp

to comparators

SAR

SAR

8

input MUX

input MUX

CCLK

002aae463

AD10

4

AD11AD12AD13

input MUX

DAC0

DAC1



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3.2.1 Programmable Gain Amplifier (PGA) (P89LPC9351)Additional PGA is integrated in each ADC module to improve the effective resolution of the ADC. A single channel can be selected for amplification. The block diagram of PGA is shown in Figure 12.

Fig 11. P89LPC9351 ADC block diagram

+

–

comp

PGA0

AD00

8

CONTROLLOGIC

AD01AD02AD03

Vref(bg)Vsen

+

–

comp

to comparators

SAR

SAR

8

input MUXAnin00Anin01Anin02Anin03

input MUX

CCLK

002aad576

PGA1

AD10

4

AD11AD12AD13

DAC0

DAC1




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Register PGACONx and PGACONxB are used for PGA configuration. The gain of PGA can be programmable to 2, 4, 8 or 16 by configuring PGAGx1 and PGAGx0 bits. PGA is enabled by setting ENPGAx bit. If ENPGAx is cleared, PGA is disabled and bypassed, which means the PGA gain value is 1.

Four external analog input signals (ADx0-ADx3) are selected by configuring PGASELx1 and PGASELx0. Temperature sensor, the internal reference voltage Vref(bg) (1.23 V ± 10 %) and analog input channel AD03 multiplex the same input channel to PGA0. Selecting temperature sensor, the internal reference voltage or AD03 input pin is achieved by configuring TSEL1 and TSEL0 bits in register PGACON0.

PGA outputs go into the 4-input multiplexer of A/D converter, allowing the amplified signal to be converted by the ADC. For PGA1, its outputs also pass to analog comparators.

3.2.1.1 PGA calibrationPGA calibration is needed when changing to different gain level. PGA offset voltage is used to guarantee the linearity of PGA output. PGAENOFFx bit in register PGACONxB is used to enable PGA offset voltage. To calibrate PGA, PGA input need to be grounded and only PGA offset voltage connects into amplifier. PGATRIMx bit in register PGACONx is used as trim enable bit. If set, PGA input is grounded for calibration mode. 4-bit trim value is used to provide the PGA offset voltage in PGA trim registers PGAxTRIM2X4X and PGAxTRIM8X16X. Then through A/D conversion, we can get PGA trim result. The trim result from the ADC then needs to be subtracted from each result of the ADC. Users need to store the trim result and do the offset subtraction by themselves.

PGA usage steps:

Fig 12. PGA block diagram

AD00AD01AD02

AD03Vref(bg)

Vsen

002aae098

PGA0 TRIMREGISTERS

MUX

MUX

MUX

4

Σ

PGAG01, PGAG00

PGASEL01,PGASEL00

TSEL1, TSEL0

AD10AD11AD12AD13

PGA1 TRIMREGISTERS

MUX

MUX4

Σ

PGASEL11,PGASEL10

PGA0 GAIN

PGAG11, PGAG10

PGA1 GAIN

PGATRIM0

PGATRIM1





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1. Select PGA gain level and input channel by configuring PGACONx register. Enable PGA by Setting ENPGAx bit.

2. Setting PGAENOFFx bit to enable PGA offset voltage.3. Setting PGATRIMx bit to ground PGA input.4. Using ADC to get converting result as PGA offset result and store it.5. Clear PGATRIMx bit to enable input signal.6. Using ADC to get converting result.7. Get amplified ADC result by subtracting PGA offset result from ADC result.

End users application can write to PGA trim registers to adjust PGA offset voltage. Increasing 4-bit trim value will increase the corresponding PGA offset voltage. During reset, 4-bits trim value is initialized to a factory pre-programmed value. To guarantee the linearity of PGA output, it is recommended not to change the PGA trim registers.

3.2.1.2 Channel selection dependencyIn auto scan mode and fixed channel single conversion mode, the PGA channel selection is dependent on the ADC channel selection, which means the PGA channel selection is tracking ADC channel selection. In other modes, the PGA channel selection is independent and can be different from the ADC channel selection. If different, the gain of the selected ADC channel is 1.

3.2.2 Temperature sensorAn on-chip wide range temperature sensor is integrated with ADC0 module. It provides temperature sensing capability of −40 °C ~ 85 °C. To get an accurate temperature value, it is necessary to get supply voltage by measuring the internal reference voltage Vref(bg) first. Temperature sensor voltage can be calculated by the following formula:

(1)

In formula (1), Aref(bg) is the A/D converting result of Vref(bg) and Asen is the A/D converting result of Vsen.

Temperature Sensor transfer function can be shown in the following formula:

Table 13. PGA trim register Register bits ContainsPGAxTRIM2X4X[3:0] trim value for 2x gain value

PGAxTRIM2X4X[7:4] trim value for 4x gain value



Table 14. PGA channel selectionADC conversion mode PGA channel selection dependencyFixed channel, continuous conversion mode PGA channel selection is independent to

ADC channel selectionDual channel, continuous conversion mode

Single step mode

Fixed channel, single conversion mode the PGA channel selection is dependent onthe ADC channel selectionAuto Scan, single/continuous conversion mode

Vsen Asen Vref bg( ) Aref bg( )⁄×=



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(2)

P89LPC9331/9341 Temperature Sensor usage steps:

1. Config TSEL1 and TSEL0 as ‘01’ to choose internal reference voltage.2. Using ADC to get converting result as Aref.3. Config TSEL1 and TSEL0 as ‘10’ to choose temperature sensor.4. Using ADC to get converting result as Asen.5. Calculate Vsen with formula (1).6. Calculate Temperature with formula (2).

P89LPC9351 Temperature Sensor usage steps:

1. Setting PGASEL01 and PGASEL00 bits to choose AD03 channel.2. Config TSEL1 and TSEL0 as ‘01’ to choose internal reference voltage.3. Using ADC to get converting result as Aref.4. Config TSEL1 and TSEL0 as ‘10’ to choose temperature sensor.5. Using ADC to get converting result as Asen.6. Calculate Vsen with formula (1).7. Calculate Temperature with formula (2).

3.2.3 ADC operating modes

3.2.3.1 Fixed channel, single conversion modeA single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel (see Table 15). An interrupt, if enabled, will be generated after the conversion completes. The input channel is selected in the ADINS register. This mode is selected by setting the SCANx bit in the ADMODA register.

3.2.3.2 Fixed channel, continuous conversion modeA single input channel can be selected for continuous conversion. The results of the conversions will be sequentially placed in the four result registers (see Table 16). An interrupt, if enabled, will be generated after every four conversions. Additional conversion

Vsen m temp b (where m = 11.3 mV/°C, b = 890 mV)+×=

Table 15. Input channels and result registers for fixed channel single, auto scan single and auto scan continuous conversion mode

Result register Input channelAD0DAT0 Anin00

AD0DAT1 Anin01

AD0DAT2 Anin02

AD0DAT3 Anin03

AD1DAT0 Anin10

AD1DAT1 Anin11

AD1DAT2 Anin12

AD1DAT3 Anin13



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results will again cycle through the four result registers, overwriting the previous results. Continuous conversions continue until terminated by the user. This mode is selected by setting the SCCx bit in the ADMODA register.

3.2.3.3 Auto scan, single conversion modeAny combination of the four input channels can be selected for conversion by setting a channel’s respective bit in the ADINS register. The channels are converted from LSB to MSB order (in ADINS). A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel (See Table 15). An interrupt, if enabled, will be generated after all selected channels have been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode.This mode is selected by setting the SCANx bit in the ADMODA register.

3.2.3.4 Auto scan, continuous conversion modeAny combination of the four input channels can be selected for conversion by setting a channel’s respective bit in the ADINS register. The channels are converted from LSB to MSB order (in ADINS). A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel (See Table 15). An interrupt, if enabled, will be generated after all selected channels have been converted. The process will repeat starting with the first selected channel. Additional conversion results will again cycle through the result registers of the selected channels, overwriting the previous results.Continuous conversions continue until terminated by the user.This mode is selected by setting the BURSTx bit in the ADMODA register.

3.2.3.5 Dual channel, continuous conversion modeThe any combination of two of the four input channels can be selected for conversion. The result of the conversion of the first channel is placed in the first result register. The result of the conversion of the second channel is placed in the second result register.The first channel is again converted and its result stored in the third result register. The second channel is again converted and its result placed in the fourth result register (See Table 17). An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel).This mode is selected by setting the SCCx bit in the ADMODA register.

Table 16. Result registers and conversion results for fixed channel, continuous conversion mode

Result register ContainsADxDAT0 Selected channel, first conversion result

ADxDAT1 Selected channel, second conversion result

ADxDAT2 Selected channel, third conversion result

ADxDAT3 Selected channel, fourth conversion result

Table 17. Result registers and conversion results for dual channel, continuous conversion mode

Result register ContainsADxDAT0 First channel, first conversion result

ADxDAT1 Second channel, first conversion result

ADxDAT2 First channel, second conversion result

ADxDAT3 Second channel, second conversion result



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NXP Semiconductors

Documents

D DR DRAFT RAFT AFT UM D DRAFT P89LPC9331/9341… · 2009. 2. 24. · P89LPC9331/9341/9351 User manual 1. Introduction The P89LPC9331/9341/9351 are single-chip microcontrollers