D Flip Flop

• Also called:

• Delay FF

• Data FF

• D-type Latches

• ‘Delayed 1

• Clock Pulse’

D Flip Flop (Specification)

A signal input and a clock signal is used

AMI-0.6micron process is used

Wp=7.5 u, Wn= 3.0 u, Ln=Lp=0.6u

Pre and Post-layout simulations using spectra

Rise time, Fall time and propagation delay increase for the

loading effects.

Why DFF

• Preferred type for integrated circuit applications

(DFF)

• S-R flip flop has indeterminate state when both inputs

are high

• The JKFF simplifies the RSFF truth table but keeps

two inputs.

Symbol

Truth Table Similar Wiring

Wiring Diagram

7474 D Flip Flop

• Logic Symbol

Note: The asynchronous inputs (PS & CLR) Override the synchronous inputs (D & CLK) .

Truth Table

D (Delay) Flip Flop Uses

Sequential logic devices used in temporary memory devices.

Wired together to form shift registers and storage registers.

Delays data from reaching output Q one clock pulse.

CMOS examples: 74HC74, 74FCT374, 40174

Over 50 different ICs in FACT CMOS family.

D Clocked Latch

It similar to a D flip flopbut it reacts to the clockdifferently

Comparing Flip Flop and Latch

D Flip Flop vs. D Clocked Latch

• D flip flop– Triggered on positive edge of clock

– Output Q (and state) changes only at a time instant

• D clocked latch– Output Q changes (with D) while clock is H

– Output Q changes during a window of time

– Trickier to use since lots of changes can happen during a time duration

• Flip flops are preferred to latches in designing circuits

• Latches are used in memory circuits, e.g., RAM

The End

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