ACNV4506Intelligent Power Module and Gate Drive Interface Optocouplers

Data Sheet

CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

DescriptionThe ACNV4506 device contains a GaAsP LED optically coupled to an integrated high gain photo detector. Minimized propagation delay difference between devices makes these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. Specifications and performance plots are given for typical IPM applications.

Functional Diagram

Features• Performance Specified for Common IPM Applications

Over Industrial Temperature Range.

• Short Maximum Propagation Delays

• Minimized Pulse Width Distortion (PWD)

• Very High Common Mode Rejection (CMR)

• High CTR.

• Available in Widebody DIP10 and GulWing packages with 13.0 mm creepage and clearance.

• Safety Approval (pending):– UL Recognized with 7500 Vrms for 1 minute per

UL1577.– CSA Approved.– IEC/EN/DIN EN 60747-5-2 Approved with VIORM =

2262Vpeak.

Specifications• Wide operating temperature range: –40°C to 105°C.

• Typical propagation delay tPHL = 200 ns, tPLH = 350 ns

• Typical Pulse Width Distortion (PWD) = 150 ns.

• 30 kV/µs minimum common mode rejection (CMR) at VCM = 1500 V.

• CTR = 90%(typ) at IF = 10mA

Applications• IPM Isolation

• Isolated IGBT/MOSFET Gate Drive

• AC and Brushless DC Motor Drives

• Industrial Inverters

Note: A 0.1 µF bypass capacitor must be connected between pins 7 and 10.

Truth Table LED VO

ON LOW

OFF HIGH

ANODE

N.C.

CATHODE

VL

VO

Ground

92

83

74SHIELD

5

1

6

1020kΩ

VCC

N.C.

N.C.

N.C.

2

Ordering InformationACNV4506 is pending UL recognition with 7500Vrms for 1 minute per UL1577.

Part number

Option

PackageSurface Mount

GullWing

Tape&Reel

UL 7500Vrms/ 1 Minute rating

IEC/EN/DIN EN 60747-5-2 Quantity

RoHSCompliant

ACNV4506

-000E 500 mil X X 35 per tube

-300E DIP-10

X X X X 35 per tube

-500E X X X X X 500 per reel

To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry.

Example 1:

ACNV4506-500E to order product of 500mil DIP-10 Widebody with Gull Wing Surface Mount package in Tape and Reel packaging with both UL 7500Vrms/1min and IEC/EN/DIN EN60747-5-2 Safety Approval in RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

3

Package Outline DrawingsACNV4506 Widebody 500Mils DIP10 Package, 13.0 mm clearance

ACNV4506 Widebody 500Mils GulWing Tape & Reel Package, 13.0 mm clearance

Dimensions in Inches [Millimeters]

[13.69 ± 0.15]0.539 ± 0.006

[11.01 ± 0.15]0.433 ± 0.006

[13.01 ± 0.15]0.512 ± 0.006

[11.01 ± 0.15]0.433 ± 0.006

[1.9

98]

0.08

[5.2

5]0.

21[13.06]0.514

+0.08-0.05+0.003-0.002

[0.25 ]0.0105° TYP

[1.30]0.05TYP

[5.25]0.207

[1.78 ± 0.15]0.070 ± 0.006 [2.54]

0.10TYP

[0.51]0.020 MIN

[0.48 ± 0.08]0.019 ± 0.003

[3.1

0] 0

.122

[3.9

0] 0

.154

Dimension in Inches [Millimeter]

LAND PATTERN RECOMMENDATION

[13.71 ± 0.15]0.540 ± 0.006

[11.01 ± 0.15]0.433 ± 0.006

[16.35 ± 0.15]0.644 ± 0.006

[1.78 ± 0.15]0.070 ± 0.006

[0.75 ± 0.15]0.030 ± 0.006

[1.00 ± 0.15]0.039 ± 0.006

[14.90 ± 0.15]0.587 ± 0.006

[13.01 ± 0.15]0.512 ± 0.006

[2.29 ± 0.15]0.090 ± 0.006

[1.30 ± 0.15]0.051 ± 0.006

[2.2

9 ± 0.

15]

0.09

0 ± 0.

006

[1.30]0.051

TYP

MAX[5.25]0.207

5° NOM

+0.076-0.051+0.003-0.002

[0.254 ]0.010

4

Table 1. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics* (ACNV4506)

Description Symbol Characteristic UnitClimatic Classification (IEC 68 Part I) 55/105/21

Maximum Working Insulation Voltage VIORM 2262 Vpeak

Input to Output Test Voltage, Method b*VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC

VPR 4242 Vpeak

Input to Output Test Voltage, Method a*VIORM x 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC

VPR 3619 Vpeak

Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec) VIOTM 12000 Vpeak

Safety-limiting values – maximum values allowed in the event of a failure (also see Figure 13).

Case TemperatureInput CurrentOutput Power

TSIS, INPUTPS, OUTPUT

1154001

°CmAW

Insulation Resistance at TS, VIO = 500 V RS >109 Ω* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section,

(IEC/EN/DIN EN 60747-5-2) for a detailed description of Method a and Method b partial discharge test profiles.

Regulatory InformationThe ACNV4506 is pending approval from the following organizations:

IECIEC/EN/DIN EN 60747-5-2:2009

ULApproval under UL 1577, component recognition program up to VISO = 7500 VRMS. File E55361.

CSAApproval under CSA Component Acceptance Notice #5, File CA 88324.

Solder Reflow ProfileRecommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.

5

Table 2. Insulation and Safety Related Specifications

Parameter Symbol ACNV4506 Units ConditionsMinimum External Air Gap (External Clearance)

L(101) 13.0 mm Measured from input terminals to output terminals, shortest distance through air.

Minimum ExternalTracking (External Creepage)

L(102) 13.0 mm Measured from input terminals to output terminals, shortest distance path along body.

Minimum Internal Plastic Gap(Internal Clearance)

2 mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector.

Minimum Internal Tracking (Internal Creepage)

NA mm Measured from input terminals to output terminals, along internal cavity.

Tracking Resistance(Comparative Tracking Index)

CTI >175 V DIN IEC 112/VDE 0303 Part 1

Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)

Table 3. Absolute Maximum Ratings

Parameter Symbol Min. Max. Units NoteStorage Temperature Tstorage -55 125 °C

Operating Temperature TA -40 105 °C

Average Input Current IF(avg) 25 mA 1

Peak Input Current(50% duty cycle, <1 ms pulse width)

IF(peak) 50 mA 2

Peak Transient Input Current(<1 µs pulse width, 300 pps)

IF(tran) 1.0 A

Reverse Input Voltage (Pin 3-2) VR 5 V

Average Output Current (Pin 8) IO(avg) 15 mA

Output Voltage (Pin 8-7) VO -0.5 30

Supply Voltage (Pin 10-7) VCC -0.5 30

Output Power Dissipation PO 100 mW 3

Total Power Dissipation PT 145 mW 4

Infrared and Vapor Phase Reflow Temperature See Reflow Thermal Profile.

Table 4. Recommended Operating Conditions

Parameter Symbol Min. Max. Units NotePower Supply Voltage VCC 4.5 30 V

Output Voltage VO 0 30 V

Input Current (ON) IF(on) 10 20 mA

Input Voltage (OFF) VF(off) -5 0.8 V

Operating Temperature TA -40 105 °C

6

Table 5. Electrical SpecificationsOver recommended operating conditions unless otherwise specified: TA = -40°C to +105°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V

Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. NoteCurrent Transfer Ratio CTR 44 90 % IF = 10 mA, VO = 0.6 V 5

Low Level Output Current IOL 4.4 9.0 mA IF = 10 mA, VO = 0.6 V 1, 2

Low Level Output Voltage VOL 0.3 0.6 V IO = 2.4 mA

Input Threshold Current ITH 1.0 5.0 mA VO = 0.8 V, IO = 0.75 mA 1 9

High Level Output Current IOH 5 50 µA VF = 0.8 V 3

High Level Supply Current ICCH 0.6 1.3 mA VF = 0.8 V, VO = Open 9

Low Level Supply Current ICCL 0.6 1.3 mA IF = 10 mA, VO = Open 9

Input Forward Voltage VF 1.5 1.85 V IF = 10 mA 4

Temperature Coefficient of Forward Voltage

ΔVF/ΔTA -1.6 mV/°C IF = 10 mA

Input Reverse Breakdown Voltage

BVR 5 V IR = 10 µA

Input Capacitance CIN 60 pF f = 1 MHz, VF = 0 V

* All typical values at 25°C, VCC = 15 V.

Table 6. Switching Specifications (RL = 20 kΩ)Over recommended operating conditions unless otherwise specified. TA = -40°C to +105°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V

Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. NotePropagation Delay Time to Low Output Level

tPHL 95 200 400 ns CL = 100 pF IF(on) = 10 mA,VF(off) = 0.8 V,VCC = 15.0 V,VTHLH = 2.0 V,VTHHL = 1.5 V

5, 7, 9-11

8, 9110 ns CL = 10 pF

Propagation Delay Time to High Output Level

tPLH 250 350 550 ns CL = 100 pF

200 ns CL = 10 pF

Pulse Width Distortion PWD 150 450 ns CL = 100 pF 13

Propagation Delay Difference Between Any 2 Parts

tPLH-tPHL -150 150 450 ns 10

Output High Level Common Mode Transient immunity

|CMH| 30 35 kV/µs IF = 0 mA, VO > 3.0 V

VCC = 15.0 V,CL = 100 pF,VCM = 1500 VP-P,TA = 25°C

6 11

Output Low Level Common Mode Transient immunity

|CML| 30 35 kV/µs IF = 10 mA, VO < 1.0 V

12

* All typical values at 25°C, VCC = 15 V.

7

Table 7. Switching Specifications (RL = Internal Pull-up)Over recommended operating conditions unless otherwise specified. TA = -40°C to +105°C, VCC = +4.5 V to 30 V, IF(on) = 10 mA to 20 mA, VF(off) = -5 V to 0.8 V

Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. NotePropagation Delay Time to Low Output Level

tPHL 95 200 400 ns IF(on) = 10 mA,VF(off) = 0.8 V,VCC = 15.0 V,VTHLH = 2.0 V,VTHHL = 1.5 V

8 8, 9

Propagation Delay Time to High Output Level

tPLH 200 365 550 ns

Pulse Width Distortion PWD 165 500 ns 13

Propagation Delay Difference Between Any 2 Parts

tPLH-tPHL -150 165 500 ns 10

Output High Level Common Mode Transient immunity

|CMH| 30 35 kV/µs IF = 0 mA, VO > 3.0 V

VCC = 15.0 V,CL = 100 pF,VCM = 1500 VP-P,TA = 25°C

6 11

Output Low Level Common Mode Transient immunity

|CML| 30 35 kV/µs IF = 10 mA, VO < 1.0 V

12

* All typical values at 25°C, VCC = 15 V.

Table 8. Package Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. NoteInput-Output Momentary Withstand Voltage

VISO 7500 Vrms RH < 50%, t = 1 min, TA = 25°C 6, 7

Input-Output Resistance RI-O 1012 Ω VI-O = 500 Vdc 6

Input-Output Capacitance CI-O 0.6 pF Freq=1 MHz 6

Notes:1. Derate linearly above 90°C free-air temperature at a rate of 0.8 mA/°C.2. Derate linearly above 90°C free-air temperature at a rate of 1.6 mA/°C.3. Derate linearly above 90°C free-air temperature at a rate of 3.0 mW/°C.4. Derate linearly above 90°C free-air temperature at a rate of 4.2 mW/°C.5. CURRENT TRANSFER RATIO in percent is defined as the ratio of output collector current (IO) to the forward LED input current (IF) times 100.6. Device considered a two-terminal device: Pins 1-5 shorted together and Pins 6-10 shorted together.7. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥ 7500 VRMS for 1 minute (leakage detection

current limit, II-O ≤ 5 µA).8. Pulse: f = 20 kHz, Duty Cycle = 10%.9. Use of a 0.1 µF bypass capacitor connected between pins 7 and 10 can improve performance by filtering power supply line noise.10. The difference between tPLH and tPHL between any two parts under the same test condition. (See IPM Dead Time and Propagation Delay

Specifications section.)11. Common mode transient immunity in a Logic High level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the

output will remain in a Logic High state (i.e., VO > 3.0 V).12. Common mode transient immunity in a Logic Low level is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the

output will remain in a Logic Low state (i.e., VO < 1.0 V).13. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given device.

8

If

VO

VTHHL

tPHL tPLH

tf tr

90%

10%

90%

10%VTHLH

TA – TEMPERATURE – °C

TA = 25°C

0.1µF

+-

+-

VCC = 15

CL*

VOUTΠ

* TOTAL LOADCAPACITANCE

92

83

74SHIELD

5

1

6

10

20kΩIF(ON) = 10 mA

92

83

74

5

1

6

10

IF

VF+

–

0

0.5

1

1.5

2

2.5

3

3.5

4

-40 -20 0 20 40 60 80 100

I OH -

HIG

H LE

VEL O

UTPU

T CUR

RENT

- µA

30 V

4.5 V

0.001

0.01

0.1

1

10

100

1 1.2 1.4 1.6 1.8 2VF - INPUT FORWARD VOLTAGE - V

I F - I

NPUT

FORW

ARD

CURR

ENT-

mAVF = 0.8 V

VCC = VO = 4.5 V OR 30 V

VCM

∆tOV

VO

VO

SWITCH AT A: IF = 0 mA

SWITCH AT B: IF = 10 mA

VCC

VOL

VCM∆t

δVδt

=

VFF

+

-

B

0.1µF IF

+-

V

100 pF *

VOUT

* 100 pF TOTALCAPACITANCE

A

VCM = 1500VΠ

+ -

92

83

74SHIELD

5

1

6

10

20kΩ

VCC = 15

92

83

74

5

1

6

10

Figure 5. Propagation Delay Test Circuit

Figure 3. High Level Output Current vs. Temperature Figure 4. Input Current vs. Forward Voltage

Figure 1. Typical Transfer Characteristics Figure 2. Normalized Output Current vs. Temperature

TA – TEMPERATURE – °C

0

2

4

6

8

10

0 5 10 15 20IF - FORWARD LED CURRENT - mA

I O - O

UTPU

T CUR

RENT

- mA

25°C

-40°C

105°C

VO = 0.6 V

0.9

0.92

0.94

0.96

0.98

1

1.02

-40 -20 0 20 40 60 80 100

NORM

ALIZ

ED O

UTPU

T CUR

RENT

IF = 10 mAVO = 0.6 V

9

100

200

300

400

500

-40 -20 0 20 40 60 80 100

t P - P

ROPA

GATI

ON D

ELAY

- ns

100

200

300

400

500

-40 -20 0 20 40 60 80 100TA - TEMPERATURE - °C TA - TEMPERATURE - °C

t P - P

ROPA

GATI

ON D

ELAY

- ns

tPLH

tPHL

0

200

400

600

800

1000

0 10 20 30 40 50RL – LOAD RESISTANCE – kΩ

t P - P

ROPA

GATI

ON D

ELAY

- ns

tPHL

tPLH

0

200

400

600

800

1000

1200

1400

0 100 200 300 400 500CL - LOAD CAPACITANCE - pF

t P - P

ROPA

GATI

ON D

ELAY

- ns

tPLH

tPHL

IF = 10 mAVCC = 15 VCL = 100 pFRL = 20 kΩ (EXTERNAL)

IF = 10 mAVCC = 15 VCL = 100 pFRL = 20 kΩ (INTERNAL)

IF = 10 mAVCC = 15 VCL = 100 pFTA = 25°C

IF = 10 mAVCC = 15 VRL = 20 kΩTA = 25°C

tPLH

tPHL

Figure 9. Propagation Delay vs. Load Resistance Figure 10. Propagation Delay vs. Load Capacitance

Figure 7. Propagation Delay with External 20 kΩ RL vs. Temperature Figure 8. Propagation Delay with Internal 20 kΩ RL vs. Temperature

Figure 6. CMR Test Circuit and Waveforms

If

VO

VTHHL

tPHL tPLH

tf tr

90%

10%

90%

10%VTHLH

TA – TEMPERATURE – °C

TA = 25°C

0.1µF

+-

+-

VCC = 15

CL*

VOUTΠ

* TOTAL LOADCAPACITANCE

92

83

74SHIELD

5

1

6

10

20kΩIF(ON) = 10 mA

92

83

74

5

1

6

10

IF

VF+

–

0

0.5

1

1.5

2

2.5

3

3.5

4

-40 -20 0 20 40 60 80 100

I OH -

HIG

H LE

VEL O

UTPU

T CUR

RENT

- µA

30 V

4.5 V

0.001

0.01

0.1

1

10

100

1 1.2 1.4 1.6 1.8 2VF - INPUT FORWARD VOLTAGE - V

I F - I

NPUT

FORW

ARD

CURR

ENT-

mAVF = 0.8 V

VCC = VO = 4.5 V OR 30 V

VCM

∆tOV

VO

VO

SWITCH AT A: IF = 0 mA

SWITCH AT B: IF = 10 mA

VCC

VOL

VCM∆t

δVδt

=

VFF

+

-

B

0.1µF IF

+-

V

100 pF *

VOUT

* 100 pF TOTALCAPACITANCE

A

VCM = 1500VΠ

+ -

92

83

74SHIELD

5

1

6

10

20kΩ

VCC = 15

92

83

74

5

1

6

10

10

0

500

1000

1500

2000

2500

0 5 10 15 20 25 30VCC - SUPPLY VOLTAGE - V

t P -

PROP

AGAT

ION

DELA

Y - n

s

tPLH

tPHL

100

200

300

400

500

0 5 10 15 20IF - FORWARD LED CURRENT - mA

t P -

PROP

AGAT

ION

DELA

Y - n

s

tPLH

tPHL

IF = 10 mACL = 100 pFRL = 20 kΩTA = 25°C

VCC = 15 VCL = 100 pFRL = 20 kΩTA = 25°C

0100200300400500600700800900

10001100

0 10 20 30 40 50 60 70 80 90 100 110 120

IS (mA)

OUTP

UT P

OWER

- P S

, INP

UT CU

RREN

T - I S

TS - CASE TEMPERATURE - °C

PS (mW)

Figure 11. Propagation Delay vs. Supply Voltage Figure 12. Propagation Delay vs. Input Current

Figure 13. Dependence of Safety Limiting Values on Temperatures (Thermal Derating Curves)

11

Applications Information

LED Drive Circuit Considerations For Ultra High CMR PerformanceWithout a detector shield, the dominant cause of op-tocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 15. The ACNV4506 improve CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. However, this shield does not eliminate the ca-pacitive coupling between the LED and the optocoupler output pin and output ground as shown in Figure 16. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocou-pler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off) during common mode transients. For example, the recommended application circuit (Figure 14), can achieve 30 kV/µs CMR while minimizing component com-plexity. Note that a CMOS gate is recommended in Figure 14 to keep the LED off when the gate is in the high state.

Another cause of CMR failure for a shielded optocoupler is direct coupling to the optocoupler output pins through CLEDO1 in Figure 16. Many factors influence the effect and magnitude of the direct coupling including: the position of the LED current setting resistor and the value of the capacitor at the optocoupler output (CL).

CMR With The LED On (CMRL)A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriv-ing the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. The recommended minimum LED current of 10 mA provides adequate margin over the maximum ITH of 5.0 mA (see Figure 1) to achieve 30 kV/µs CMR.

The placement of the LED current setting resistor effects the ability of the drive circuit to keep the LED on during transients and interacts with the direct coupling to the optocoupler output. For example, the LED resistor in Figure 17 is connected to the anode. Figure 18 shows the AC equivalent circuit for Figure 17 during common mode transients. During a +dVCM/dt in Figure 18, the current available at the LED anode (Itotal) is limited by the series resistor. The LED current (IF) is reduced from its DC value by an amount equal to the current that flows through CLEDP and CLEDO1. The situation is made worse because the current through CLEDO1 has the effect of trying to pull the output high (toward a CMR failure) at the same time the LED current is being reduced. For this reason, the rec-ommended LED drive circuit (Figure 14) places the current setting resistor in series with the LED cathode. Figure 19

Figure 14. Recommended LED Drive Circuit

Figure 15. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers

*100 pF TOTALCAPACITANCE

310Ω

+5 V

CMOS

0.1µF

+- VCC = 15V

CL*

VOUT

92

83

74SHIELD

5

1

6

10

20kΩ92

83

74

5

1

6

10

CLEDP

CLEDN

92

83

74

5

1

6

10

20kΩ

CLEDP

CLEDN

CLED0192

83

74SHIELD

5

1

6

10

20kΩ

Figure 16. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers

Figure 17. LED Drive Circuit with Resistor Connected to LED Anode (Not Recommended)

*100 pF TOTALCAPACITANCE

310Ω +5 V

CMOS

0.1µF

+- VCC = 15V

CL*

VOUT

92

83

74SHIELD

5

1

6

10

20kΩ92

83

74

5

1

6

10

12

Figure 18. AC Equivalent Circuit for Figure 17 during Common Mode Transients

Figure 19. AC Equivalent Circuit for Figure 14 during Common Mode Transients

VCM

ITOTAL*

100 pF

VOUT

+ -

* THE ARROWS INDICATE THE DIRECTIONOF CURRENT FLOW DURING +dVCM/dt

300Ω IF

ICLEDPCLEDP

CLEDN

CLED0192

83

74SHIELD

5

1

6

10

20kΩ92

83

74

5

1

6

10

ICLEDN

*

VCM

20kΩVOUT

+ -

* THE ARROWS INDICATE THE DIRECTION OF CURRENTFLOW FOR +dVCM/dt TRANSIENTS.** OPTIONAL CLAMPING DIODE FOR IMPROVED CMHPERFORMANCE. VR < VF (OFF) DURING +dVCM/dt.

300Ω

+ -

CLEDP

CLEDN

CLED0192

83

74SHIELD

5

1

6

10

20kΩ

*

2

3

4

5

1

100 pFVR**

is the AC equivalent circuit for Figure 14 during common mode transients. In this case, the LED current is not reduced during a +dVCM/dt transient because the current flowing through the package capacitance is supplied by the power supply. During a -dVCM/dt transient, however, the LED current is reduced by the amount of current flowing through CLEDN. But, better CMR performance is achieved since the current flowing in CLEDO1 during a negative transient acts to keep the output low.

CMR With The LED Off (CMRH)A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. For example, during a +dVCM/dt transient in Figure 19, the current flowing through CLEDN is supplied by the parallel combi-nation of the LED and series resistor. As long as the voltage developed across the resistor is less than VF(OFF) the LED will remain off and no common mode failure will occur. Even if the LED momentarily turns on, the 100 pF capacitor from pins 8-7 will keep the output from dipping below the threshold. The recommended LED drive circuit (Figure 14) provides about 10 V of margin between the lowest opto-coupler output voltage and a 3 V IPM threshold during a 30 kV/µs transient with VCM = 1500 V. Additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line connection in Figure 19, to clamp the voltage across the LED below VF(OFF).

Since the open collector drive circuit, shown in Figure 20, cannot keep the LED off during a +dVCM/dt transient, it is not desirable for applications requiring ultra high CMRH performance. Figure 21 is the AC equivalent circuit for Figure 20 during common mode transients. Essentially all the current flowing through CLEDN during a +dVCM/dt transient must be supplied by the LED. CMRH failures can occur at dv/dt rates where the current through the LED and CLEDN exceeds the input threshold. Figure 22 is an alternative drive circuit which does achieve ultra high CMR performance by shunting the LED in the off state.

Figure 20. Not Recommended Open Collector LED Drive Circuit

Figure 21. AC Equivalent Circuit for Figure 20 during Common Mode Transients

Figure 22. Recommended LED Drive Circuit for Ultra High CMR

+5 V

Q1

92

83

74SHIELD

5

1

6

10

20kΩ

100 pFI

VCM

+ -

Q1

CLEDN

92

83

74SHIELD

5

1

6

10

I

20kΩVOUT

20kΩ

CLED01

CLEDP

CLEDN*

300Ω

* THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW FOR +dVCM/dt TRANSIENTS.

+5 V

92

83

74SHIELD

5

1

6

10

20kΩ

13

IPM Dead Time and Propagation Delay SpecificationsThe ACNV4506 includes a Propagation Delay Difference specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 23) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails.

To minimize dead time the designer must consider the propagation delay characteristics of the optocoupler as well as the characteristics of the IPM IGBT gate drive circuit. Considering only the delay characteristics of the optocoupler (the characteristics of the IPM IGBT gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn on (tPHL) and turn-off (tPLH) propagation delay specifications, preferably over the desired operating temperature range.

The limiting case of zero dead time occurs when the input to Q1 turns off at the same time that the input to Q2 turns on. This case determines the minimum delay between LED1 turn-off and LED2 turn-on, which is related to the worst case optocoupler propagation delay waveforms, as shown in Figure 24. A minimum dead time of zero is achieved in Figure 24 when the signal to turn on LED2 is delayed by (tPLH max - tPHL min) from the LED1 turn off.

Note that the propagation delays used to calculate PDD are taken at equal temperatures since the optocouplers under consideration are typically mounted in close proximity to each other. (Specifically, previous equation are not the same as the tPLH max and tPHL min, over the full operating temperature range, specified in the data sheet.) This delay is the maximum value for the propaga-tion delay difference specification which is specified at 450 ns for the ACNV4506 over an operating temperature range of -40°C to 105°C.

Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time occurs in the highly unlikely case where one optocoupler with the fastest tPLH and another with the slowest tPHL are in the same inverter leg. The maximum dead time in this case becomes the sum of the spread in the tPLH and tPHL propa-gation delays as shown in Figure 25. The maximum dead time is also equivalent to the difference between the maximum and minimum propagation delay difference specifications. The maximum dead time (due to the opto-couplers) for the ACNV4506 are 600 ns (= 450 ns - (-150 ns)) over an operating temperature range of -40°C to 105°C.

Figure 23. Typical Application Circuit

310Ω

+5 VQ1

Q2

CMOS

ILED1

310Ω

+5 V

CMOS

ILED2

-HV

ACNV4506

ACNV4506ACNV4506ACNV4506ACNV4506

M

IPM

+HV0.1µF

0.1µF

VCC1

VOUT1

VCC2

VOUT2

92

83

74SHIELD

5

1

6

10

20kΩ

92

83

74SHIELD

5

1

6

10

20kΩ

MM

92

83

74

5

1

6

10

92

83

74

5

1

6

10

92

83

74

5

1

6

10

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. AV02-2483EN - August 31, 2011

VOUT1VOUT2

ILED2

tPLH MAX.

PDD* MAX. =(tPLH-tPHL) MAX. = tPLH MAX. - tPHL MIN.

tPHL MIN.

ILED1

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

*PDD = PROPAGATION DELAY DIFFERENCE

Note: The propagation delays used to calculatePDD are taken at equal temperatures.

VOUT1VOUT2

ILED2

tPLH MIN.

MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER)= (tPLH MAX. - tPLH MIN.) + (tPHL MAX. - tPHL MIN.)= (tPLH MAX. - tPHL MIN.) - (tPLH MIN. - tPHL MAX.)= PDD* MAX. - PDD* MIN.

tPHL MIN.

ILED1

Q1 ON

Q2 OFF

Q1 OFF

Q2 ON

*PDD = PROPAGATION DELAY DIFFERENCE

tPLH MAX.

tPHL MAX.

PDD*MAX.

MAX.DEAD TIME

Note: The propagation delays used to calculate the maximumDead time are taken at equal temperatures.

Figure 24. Minimum LED Skew for Zero Dead Time

Figure 25. Waveforms for Deadtime Calculation