DATA SHEET - WordPress.com · •Telecom equipment •Portable instruments •Point-of-sale terminals. 3 GENERAL DESCRIPTION The PCF2103 family is a low power CMOS LCD controller

DATA SHEET

Product specificationFile under Integrated Circuits, IC12

1998 May 11

INTEGRATED CIRCUITS

PCF2103 familyLCD controllers/drivers

1998 May 11 2

Philips Semiconductors Product specification

LCD controllers/drivers PCF2103 family

CONTENTS

1 FEATURES

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 ORDERING INFORMATION

5 BLOCK DIAGRAM

6 PINNING

7 FUNCTIONAL DESCRIPTION

7.1 LCD bias voltage generator7.2 Oscillator7.3 External clock7.4 Power-on reset7.5 Power-down mode7.6 Registers7.7 Busy flag7.8 Address Counter (AC)7.9 Display Data RAM (DDRAM)7.10 Character Generator ROM (CGROM)7.11 Character Generator RAM (CGRAM)7.12 Cursor control circuit7.13 Timing generator7.14 LCD row and column drivers7.15 Reset function

8 INSTRUCTIONS

8.1 Clear display8.2 Return home8.3 Entry mode set8.3.1 I/D8.3.2 S8.4 Display control (and partial power-down mode)8.4.1 D8.4.2 C8.4.3 B8.5 Cursor or display shift8.6 Function set8.6.1 DL (parallel mode only)8.6.2 M8.6.3 H

8.7 Set CGRAM address8.8 Set DDRAM address8.9 Read busy flag and address counter8.10 Write data to CGRAM or DDRAM8.11 Read data from CGRAM or DDRAM8.12 Extended function set instructions and features8.12.1 New instructions8.12.2 Icon control8.12.3 IM8.12.4 IB8.12.5 Screen configuration8.12.6 Display configuration8.12.7 Reducing current consumption

9 INTERFACE TO MICROCONTROLLER

9.1 Parallel interface9.2 I2C-bus interface9.2.1 Characteristics of the I2C-bus9.2.2 I2C-bus protocol9.2.3 Definitions

10 LIMITING VALUES

11 HANDLING

12 DC CHARACTERISTICS

13 AC CHARACTERISTICS

14 TIMING CHARACTERISTICS

15 APPLICATION INFORMATION

15.1 8-bit operation, 1-line display using internalreset


15.3 8-bit operation, 2-line display15.4 I2C-bus operation, 1-line display

16 BONDING PAD LOCATIONS

17 DEFINITIONS

18 LIFE SUPPORT APPLICATIONS

19 PURCHASE OF PHILIPS I2C COMPONENTS

1998 May 11 3



2 APPLICATIONS

• Telecom equipment

• Portable instruments

• Point-of-sale terminals.

3 GENERAL DESCRIPTION

The PCF2103 family is a low power CMOS LCD controllerand driver, designed to drive a dot matrix LCD display of2 line by 12 or 1 line by 24 characters with 5 × 8 dotformat. All necessary functions for the display are providedin a single chip, including on-chip generation of LCD biasvoltages, resulting in a minimum of external componentsand lower system current consumption. The PCF2103interfaces to most microcontrollers via a 4 or 8-bit bus orvia the 2-wire I2C-bus. The chip contains a charactergenerator and displays alphanumeric and kana(Japanese) characters. The letter ‘X’ in PCF2103Xcharacterizes the built-in character set. Various charactersets can be manufactured on request.

4 ORDERING INFORMATION

TYPE NUMBERPACKAGE

NAME DESCRIPTION VERSION

PCF2103EU/2/F2 − chip with bumps in tray −

1 FEATURES

• Single-chip LCD controller/driver

• 2-line display of up to 12 characters + 120 icons,or 1-line display of up to 24 characters + 120 icons

• 5 × 7 character format plus cursor; 5 × 8 for kana(Japanese syllabary) and user defined symbols

• Icon mode: reduced current consumption whiledisplaying icons only(1)

• Icon blink function

• On-chip:

– Generation of intermediate LCD bias voltages

– Oscillator requires no external components(external clock also possible)

• Display data RAM: 80 characters

• Character generator ROM: 240, 5 × 8 characters

• Character generator RAM: 16, 5 × 8 characters;3 characters used to drive 120 icons, 6 characters usedif icon blink feature is used in application

• 4 or 8-bit parallel bus and 2-wire I2C-bus interface

• CMOS compatible

• 18 row, 60 column outputs

• Mux rates 1 : 18 (for normal operation) and 1 : 2(for icon-only mode)

• Uses common 11 code instruction set (extended)

• Logic supply voltage range, VDD − VSS = 1.8 to 5.5 V;chip may be driven with two battery cells

• Display supply voltage range, VLCD − VSS = 2.2 to 6.5 V

• Very low current consumption (20 to 120 µA):

– Icon mode: <25 µA

– Power-down mode: <2.5 µA.

(1) Icon mode is used to save current. When only iconsare displayed, a much lower operating voltage VLCD

can be used and the switching frequency of the LCDoutputs is reduced. In most applications it is possibleto use VDD as VLCD.

1998 May 11 4



5 BLOCK DIAGRAM

Fig.1 Block diagram.

handbook, full pagewidth

MGL259

CURSOR AND DATA CONTROL

SHIFT REGISTER 5 × 12-BIT

DATA LATCHES

COLUMN DRIVERS

60

5

60

CHARACTERGENERATORRAM (128 × 5)

(CGRAM)16 CHARACTERS

CHARACTERGENERATOR

ROM(CGROM)

240 CHARACTERS

DISPLAY DATA RAM(DDRAM)

80 CHARACTERS/BYTES

ADDRESS COUNTER(AC)

INSTRUCTIONDECODER

INSTRUCTIONREGISTER

ROW DRIVERS

SHIFT REGISTER 18-BIT

BIASVOLTAGE

GENERATOR

BUSYFLAG

DATAREGISTER

(DR)

I/O BUFFER

OSCILLATOR

TIMINGGENERATOR

DISPLAYADDRESSCOUNTER

POWER-ONRESET

VDD

VSS

T1

VLCD

C1 to C60 R1 to R18

OSC

PD

PCF2103

DB0 to DB3/SA0 DB4 to DB7 E R/W RS SCL SDA

18

18

60

5

7 7

8

8

77

8

88

1998 May 11 5



6 PINNING

Note

1. This is the voltage used for the generation of LCD bias levels.

SYMBOL DIE PAD DESCRIPTION

VDD 1 supply voltage

OSC 2 oscillator/external clock input

PD 3 power-down pad input

T1 4 test pad (connected to VSS)

VSS 5 ground

VLCD 6 VLCD input; note 1

R9 to R16 7 to 14 LCD row driver outputs 9 to 16

R18 15 LCD row driver output 18

C60 to C1 16 to 23, 26 to 50,53 to 77, 80, 81

LCD column driver outputs 60 to 1

R8 to R1 82 to 89 LCD row driver outputs 8 to 1

R17 90 LCD row driver output 17

SCL 91 I2C-bus serial clock input

SDA 92 I2C-bus serial data input/output

E 93 data bus clock input

RS 94 register select input

R/W 95 read/write input

DB7 96 bit of bi-directional data bus




DB3/SA0 100 bit of bi-directional data bus/I2C-bus address pin




1998 May 11 6



Table 1 Pin functions; note 1

Note

1. When the I2C-bus is used, the parallel interface pin E must be defined as E = 0. In I2C-bus read mode DB7 to DB0should be connected to VDD or left open-circuit.

a) When the parallel bus is used, pins SCL and SDA must be connected to VSS or VDD; they may not be leftunconnected.

b) If the 4-bit interface is used without reading out from the PCF2103 (i.e. R/W is set permanently to logic 0), theunused ports DB0 to DB3 can either be set to VSS or VDD instead of leaving them open.

NAME FUNCTION DESCRIPTION

RS register select RS selects the register to be accessed for read and write; there is an internal pull-upon this pin

RS = 0 selects the instruction register for write and the busy flag and addresscounter for read

RS = 1 selects the data register for both read and write

R/W read/write R/W selects either the read (R/W = 1) or write (R/W = 0) operation; there is aninternal pull-up on this pin

E data bus clock pin E is set HIGH to signal the start of a read or write operation; data is clocked in orout of the chip on the negative edge of the clock

DB7 to DB0 data bus the bi-directional, 3-state data bus transfers data between the system controller andthe PCF2103; DB7 may be used as the busy flag, signalling that internal operationsare not yet completed; in 4-bit operations the 4 higher order lines DB7 to DB4 areused; DB3 to DB0 must be left open-circuit; there is an internal pull-up on each of thedata lines

C1 to C60 column driveroutputs

these pins output the data for columns

R1 to R18 row driveroutputs

these pins output the row select waveforms to the display; R17 and R18 drive theicons

VLCD LCD powersupply

positive power supply for the liquid crystal display

OSC oscillator when the on-chip oscillator is used this pin must be connected to VDD; an externalclock signal, if used, is input at this pin

SCL serial clock line input for the I2C-bus clock signal

SDA serial data line I/O for the I2C-bus data line

SA0 address pin the hardware sub-address line is used to program the device sub-address for twodifferent PCF2103s on the same I2C-bus

T1 test pad must be connected to VSS; not user accessible

PD power-down pad PD selects chip power-down mode; for normal operation PD = 0

1998 May 11 7



7 FUNCTIONAL DESCRIPTION

7.1 LCD bias voltage generator

The intermediate bias voltages for the LCD display are generated on-chip. This removes the need for an externalresistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends onthe multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels and is given by the relationships givenin Tables 2 and 3. Using a 5-level bias scheme for 1 : 18 maximum rate allows VLCD <5 V for most LCD liquids.

Table 2 Optimum/maximum values for VOP (off pixels start darkening; Voff = Vth)

Table 3 Minimum values for VOP (on pixels clearly visible; Von > Vth)

MUX RATE NUMBER OF LEVELS V on/Vth VOP/Vth VOP (typical; for V th = 1.4 V)

1 : 18 5 1.272 3.7 5.2 V

1 : 2 3 2.236 2.283 3.9 V

MUX RATE NUMBER OF LEVELS V on/Vth VOP/Vth VOP (typical; for V th = 1.4 V)

1 : 18 5 1.12 3.2 4.6 V

1 : 2 3 1.2 1.5 2.1 V

7.2 Oscillator

The on-chip oscillator provides the clock signal for thedisplay system. No external components are required andpin OSC must be connected to VDD.

7.3 External clock

If an external clock is to be used, it is input at the OSC pin.The resulting display frame frequency is given by

Only in the power-down state is the clock allowed to bestopped (OSC connected to VSS), otherwise the LCD isfrozen in a DC state.

7.4 Power-on reset

The on-chip power-on reset block initializes the chip afterpower-on or power failure. This is a synchronous reset andrequires 3 oscillator cycles to be executed. Afterwards, aclear display is initiated.

7.5 Power-down mode

The chip can be put into power-down mode where all staticcurrents are switched off (no internal oscillator, no biaslevel generation, all LCD outputs are internally connectedto VSS) when PD = 1.

fframe

fosc

3072-------------=

During power-down, the whole chip is being reset and willrestart with a clear display after power-down. Therefore,the whole chip has to be initialized after a power-down asafter an initial power-up.

7.6 Registers

The PCF2103 has two 8-bit registers, an InstructionRegister (IR) and a Data Register (DR). The RegisterSelect signal (RS) determines which register will beaccessed. The instruction register stores instruction codessuch as ‘display clear’ and ‘cursor shift’, and addressinformation for the Display Data RAM (DDRAM) andCharacter Generator RAM (CGRAM). The instructionregister can be written from but not read by the systemcontroller. The data register temporarily stores data to beread from the DDRAM and CGRAM. When reading, datafrom the DDRAM or CGRAM corresponding to the addressin the instruction register is written to the data register priorto being read by the ‘read data’ instruction.

7.7 Busy flag

The busy flag indicates the internal status of the PCF2103.Logic 1 indicates that the chip is busy and furtherinstructions will not be accepted. The busy flag is output atpin DB7 when RS = 0 and R/W = 1. Instructions shouldonly be written after checking that the busy flag is logic 0or waiting for the required number of cycles.

1998 May 11 8



7.8 Address Counter (AC)

The address counter assigns addresses to the DDRAMand CGRAM for reading and writing and is set by thecommands ‘set CGRAM address’ and ‘set DDRAMaddress’. After a read/write operation the address counteris automatically incremented or decremented by 1.The address counter contents are output to the bus(DB6 to DB0) when RS = 0 and R/W = 1.

7.9 Display Data RAM (DDRAM)

The DDRAM stores up to 80 characters of display datarepresented by 8-bit character codes. RAM locationswhich are not used for storing display data can be used asgeneral purpose RAM. The basic RAM-to-displayaddressing scheme is shown in Fig.2. With no display shiftthe characters represented by the codes in the first24 RAM locations starting at address 00 in line 1 aredisplayed. Figures 3 and 4 show the display mapping forright and left shift respectively.

When data is written to or read from the DDRAMwrap-around occurs from the end of one line to the start ofthe next line. When the display is shifted each line wrapsaround within itself, independently of the others. Thus alllines are shifted and wrapped around together.The address ranges and wrap-around operations for thevarious modes are shown in Table 4.

7.10 Character Generator ROM (CGROM)

The Character Generator ROM (CGROM) generates240 character patterns in 5 × 8 dot format from 8-bitcharacter codes. Figure 6 shows the character set that iscurrently implemented.

7.11 Character Generator RAM (CGRAM)

Up to 16 user defined characters may be stored in theCGRAM. Some CGRAM characters (see Fig.14) are alsoused to drive icons (6 if icons blink and both icon rows areused in application; 3 if no blink but both icon rows areused in application; 0 if no icons are driven by the iconrows). The CGROM and CGRAM use a common addressspace, of which the first column is reserved for theCGRAM (see Fig.6). Figure 7 shows the addressingprinciple for the CGRAM.

7.12 Cursor control circuit

The cursor control circuit generates the cursor (underlineand/or cursor blink as shown in Fig.5) at the DDRAMaddress contained in the address counter. When theaddress counter contains the CGRAM address the cursorwill be inhibited.

7.13 Timing generator

The timing generator produces the various signalsrequired to drive the internal circuitry. Internal chipoperation is not disturbed by operations on the data buses.

7.14 LCD row and column drivers

The PCF2103 contains 18 row and 60 column drivers,which connect the appropriate LCD bias voltages insequence to the display in accordance with the data to bedisplayed. R17 and R18 drive the icon rows.

The bias voltages and the timing are selectedautomatically when the number of lines in the display isselected. Figures 8, 9 and 10 show typical waveforms.Unused outputs should be left unconnected.

Table 4 Address space and wrap-around operation

Notes

1. Moves to next line.

2. Stays within line.

MODE ADDRESS SPACEREAD/WRITE

WRAP-AROUND (1)DISPLAY SHIFT

WRAP-AROUND (2)

1 × 24 00H to 4FH 4FH to 00H 4FH to 00H

2 × 12 00H to 27H; 40H to 67H 27H to 40H; 67H to 00H 27H to 00H; 67H to 40H

1998 May 11 9



Fig.2 DDRAM-to-display mapping: no shift.


00 01 02 03 04 15 16 17 18 19 4C 4D 4E 4F

non-displayed DDRAM addresses

64 65 66 6740 41 42 43 44 49 4A 4B 4C 4D

00 01 02 03 04 09 0A 0B 0C 0D 24 25 26 27

non-displayed DDRAM address

line 1

line 2

MGE991

DDRAMaddress

2-line display

1 2 3 4 5 22 23 24

1 2 3 4 5 10 11 12

1 2 3 4 5 10 11 12

displayposition

DDRAMaddress

1-line display

Fig.3 DDRAM-to-display mapping: right shift.

handbook, halfpage

MGE992

27 00 01 02 03

67 40 41 42 43

08 09 0A

48 49 4A

DDRAMaddress

line 1

line 2

2-line display

1 2 3 4 5 22 23 24

1 2 3 4 5 10 11 12

1 2 3 4 5 10 11 12

4F 00 01 02 03 14 15 16

displayposition

DDRAMaddress

1-line display

1998 May 11 10



Fig.4 DDRAM-to-display mapping: left shift.

handbook, halfpage

01 04 05

41 42 43 44 45

0A 0B 0C

4A 4B 4C

DDRAMaddress

line 1

line 2

2-line display

1 2 3 4 5 22 23 24

1 2 3 4 5 10 11 12

1 2 3 4 5 10 11 12

01 04 05

02 03

02 03 16 17 18

displayposition

DDRAMaddress

1-line display

MGE993

Fig.5 Cursor and blink display examples.

MGA801cursor

5 x 7 dot character font alternating display

cursor display example blink display example

1998 May 11 11



Fig.6 Character set ‘E’ in CGROM.


MGD689

0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

upper4 bits

lower4 bits

xxxx 0000

xxxx 0001

xxxx 0010

xxxx 0011

xxxx 0100

xxxx 0101

xxxx 0110

xxxx 0111

xxxx 1000

xxxx 1001

xxxx 1010

xxxx 1011

xxxx 1100

xxxx 1101

xxxx 1110

xxxx 1111 16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

1998 May 11 12



Fig.7 Relationship between CGRAM addresses and data and display patterns.

Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6.

CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR withthe cursor. Data in the 8th position will appear in the cursor position.

Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.6.

As shown in Figs 6 and 7, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 correspondsto selection for display.

Only bits 0 to 5 of the CGRAM address are set by the ‘set CGRAM address’ command. Bit 6 can be set using the ‘set DDRAM address’ command inthe valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the ‘read busy flag and addresscounter’ command; see Table 7.


MGE995

7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 4 3 2 1 0

higherorderbits

lowerorderbits

lowerorderbits

higherorderbits

lowerorderbits

higherorderbits

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 1 0 0 00 1 0 0 0 00 1 1 01 0 0 0 0 01 0 1 0 0 01 1 0 0 0 01 1 1 0 0 0 0 0

0 0 0 0 0 00 0 1 0 0 00 1 0

0 0 0 00 1 11 0 01 0 1 0 0 0 01 1 0 0 0 0 01 1 1 0 0 0 0 0

0 0 1

0 0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 0 1 0

0 0 0 0 1 1 1 10 0 0 0 1 1 1 10 0 0 0 1 1 1 10 0 0 0 1 1 1 1

0 10 0 0 0 0

1 0 01 0 11 1 01

1111

1111

1111

1111 1 1

character codes(DDRAM data)

CGRAMaddress

character patterns(CGRAM data)

4 3 2 1 0

00 0 01 1 1

0 0 00

0 01 00 0 010 0 0

11

10 0

11

11 1 11

111

0 0 0

11 0 10 0 0

1 1 10

1 11 10 1 000 1 0

01

00 0

01

10 1 00

100

0 0 0

character code(CGRAM data)

characterpattern

example 1

cursorposition

characterpattern

example 2

1998 May 11 13



Fig.8 Typical LCD waveforms; character mode.


MGE996

state 1 (ON)

state 2 (OFF)

frame n + 1 frame n

1 2 3 18 1 2 3 18

ROW 1

VLCDV2V3/V4V5VSS

ROW 9

VLCDV2V3/V4V5VSS

ROW 2

VLCDV2V3/V4V5VSS

COL1

VLCDV2V3/V4V5VSS

COL2

VLCDV2V3/V4V5VSS

0 Vstate 1

VOP

0.5VOP0.25VOP

−0.25VOP−0.5VOP

−VOP

0 Vstate 2

VOP

0.5VOP0.25VOP

−0.25VOP−0.5VOP

−VOP

R1

R2

R3

R4

R5

R6

R7

R8

R9

1998 May 11 14



Fig.9 Mux 1 : 2 LCD waveforms; icon mode.


MGE997

frame n + 1 frame n

VLCD2/31/3

VSS

VLCD

2/31/3

VSS

VLCD2/31/3

VSS

VLCD2/31/3

VSS

VLCD2/31/3

VSS

VLCD2/31/3

VSS

VLCD2/31/3

VSS

COL 4 OFF/OFF

COL 3 ON/ON

COL 2 OFF/ON

COL 1 ON/OFF

ROW 1 to 16

ROW 18

ROW 17

only icons aredriven (MUX 1 : 2)

1998 May 11 15



Fig.10 Mux 1 : 2 LCD waveforms; icon mode.

VON(rms) = 0.745 VOP.

VOFF(rms) = 0.333 VOP.

DVON

VOFF------------- 2.23= =


MGE998

frame n + 1 frame n

VOP2/3 VOP1/3 VOP

0−1/3 VOP−2/3 VOP

−VOP

VOP2/3 VOP1/3 VOP

0−1/3 VOP−2/3 VOP

−VOP

VOP2/3 VOP1/3 VOP

0−1/3 VOP−2/3 VOP

−VOP

state 3COL 1 -

ROW 1 to 16

state 2COL 2 -ROW 17

state 1COL 1 -ROW 17

state 3 (OFF)

R17

R18

R1-16

VPIXEL

state 1 (ON)

state 2 (OFF)

1998 May 11 16



7.15 Reset function

The PCF2103 automatically initializes (resets) when power is turned on. The reset executes a ‘clear display’ instruction,requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 5.

Table 5 State after reset

STEP INSTRUCTION RESET STATE (BIT/REGISTER) RESET STATE (DESCRIPTION)

1 clear display

2 entry mode set I/D = 1 +1 (increment)

S = 0 no shift

3 display control D = 0 display off

C = 0 cursor off

B = 0 cursor character blink off

4 function set DL = 1 8-bit interface

M = 0 1-line display

H = 0 normal instruction set

5 default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until initializationends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 16 and 17

6 icon control IM, IB = 00 icons/icon blink disabled

7 display/screen configuration L, P, Q = 000 default configurations

8 I2C-bus interface reset

1998 May 11 17



8 INSTRUCTIONS

Only two PCF2103 registers, the Instruction Register (IR)and the Data Register (DR) can be directly controlled bythe microcontroller. Before internal operation, controlinformation is stored temporarily in these registers to allowinterface to various types of microcontrollers whichoperate at different speeds or to allow interface toperipheral control ICs. The format for instructions whenI2C-bus control is used is shown in Table 6. The PCF2103operation is controlled by the instructions given in Table 7together with their execution time. Details are explained insubsequent sections.

Instructions are of 4 types, those that:

1. Designate PCF2103 functions such as display format,data length, etc.

2. Set internal RAM addresses

3. Perform data transfer with internal RAM

4. Others.

In normal use, instructions that perform data transfer withinternal RAM are used most frequently. However,automatic incrementing by 1 (or decrementing by 1) ofinternal RAM addresses after each data write lessens themicrocontroller program load. The display shift in particularcan be performed concurrently with display data write,enabling the designer to develop systems in minimum timewith maximum programming efficiency.

During internal operation, no instruction other than the‘read busy flag and address counter’ instruction will beexecuted. Because the busy flag is set to logic 1 while aninstruction is being executed, the user should verify thatthe busy flag is at logic 0 before sending the nextinstruction or wait for the maximum instruction executiontime, as given in Table 7. An instruction sent while thebusy flag is logic 1 will not be executed.

Table 6 Instruction set for I2C-bus commands

Note

1. R/W is set together with the slave address.

CONTROL BYTE COMMAND BYTE I 2C-BUS COMMANDS

Co RS 0 0 0 0 0 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1

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Product specification

LCD

controllers/driversP

CF

2103 family

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Table 7 Instruction set with parallel bus commands; note 1

INSTRUCTION RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DESCRIPTIONREQUIRED

CLOCKCYCLES

H = 0 or 1

NOP 0 0 0 0 0 0 0 0 0 0 no operation 3

Function set 0 0 0 0 1 DL 0 M 0 H sets interface Data Length (DL) and number ofdisplay lines (M); extended instruction set control(H)

3

Read busy flagand addresscounter

0 1 BF AC reads the Busy Flag (BF) indicating internaloperating is being performed and reads addresscounter contents

0

Read data 1 1 read data reads data from CGRAM or DDRAM 3

Write data 1 0 write data writes data from CGRAM or DDRAM 3

H = 0

Clear display 0 0 0 0 0 0 0 0 0 1 clears entire display and sets DDRAM address 0in address counter

165

Return home 0 0 0 0 0 0 0 0 1 0 sets DDRAM address 0 in address counter; alsoreturns shifted display to original position; DDRAMcontents remain unchanged

3

Entry mode set 0 0 0 0 0 0 0 1 I/D S sets cursor move direction and specifies shift ofdisplay; these operations are performed duringdata write and read

3

Display control 0 0 0 0 0 0 1 D C B sets entire display on/off (D), cursor on/off (C) andblink of cursor position character (B); D = 0(display off) puts chip into power-down mode

3

Cursor/displayshift

0 0 0 0 0 1 S/C R/L 0 0 moves cursor and shifts display without changingDDRAM contents

3

Set CGRAMaddress

0 0 0 1 ACG sets CGRAM address; bit 6 is to be set by thecommand ‘set DDRAM address’; look at thedescription of the commands

3

Set DDRAMaddress

0 0 1 ADD sets DDRAM address 3

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LCD


CF

2103 family


Note

1. X = don’t care.

H = 1

Reserved 0 0 0 0 0 0 0 0 0 1 do not use −Screenconfiguration

0 0 0 0 0 0 0 0 1 L set screen configuration 3

Displayconfiguration

0 0 0 0 0 0 0 1 P Q set display configuration 3

Icon control 0 0 0 0 0 0 1 IM IB 0 set icon mode (IM), icon blink (IB) 3

Reserved 0 0 0 0 0 1 X X X X do not use −Reserved 0 0 0 1 X X X X X X do not use −Reserved 0 0 1 X X X X X X X do not use −

INSTRUCTION RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DESCRIPTIONREQUIRED

CLOCKCYCLES

1998 May 11 20



Table 8 Specification of mnemonics used in Table 7

BIT LOGIC 0 LOGIC 1

I/D decrement increment

S display freeze display shift

D display off display on

C cursor off cursor on

B cursor character blink off: character at cursorposition does not blink

cursor character blink on: character at cursorposition blinks

S/C cursor move display shift

R/L left shift right shift

DL 4 bits 8 bits

H use basic instruction set use extended instruction set

L (ignored,if M = 1)

left/right screen: standard connection(as in PCF2114);1st 12 characters of 24: columns are from 1 to 60;2nd 12 characters of 24: columns are from 1 to 60

left/right screen: mirrored connection(as in PCF2116);1st 12 characters of 24: columns are from 1 to 60;2nd 12 characters of 24: columns are from 60 to 1

P column data: left to right (as in PCF2116);column data is displayed from 1 to 60

column data: right to left;column data is displayed from 60 to 1

Q row data: top to bottom (as in PCF2116);row data is displayed from 1 to 16 and icon rowdata is in 17 and 18

row data: bottom to top;row data is displayed from 16 to 1 and iconrow data is in 18 and 17

IM character mode; full display icon mode; only icons displayed

IB icon blink disabled icon blink enabled

M 1-line by 24 display 2-line by 12 display

C0 last control byte; see Table 6 another control byte follows after data/command

1998 May 11 21



Fig.11 4-bit transfer example.

MGA804

RS

E

DB7

R/W

DB6

DB5

DB4

instructionwrite

busy flag andaddress counter read

data registerread

IR7 IR3 BF AC3 DR7 DR3

IR6 IR2 AC6 AC2 DR6 DR2



Fig.12 An example of 4-bit data transfer timing sequence.

IR7 and IR3: instruction 7th and 3rd bit.

AC3: address counter 3rd bit.

D7 and D3: data 7th and 3rd bit.

MGA805

RS

E

internal

DB7

R/W

internal operation

IR7 IR3 AC3 D7 D3not

busyAC3busy

instructionwrite

busy flagcheck

busy flagcheck

instructionwrite

1998 May 11 22



Fig.13 Example of busy flag checking timing sequence.

MGA806

instructionwrite

busy flagcheck

busy flagcheck

busy flagcheck

instructionwrite

internal operation

RS

E

internal

DB7

R/W

data busy busynot

busy data

8.1 Clear display

‘Clear display’ writes character code 20H into all DDRAMaddresses (the character pattern for character code 20Hmust be a blank pattern), sets the DDRAM addresscounter to logic 0 and returns display to its original positionif it was shifted. Thus, the display disappears and thecursor or blink position goes to the left edge of the display.Sets entry mode I/D = 1 (increment mode). S of entrymode does not change.

The instruction ‘clear display’ requires extra executiontime. This may be allowed by checking the Busy Flag (BF)or by waiting until the 165 clock cycles have elapsed.The latter must be applied where no read-back options areforeseen, as in some Chip-On-Glass (COG) applications.

8.2 Return home

‘Return home’ sets the DDRAM address counter to logic 0and returns display to its original position if it was shifted.DDRAM contents do not change. The cursor or blinkposition goes to the left of the first display line. I/D and S ofentry mode do not change.

8.3 Entry mode set

8.3.1 I/D

When I/D = 1 (0) the DDRAM or CGRAM addressincrements (decrements) by 1 when data is written into orread from the DDRAM or CGRAM. The cursor or blinkposition moves to the right when incremented and to theleft when decremented. The cursor underline and cursorcharacter blink are inhibited when the CGRAM isaccessed.

8.3.2 S

When S = 1, the entire display shifts either to the right(I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thusit looks as if the cursor stands still and the display moves.The display does not shift when reading from the DDRAM,or when writing into or reading out of the CGRAM. WhenS = 0 the display does not shift.

1998 May 11 23



8.4 Display control (and partial power-down mode)

8.4.1 D

The display is on when D = 1 and off when D = 0. Displaydata in the DDRAM are not affected and can be displayedimmediately by setting D to logic 1.

When the display is off (D = 0) the chip is in partialpower-down mode:

• The LCD outputs are connected to VSS

• Bias generator is turned off.

3 oscillator cycles are required after sending the‘display off’ instruction to ensure all outputs are at VSS,afterwards OSC can be stopped. If the oscillator is runningduring partial power-down mode (‘display off’) the chip canstill execute instructions. Even lower current consumptionis obtained by inhibiting the oscillator (OSC = VSS).

To ensure IDD < 2 µA the parallel bus pins DB7 to DB0should be connected to VDD; RS and R/W to VDD or leftopen-circuit and PD to VDD. Recovery from power-downmode: put PD back to logic 0, if necessary put OSC backto VDD and send a ‘display control’ instruction with D = 1 toenable the display again.

8.4.2 C

The cursor is displayed when C = 1 and inhibited whenC = 0. Even if the cursor disappears, the display functionsI/D, etc. remain in operation during display data write.The cursor is displayed using 5 dots in the 8th line (seeFig.5).

8.4.3 B

The character indicated by the cursor blinks when B = 1.The cursor character blink is displayed by switchingbetween display characters and all dots on with a period of

approximately 1 s, with

The cursor underline and the cursor character blink can beset to display simultaneously.

8.5 Cursor or display shift

‘Cursor/display shift’ moves the cursor position or thedisplay to the right or left without writing or reading displaydata. This function is used to correct a character or movethe cursor through the display. In 2-line displays, thecursor moves to the next line when it passes the lastposition (40) of the line. When the displayed data is shiftedrepeatedly all lines shift at the same time; displayedcharacters do not shift into the next line.

fBLINK

fosc

52224----------------=

The Address Counter (AC) content does not change if theonly action performed is shift display, but increments ordecrements with the ‘cursor shift’.

8.6 Function set

8.6.1 DL (PARALLEL MODE ONLY)

Sets interface data width. Data is sent or received in bytes(DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4)when DL = 0. When 4-bit width is selected, data istransmitted in two cycles using the parallel bus. In a 4-bitapplication DB3 to DB0 should be left open-circuit (internalpull-ups). Hence in the first ‘function set’ instruction afterpower-on N and H are set to logic 1. A second‘function set’ must then be sent (2 nibbles) to set N and Hto their required values.

‘Function set’ from the I2C-bus interface sets the DL bit tologic 1.

8.6.2 M

Chooses either 1-line by 24 display (M = 0) or 2-line by12 display (M = 1).

8.6.3 H

When H = 0 the chip can be programmed via the standard11 instruction codes used in the PCF2116 and other LCDcontrollers.

When H = 1 the extended range of instructions will beused. These are mainly for controlling the displayconfiguration and the icons.

8.7 Set CGRAM address

‘Set CGRAM address’ sets bits 5 to 0 of the CGRAMaddress ACG into the address counter (binary A[5] to A[0]).Data can then be written to or read from the CGRAM.

Attention: the CGRAM address uses the same addressregister as the DDRAM address and consists of 7 bits(binary A[6] to A[0]). With the ‘set CGRAM address’command, only bits 5 down to 0 are set. Bit 6 can be setusing the ‘set DDRAM address’ command first, or by usingthe auto-increment feature during CGRAM write.All bits 6 to 0 can be read using the‘read busy flag and address counter’ command.

When writing to the lower part of the CGRAM, ensure thatbit 6 of the address is not set (e.g. by an earlier DDRAMwrite or read action).

1998 May 11 24



8.8 Set DDRAM address

‘Set DDRAM address’ sets the DDRAM address ADD intothe address counter (binary A[6] to A[0]). Data can then bewritten to or read from the DDRAM.

8.9 Read busy flag and address counter

‘Read busy flag and address counter’ reads the Busy Flag(BF) and Address Counter (AC). BF = 1 indicates that aninternal operation is in progress. The next instruction willnot be executed until BF = 0, so BF should be checkedbefore sending another instruction.

At the same time, the value of the address counterexpressed in binary A[6] to A[0] is read out. The addresscounter is used by both CGRAM and DDRAM, and itsvalue is determined by the previous instruction.

8.10 Write data to CGRAM or DDRAM

‘Write data’ writes binary 8-bit data D[7] to D[0] to theCGRAM or the DDRAM.

Whether the CGRAM or DDRAM is to be written into isdetermined by the previous ‘set CGRAM address’ or ‘setDDRAM address’ command. After writing, the addressautomatically increments or decrements by 1, inaccordance with the entry mode. Only bits D[4] to D[0] ofCGRAM data are valid, bits D[7] to D[5] are ‘don’t care’.

8.11 Read data from CGRAM or DDRAM

‘Read data’ reads binary 8-bit data D[7] to D[0] from theCGRAM or DDRAM.

The most recent ‘set address’ command determineswhether the CGRAM or DDRAM is to be read.

The ‘read data’ instruction gates the content of the DataRegister (DR) to the bus while pin E is HIGH. After pin Egoes LOW again, internal operation increments (ordecrements) the AC and stores RAM data correspondingto the new AC into the DR.

It should be noted that there are only three instructions thatupdate the Data Register (DR). These are:

• ‘set CGRAM address’

• ‘set DDRAM address’

• ‘read data’ from CGRAM or DDRAM.

Other instructions (e.g. ‘write data’, ‘cursor/display shift’,‘clear display’, ‘return home’) do not modify the dataregister content.

8.12 Extended function set instructions andfeatures

8.12.1 NEW INSTRUCTIONS

H = 1 sets the chip into alternate instruction set mode.

8.12.2 ICON CONTROL

The PCF2103 can drive up to 120 icons. See Fig.14 forCGRAM to icon mapping.

8.12.3 IM

When IM = 0 the chip is in character mode. In charactermode characters and icons are driven (mux 1 : 18).

When IM = 1 the chip is in icon mode. In icon mode onlythe icons are driven (mux 1 : 2).

8.12.4 IB

Icon blink control is independent of the cursor/characterblink function.

When IB = 0 icon blink is disabled. Icon data is stored inCGRAM character 0 to 2 (3 × 8 × 5 = 120 bits for120 icons).

When IB = 1 icon blink is enabled. In this case each icon iscontrolled by two bits. Blink consists of two half phases(corresponding to the cursor on and off phases called evenand odd phases hereafter).

Icon states for the even phase are stored in CGRAMcharacters 0 to 2 (3 × 8 × 5 = 120 bits for 120 icons).These bits also define the icon state when the icon blink isnot used.

Icon states for the odd phase are stored in CGRAMcharacter 4 to 6 (another 120 bits for the 120 icons). Whenicon blink is disabled CGRAM characters 4 to 6 may beused as normal CGRAM characters.

1998 May 11 25



Table 9 Blink effect for icons and cursor character blink

PARAMETER EVEN PHASE ODD PHASE

Cursor underline on off

Cursor character blink block (all on) normal (display character)

Icons state 1: CGRAM characters 0 to 2 state 2: CGRAM characters 4 to 6

Fig.14 CGRAM-to-icon mapping.

CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off.

Data in character codes 0 to 2 define the icon states when icon blink is disabled or during the even phase when icon blink is enabled.

Data in character codes 4 to 6 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).


MGG001

116-120 odd (blink) 18/56-60 0 0 0 0 0 1 1 0

icon view

0 1 1 0 0 1 1 0 0 1 1 0

1-5 odd (blink) 17/1-5 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0

116-120 even 18/56-60 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 0 1

61-65 even 18/1-5 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 0

56-60 even 17/56-60 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1

11-15 even 17/11-15 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0

6-10 even 17/6-10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0

1-5 even 17/1-5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1

7 6 5 4 3 2 1 0

MSB LSB LSBMSB MSBLSB

6 5 4 3 2 1 0 4 3 2 1 0

icon no. phase ROW/COL character codes CGRAM address CGRAM data

handbook, full pagewidth COL 1 to 5

1 2 3 4 5

61 62 63 64 65

display:

ROW 17 –

ROW 18 –

block of 5 columns

COL 6 to 10

6 7 8 9 10

66 67 68 69 70

COL 56 to 60

56 57 58 59 60

116 117 118 119 120

MGE999

1998 May 11 26



8.12.5 SCREEN CONFIGURATION

The default value for L is logic 0. In the event of L = 0 thetwo halves of a split screen are connected in a standardway i.e. column 1/61, 2/62 to 60/120. In the event of L = 1the two halves of a split screen are connected in a mirroredway i.e. column 1/120, 2/119 to 60/61. This allows singlelayer PCB or glass layout.

8.12.6 DISPLAY CONFIGURATION

The default value for P and Q is logic 0. P = 1 mirrors thecolumn data whereas Q = 1 mirrors the row data.

8.12.7 REDUCING CURRENT CONSUMPTION

Reducing current consumption can be achieved by one ofthe options mentioned in Table 10.

Table 10 Reducing current consumption

ORIGINAL MODE ALTERNATIVE MODE

Character mode icon mode (control bit IM)

Display on display off (control bit D)

9 INTERFACE TO MICROCONTROLLER

9.1 Parallel interface

The PCF2103 can send data in either two 4-bit operationsor one 8-bit operation and can thus interface to 4-bit or8-bit microcontrollers.

In 8-bit mode data is transferred as 8-bit bytes using the8 data lines DB7 to DB0. Three further control lines E, RSand R/W are required; see Table 1.

In 4-bit mode data is transferred in two cycles of 4 bitseach using pins DB7 to DB4 for transaction. The higherorder bits (corresponding to DB7 to DB4 in 8-bit mode) aresent in the first cycle and the lower order bits (DB3 to DB0in 8-bit mode) in the second. Data transfer is completeafter two 4-bit data transfers. Note that two cycles are alsorequired for the busy flag check. 4-bit operation is selectedby instruction. See Figs 11 to 14 for examples of busprotocol.

In 4-bit mode pins DB3 to DB0 must be left open-circuit.They are pulled up to VDD internally.

1998 May 11 27



9.2 I2C-bus interface

9.2.1 CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for bidirectional, two-line communicationbetween different ICs or modules. The two lines are aserial data line (SDA) and a Serial Clock Line (SCL).Both lines must be connected to a positive supply via apull-up resistor. Data transfer may be initiated only whenthe bus is not busy.

Each byte of eight bits is followed by an acknowledge bit.The acknowledge bit is a HIGH-level signal put on the busby the transmitter during which time the master generatesan extra acknowledge related clock pulse. A slave receiverwhich is addressed must generate an acknowledge afterthe reception of each byte. Also a master receiver mustgenerate an acknowledge after the reception of each bytethat has been clocked out of the slave transmitter.

The device that acknowledges must pull down the SDAline during the acknowledge clock pulse, so that the SDAline is stable LOW during the HIGH period of theacknowledge related clock pulse (set-up and hold timesmust be taken into consideration). A master receiver mustsignal an end of data to the transmitter by not generatingan acknowledge on the last byte that has been clocked outof the slave. In this event the transmitter must leave thedata line HIGH to enable the master to generate a STOPcondition.

9.2.2 I2C-BUS PROTOCOL

Before any data is transmitted on the I2C-bus, the devicewhich should respond is addressed first. The addressing isalways carried out with the first byte transmitted after thestart procedure. The I2C-bus configuration for the differentPCF2103 read and write cycles is shown in Figs 20 to 21.The slow down feature of the I2C-bus protocol (receiverholds SCL low during internal operations) is not used in thePCF2103.

9.2.3 DEFINITIONS

• Transmitter: the device which sends the data to the bus

• Receiver: the device which receives the data from thebus

• Master: the device which initiates a transfer, generatesclock signals and terminates a transfer

• Slave: the device addressed by a master

• Multi-master: more than one master can attempt tocontrol the bus at the same time without corrupting themessage

• Arbitration: procedure to ensure that, if more than onemaster simultaneously tries to control the bus, only oneis allowed to do so and the message is not corrupted

• Synchronization: procedure to synchronize the clocksignals of two or more devices.

1998 May 11 28



Fig.15 System configuration.

MGA807

SDA

SCL

MASTERTRANSMITTER/

RECEIVER

MASTERTRANSMITTER

SLAVETRANSMITTER/

RECEIVER

SLAVERECEIVER

MASTERTRANSMITTER/

RECEIVER

Fig.16 Bit transfer.


MBC621

data linestable;

data valid

changeof dataallowed

SDA

SCL

Fig.17 Definition of START and STOP conditions.


MBC622

SDA

SCLP

STOP condition

SDA

SCLS

START condition

Fig.18 Acknowledgement on the I2C-bus.


MBC602

S

STARTcondition

9821

clock pulse foracknowledgement

not acknowledge

acknowledge

DATA OUTPUTBY TRANSMITTER

DATA OUTPUTBY RECEIVER

SCL FROMMASTER

1998M

ay11

29

Philips S

emiconductors


LCD


CF

2103 family



MGL250

SA0

S P0 1 1 1 0 1 0 A

slave address

CONTROL BYTE A1

Co

DATA BYTE A CONTROL BYTE A

R/W

0

Co updatedata pointer

1 byte n ≥ 0 bytes2n ≥ 0 bytes

DATA BYTE A

acknowledgementfrom PCF2103

RS RS

SA0

0 1 1 1 0 1 0

PCF2103slave address R/W

Fig.19 Master transmits to slave receiver; write mode.

1998M

ay11

30

Philips S

emiconductors


LCD


CF

2103 family


Fig.20 Master reads after setting word address; write word address, set RS; ‘read data’.

(1) Last data byte is a dummy byte (may be omitted).

agewidth

MGG003

SA0

S 0 1 1 1 0 1 0 A

slave address

CONTROL BYTE A1

Co

DATA BYTE A CONTROL BYTE A

R/W

0

Co


updatedata pointer

1 byte n ≥ 0 bytes

n bytes last byte

2n 0 bytes

DATA BYTE(1) A

acknowledgement

SA0

S 1 A DATA BYTE A 1 P SLAVEADDRESS DATA BYTE

acknowledgement acknowledgement no acknowledgement

R/W

RS RS

1998 May 11 31



Fig.21 Master reads slave immediately after first byte; read mode (RS previously defined).

dbook, full pagewidth

MGL251


updatedata pointer

n bytes last byte

SA0

S 1 A DATA BYTE A 1 P SLAVEADDRESS DATA BYTE

acknowledgementfrom PCF2103

acknowledgementfrom master

no acknowledgementfrom master

R/W

Fig.22 I2C-bus timing diagram.

dbook, full pagewidth

SDA

MGA728

SDA

SCL

tSU;STA t SU;STO

tHD;STA

t BUF t LOW

t HD;DAT t HIGHt r

t f

t SU;DAT

1998 May 11 32



10 LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134).

11 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it isdesirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”).

SYMBOL PARAMETER MIN. MAX. UNIT

VDD supply voltage −0.5 +6.5 V

VLCD LCD supply voltage −0.5 +7.5 V

VI(1) input voltage on pins OSC, RS, R/W, E and DB7 to DB0 −0.5 VDD + 0.5 V

VI(2) input voltage on pins SCL and SDA −0.5 +6.5 V

VO output voltage on pins R1 to R18, C1 to C60 and VLCD −0.5 VLCD + 0.5 V

II DC input current −10 +10 mA

IO DC output current −10 +10 mA

IDD, ISS and ILCD VDD, VSS or VLCD current −50 +50 mA

Ptot total power dissipation − 400 mW

P/out power dissipation per output − 100 mW

Tstg storage temperature −65 +150 °C

1998 May 11 33



12 DC CHARACTERISTICSVDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDD supply voltage 1.8 − 5.5 V

VLCD LCD supply voltage 2.2 − 6.5 V

ISS supply current note 1 − 60 120 µA

VDD = 3 V; VLCD = 5 V;notes 1 and 2

− 45 80 µA

icon mode; VDD = 3 V;VLCD = 2.5 V;notes 1 and 2

− 25 45 µA

power-down mode;VDD = 3 V; VLCD = 2.5 V;DB7 to DB0,RS and R/W = 1;OSC = 0; PD = 1; note 1

− 2 6 µA

VPOR power-on reset voltage note 3 − 1.3 1.6 V

Logic

VIL LOW-level input voltage onpins T1, E, RS, R/W,DB7 to DB0 and SA0

0 − 0.3VDD V

VIH HIGH-level input voltage onpins T1, E, RS, R/W,DB7 to DB0 and SA0

0.7VDD − VDD V

VIL(PD) LOW-level input voltage onpin PD

0 − 0.2VDD V

VIH(PD) HIGH-level input voltage onpin PD

0.8VDD − VDD V

VIL(OSC) LOW-level input voltage onpin OSC

0 − VDD − 1.5 V

VIH(OSC) HIGH-input voltage on pin OSC VDD − 0.1 − VDD V

IOL(DB) LOW-level output current onpins DB7 to DB0

VOL = 0.4 V; VDD = 5 V 1.6 4 − mA

IOH(DB) HIGH-level output current onpins DB7 to DB0

VOH = 4 V; VDD = 5 V −1 −8 − mA

Ipu pull-up current onpins DB7 to DB0

VI = VSS 0.04 0.12 1 µA

IL leakage current on pins OSC, E,RS, R/W, DB7 to DB0 and SA0

VI = VDD or VSS −1 − +1 µA

1998 May 11 34



Notes

1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive.

2. Tamb = 25 °C; fosc = 200 kHz.

3. Resets all logic when VDD < VPOR; 3 oscillator clock cycles required.

4. Tested on sample basis.

5. Resistance of output terminals (R1 to R18 and C1 to C60) with a load current of 20 µA; outputs measured one at atime.

6. LCD outputs open-circuit.

I2C-bus

SDA AND SCL

VIL LOW-level input voltage 0 − 0.3VDD V

VIH HIGH-level input voltage 0.7VDD − 5.5 V

IL input leakage current VI = VDD or VSS −1 − +1 µA

Ci input capacitance note 4 − − 10 pF

IOL LOW-level output currentpin SDA

VOL = 0.4 V; VDD = 5 V 3 − − mA

LCD outputs

Ro(ROW) row output resistance onpins R1 to R18

note 5 − 10 30 kΩ

Ro(COL) column output resistance onpins C1 to C60

note 5 − 15 40 kΩ

Vbias(tol) bias tolerance onpins R1 to R18 and C1 to C60

note 6 − 20 130 mV


1998 May 11 35



13 AC CHARACTERISTICSVDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.2 − 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.

Note

1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced toVIL and VIH with an input voltage swing of VSS to VDD.


ffr(LCD) LCD frame frequency (internal clock) VDD = 5.0 V 45 81 147 Hz

fosc oscillator frequency (not available at any pin) 140 250 450 kHz

fosc(ext) external clock frequency 140 − 450 kHz

tOSCST oscillator start-up time after PD going fromlogic 1 to logic 0

− 200 300 µs

Bus timing characteristics: parallel interface; note 1

WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2103); see Fig.23

Ten(cy) enable cycle time 500 − − ns

tW(en) enable pulse width 220 − − ns

tsu(A) address set-up time 50 − − ns

th(A) address hold time 25 − − ns

tsu(D) data set-up time 60 − − ns

th(D) data hold time 25 − − ns

READ OPERATION (READING DATA FROM PCF2103 TO MICROCONTROLLER); see Fig.24

Ten(cy) enable cycle time 500 − − ns

tW(en) enable pulse width 220 − − ns

tsu(A) address set-up time 50 − − ns

th(A) address hold time 25 − − ns

td(D) data delay time − − 150 ns

th(D) data hold time 20 − 100 ns

Timing characteristics: I 2C-bus interface; note 1

fSCL SCL clock frequency − − 400 kHz

tLOW SCL clock LOW period 1.3 − − µs

tHIGH SCL clock HIGH period 0.6 − − µs

tSU;DAT data set-up time 100 − − ns

tHD;DAT data hold time 0 − − ns

tr SCL and SDA rise time − − 300 ns

tf SCL and SDA fall time − − 300 ns

CB capacitive bus line load − − 400 pF

tSU;STA set-up time for a repeated START condition 0.6 − − µs

tHD;STA START condition hold time 0.6 − − µs

tSU;STO set-up time for STOP condition 0.6 − − µs

tSW tolerable spike width on bus − − 50 ns

1998 May 11 36



14 TIMING CHARACTERISTICS

Fig.23 Parallel bus write operation sequence; writing data from microcontroller to PCF2103.

handbook, full pagewidthRS

E

DB0 to DB7

V

V

V

VV

V

V

VV

V

V

V

V

T

IHIL

IHIL

IH

IL

IL IL

IH

IL

IHILVIL

VIH

IL

en(cy)

h(D)t

DATAVALID

MGL252

R/W

tsu(A)

tsu(D)

th(A)

th(A)tW(en)

Fig.24 Parallel bus read operation sequence; reading data from PCF2103 to microcontroller.

handbook, full pagewidthRS

R/W

E

DB0 to DB7

V

V

VV

V

V

VV

VV

IH

IL

IHIL

IHIL

IHIL

VOL

VOH

IL

Ten(cy)

h(D)t

tsu(A) th(A)

th(A)tW(en)

IH

VOL

VOH

td(D)

VIH

MGL253

DATAVALID

1998 May 11 37



15 APPLICATION INFORMATION

Fig.25 Direct connection to 8-bit microcontroller; 8-bit bus.


PCF2103

MGL254

P80CL51

2 × 12 CHARACTERLCD DISPLAY

PLUS 120 ICONS16

8

C1 to C60 60

2RSP20

P21

EP22

DB7 to DB0P17 to P10

R17, R18

R1 to R16

R/W

Fig.26 Direct connection to 8-bit microcontroller; 4-bit bus.


PCF2103

MGL255

P80CL51

2 × 12 CHARACTERLCD DISPLAY

PLUS 120 ICONS16

4

C1 to C60 60

2RSP10

P11

EP12

DB7 to DB4P17 to P14

R17, R18

R1 to R16

R/W

Fig.27 Application example using parallel interface.


MGL256

PCF21032 × 12 CHARACTER

LCD DISPLAYPLUS 120 ICONS16

8

C1 to C60 60

2OSC

RSDB7 to DB0 E

100nF

100nF

R17, R18

R1 to R16

VDD

VSS

VDD

VLCD

VSS

R/W

VLCD

1998 May 11 38



Fig.28 Application using I2C-bus interface.

handbook, full pagewidth VDDVDD

SCL SDAMASTER TRANSMITTERPCF84C81A; P80CL410



C1 to C60 60

2OSC

SCL SDA

DB3/SAO

100nF

100nF

R17, R18

R1 to R16

VDD

VDD

VLCD

VSS

VDD

VLCD

VSS



C1 to C60 60

2OSC

SCL SDA

DB3/SAO

100nF

100nF

R17, R18

R1 to R16

VSS

VDD

VSS

VDD

VLCD

VSS

MGL257

VLCD

1998 May 11 39




The program must set functions prior to 4-bit operation;Table 11 shows an example. When power is turned on,8-bit operation is automatically selected and the PCF2103attempts to perform the first write as an 8-bit operation.Since nothing is connected to DB0 to DB3, a rewrite isthen required. However, since one operation is completedin two accesses of 4-bit operation, a rewrite is required toset the functions (see Table 11 step 3). Thus, DB4 to DB7of the ‘function set’ are written twice.


Table 12 shows an example of a 1-line display in 8-bitoperation. The PCF2103 functions must be set by the‘function set’ instruction prior to display. Since the DDRAMcan store data for 80 characters, the RAM can be used foradvertising displays when combined with display shiftoperation.

Since the display shift operation changes display positiononly and DDRAM contents remain unchanged, displaydata entered first can be displayed when the ‘return home’operation is performed.

15.3 8-bit operation, 2-line display

For a 2-line display, the cursor automatically moves fromthe first to the second line after the 40th digit of the first linehas been written. Thus, if there are only 8 characters in thefirst line, the DDRAM address must be set after the eighthcharacter is completed (see Table 6). It should be notedthat both lines of the display are always shifted together;data does not shift from one line to the other.

15.4 I2C-bus operation, 1-line display

A control byte is required with most commands(see Table 15).

Table 11 4-bit operation, 1-line display example; using internal reset

STEP INSTRUCTION DISPLAY OPERATION

1 power supply on (PCF2103 is initialized bythe internal reset circuit)

initialized; no display appears

2 function set

RS R/W DB7 DB6 DB5 DB4 sets to 4-bit operation; in this instance operationis handled as 8-bit by initialization and only thisinstruction completes with one write

0 0 0 0 1 0

3 function set

0 0 0 0 1 0 sets to 4-bit operation, selects 1-line display andVLCD = V0; 4-bit operation starts from this pointand resetting is needed

0 0 0 0 0 0

4 display on/off control

0 0 0 0 0 0 _ turns on display and cursor; entire display isblank after initialization0 0 1 1 1 0

5 entry mode set

0 0 0 0 0 0 _ sets mode to increment the address by 1 and toshift the cursor to the right at the time of write tothe DD/CGRAM; display is not shifted

0 0 0 1 1 0

6 ‘write data’ to CGRAM/DDRAM

1 0 0 1 0 1 P_ writes ‘P’; the DDRAM has already been selectedby initialization at power-on; the cursor isincremented by 1 and shifted to the right

1 0 0 0 0 0

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Table 12 8-bit operation, 1-line display example; using internal reset (character set ‘A’)


1 power supply on (PCF2103 is initialized by the internal resetfunction)


2 function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 sets to 8-bit operation, selects 1-line display

0 0 0 0 1 1 0 0 0 0

3 display mode on/off control

0 0 0 0 0 0 1 1 1 0 _ turns on display and cursor; entire display is blank afterinitialization

4 entry mode set

0 0 0 0 0 0 0 1 1 0 _ sets mode to increment the address by 1 and to shift thecursor to the right at the time of the write to theDD/CGRAM; display is not shifted


1 0 0 1 0 1 0 0 0 0 P_ writes ‘P’; the DDRAM has already been selected byinitialization at power-on; the cursor is incremented by 1and shifted to the right


1 0 0 1 0 0 1 0 0 0 PH_ writes ‘H’

7 to 11 |

|


1 0 0 1 0 1 0 0 1 1 PHILIPS_ writes ‘S’

13 entry mode set

0 0 0 0 0 0 0 1 1 1 PHILIPS_ sets mode for display shift at the time of write


1 0 0 0 1 0 0 0 0 0 HILIPS _ writes space


1 0 0 1 0 0 1 1 0 1 ILIPS M_ writes ‘M’

16 |

|

|

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1 0 0 1 0 0 1 1 1 1 MICROKO writes ‘O’

18 cursor/display shift

0 0 0 0 0 1 0 0 0 0 MICROKO shifts only the cursor position to the left


0 0 0 0 0 1 0 0 0 0 MICROKO shifts only the cursor position to the left


1 0 0 1 0 0 0 0 1 1 ICROKO writes ‘C’ correction; the display moves to the left


0 0 0 0 0 1 1 1 0 0 MICROKO shifts the display and cursor to the right


0 0 0 0 0 1 0 1 0 0 MICROCO_ shifts only the cursor to the right


1 0 0 1 0 0 1 1 0 1 ICROCOM_ writes ‘M’

24 |

|

|

25 return home

0 0 0 0 0 0 0 0 1 0 PHILIPS M returns both display and cursor to the original position(address 0)


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Table 13 8-bit operation, 1-line display and icon example; using internal reset (character set ‘A’)




2 function set

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 sets to 8-bit operation, selects 1-line display

0 0 0 0 1 1 0 0 0 0

3 display mode on/off control

0 0 0 0 0 0 1 1 1 0 _ turns on display and cursor; entire display is blank afterinitialization

4 entry mode set

0 0 0 0 0 0 0 1 1 0 _ sets mode to increment the address by 1 and to shift thecursor to the right at the time of the write to theDD/CGRAM; display is not shifted

5 set CGRAM address

0 0 0 1 0 0 0 0 0 0 _ sets the CGRAM address to position of character 0; theCGRAM is selected


1 0 0 0 0 0 1 0 1 0 _ writes data to CGRAM for icon even phase; icons appear

7 |

|

8 set CGRAM address

0 0 0 1 1 1 0 0 0 0 _ sets the CGRAM address to position of character 4; theCGRAM is selected


1 0 0 0 0 0 1 0 1 0 _ writes data to CGRAM for icon odd phase

10 |

|

11 function set

0 0 0 0 1 1 0 0 0 1 _ sets H = 1

12 icon control

0 0 0 0 0 0 1 0 1 0 _ icons blink

13 function set

0 0 0 0 1 1 0 0 0 1 _ sets H = 0

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14 set DDRAM address

0 0 1 0 0 0 0 0 0 0 sets the DDRAM address to the first position; DDRAM isselected


1 0 0 1 0 1 0 0 0 0 P_ writes ‘P’; the cursor is incremented by 1 and shifted tothe right


1 0 0 1 0 0 1 0 0 0 PH_ writes ‘H’

17 to 20 |

|

21 return home

0 0 0 0 0 0 0 0 1 0 PHILIPS returns both display and cursor to the original position(address 0)


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Table 14 8-bit operation, 2-line display example; using internal reset




2 function set sets to 8-bit operation; selects 2-line display and voltagegenerator off

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 1 1 0 0 0

3 display on/off control turns on display and cursor; entire display is blank afterinitialization_

0 0 0 0 0 0 1 1 1 0

4 entry mode set sets mode to increment the address by 1 and to shift thecursor to the right at the time of write to the CG/DDRAM;display is not shifted

_

0 0 0 0 0 0 0 1 1 0

5 ‘write data’ to CGRAM/DDRAM writes ‘P’; the DDRAM has already been selected byinitialization at power-on; the cursor is incremented by 1and shifted to the right

P_

1 0 0 1 0 1 0 0 0 0

6 to 10 |

|

|

11 ‘write data’ to CGRAM/DDRAM writes ‘S’

PHILIPS_

1 0 0 1 0 1 0 0 1 1

12 set DDRAM address sets DDRAM address to position the cursor at the head ofthe 2nd linePHILIPS

0 0 1 1 0 0 0 0 0 0 _

13 ‘write data’ to CGRAM/ DDRAM writes ‘M’

PHILIPS

1 0 0 1 0 0 1 1 0 1 M_

14 to 19 |

|

|

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20 ‘write data’ to CGRAM/DDRAM writes ‘O’

PHILIPS

1 0 0 1 0 0 1 1 1 1 MICROCO_

21 ‘write data’ to CGRAM/DDRAM sets mode for display shift at the time of write

PHILIPS

0 0 0 0 0 0 0 1 1 1 MICROCO_

22 ‘write data’ to CGRAM/DDRAM writes ‘M’; display is shifted to the left; the first and secondlines shift togetherHILIPS

1 0 0 1 0 0 1 1 0 1 ICROCOM_

23 |

|

|

24 return home returns both display and cursor to the original position(address 0)PHILIPS

0 0 0 0 0 0 0 0 1 0 MICROCOM


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Table 15 Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1)


1 I2C-bus start initialized; no display appears

2 slave address for write

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack during the acknowledge cycle SDA will be pulled-down by thePCF21030 1 1 1 0 1 0 0 1

3 send a control byte for ‘function set’

Co RS 0 0 0 0 0 0 Ack control byte sets RS for following data bytes

0 0 0 0 0 0 0 0 1

4 function set

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack selects 1-line display; SCL pulse during acknowledge cyclestarts execution of instruction0 0 1 X 0 0 0 0 1

5 display on/off control _

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack turns on display and cursor; entire display shows character 20H(blank in ASCII-like character sets)0 0 0 0 1 1 1 0 1

6 entry mode set _

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack sets mode to increment the address by 1 and to shift the cursorto the right at the time of write to the DDRAM or CGRAM; displayis not shifted

0 0 0 0 0 1 1 0 1

7 I2C-bus start _

for writing data to DDRAM, RS must be set to 1; therefore acontrol byte is needed

8 slave address for write _

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack

0 1 1 1 0 1 0 0 1

9 send a control byte for ‘write data’ _

Co RS 0 0 0 0 0 0 Ack

0 1 0 0 0 0 0 0 1

10 ‘write data’ to DDRAM

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack writes ‘P’; the DDRAM has been selected at power-up; thecursor is incremented by 1 and shifted to the right0 1 0 1 0 0 0 0 1 P_

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DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack writes ‘H’

0 1 0 0 1 0 0 0 1 PH_

12 to 15 |

|

|

|


DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack writes ‘S’

0 1 0 1 0 0 1 1 1 PHILIPS_

17 (optional I2C-bus stop) I2C-bus start + slave addressfor write (as step 8) PHILIPS_

18 control byte

Co RS 0 0 0 0 0 0 Ack

1 0 0 0 0 0 0 0 1 PHILIPS_

19 return home

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack sets DDRAM address 0 in address counter (also returns shifteddisplay to original position; DDRAM contents unchanged); thisinstruction does not update the Data Register (DR)

0 0 0 0 0 0 1 0 1 PHILIPS

20 I2C-bus start PHILIPS

21 slave address for read

SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack during the acknowledge cycle the content of the DR is loadedinto the internal I2C-bus interface to be shifted out; in theprevious instruction neither a ‘set address’ nor a ‘read data’ hasbeen performed; therefore the content of the DR was unknown;R/W has to be set to logic 1 while still in I2C-bus write mode

0 1 1 1 0 1 0 1 1 PHILIPS

22 control byte for read

Co RS 0 0 0 0 0 0 Ack DDRAM content will be read from following instructions

0 1 1 0 0 0 0 0 1 PHILIPS


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Notes


2. SDA is left at high-impedance by the microcontroller during the read acknowledge.

23 ‘read data’: 8 × SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 8 × SCL; content loaded into interface during previousacknowledge cycle is shifted out over SDA; MSB is DB7; duringmaster acknowledge content of DDRAM address 01 is loadedinto the I2C-bus interface

X X X X X X X X 0 PHILIPS

24 ‘read data’: 8 × SCL + master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 8 × SCL; code of letter ‘H’ is read first; during masteracknowledge code of ‘I’ is loaded into the I2C-bus interface0 1 0 0 1 0 0 0 0 PHILIPS

25 ‘read data’: 8 × SCL + no master acknowledge; note 2

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack no master acknowledge; after the content of the I2C-businterface register is shifted out no internal action is performed;no new data is loaded to the interface register, Data Register(DR) is not updated, Address Counter (AC) is not incrementedand cursor is not shifted

0 1 0 0 1 0 0 1 1 PHILIPS

26 I2C-bus stop PHILIPS


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Table 16 Initialization by instruction, 8-bit interface (note 1)

Note


STEP DESCRIPTION

power-on or unknown state

|

wait 2 ms after VDD rises above VPOR

|

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 BF cannot be checked before this instruction

0 0 0 0 1 1 X X X X function set (interface is 8 bits long)

|

wait 2 ms

|



|

wait more than 40 µs

|



|

|

BF can be checked after the following instructions; when BF is not checked,the waiting time between instructions is the specified instruction time(see Table 4)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 function set (interface is 8 bits long); specify the number of display lines

0 0 0 0 1 1 0 M 0 H

0 0 0 0 0 0 1 0 0 0 display off

0 0 0 0 0 0 0 0 0 1 clear display

0 0 0 0 0 0 0 1 I/D S entry mode set

|

Initialization ends

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Table 17 Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation

STEP DESCRIPTION

Power-on or unknown state

|

Wait 2 ms after VDD rises above VPOR

|

RS R/W DB7 DB6 DB5 DB4 BF cannot be checked before this instruction

0 0 0 0 1 1 function set (interface is 8 bits long)

|

Wait 2 ms

|



|

Wait 40 µs

|



| BF can be checked after the following instructions; when BF is not checked, the waiting timebetween instructions is the specified instruction time (see Table 4)

RS R/W DB7 DB6 DB5 DB4 function set (set interface to 4 bits long)

0 0 0 0 1 0 interface is 8 bits long


0 0 0 M 0 H specify number of display lines

0 0 0 0 0 0

0 0 1 0 0 0 display off

0 0 0 0 0 0 clear display

0 0 0 0 0 1

0 0 0 0 0 0 entry mode set

0 0 0 1 I/D S

|

Initialization ends

1998 May 11 51



16 BONDING PAD LOCATIONS

Fig.29 Bonding pad locations.


MGL258

1105 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

VD

D

OS

C

PD T1

VS

S

R9

VLC

D

R10

R11

R12

R13

R14

R15

R16

R18

C60

C59

C58

C57

C56

C55

C54

C53

C20

C21

C22

C23

C24

C25

C26

C27

C12

C13

C14

C15

C16

C17

C18

C19

C3

C4

C5

C6

C7

C8

C9

C10

C11

26

25

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

C52

C51

C50

C49

C48

C47

C46

C45

C44

C43

C42

C41

C40

C39

C38

C37

C36

C35

C34

C33

C32

C31

C30

C29

C28

53 5254555657585960616263646566676869707172737475767778

80

79

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

C2

C1

R8

R7

R6

R5

R4

R3

R2

R1

R17

SCL

SDA

E

RS

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

C52(dummy)

C28(dummy)

C3(

dum

my)

C27

(dum

my)

RO

M x

xx

PC

F21

03-2

x

y

00

≈ 2.99 mm

≈ 3.18mm

R/W

C2(dummy)

DB0(dummy)

VD

D(d

umm

y)

C53

(dum

my)

1998 May 11 52



Table 18 Bonding pad locations (dimensions in µm).All x/y coordinates are referenced to centre ofchip (see Fig.29)

SYMBOL PAD X Y

VDD (dummy) 105 −1228 −1414

VDD 1 −1048 −1414

OSC 2 −958 −1414

PD 3 −868 −1414

T1 4 −778 −1414

VSS 5 −688 −1414

VLCD 6 −516 −1414

R9 7 −349 −1414

R10 8 −259 −1414

R11 9 −169 −1414

R12 10 −79 −1414

R13 11 11 −1414

R14 12 101 −1414

R15 13 191 −1414

R16 14 281 −1414

R18 15 371 −1414

C60 16 461 −1414

C59 17 551 −1414

C58 18 641 −1414

C57 19 731 −1414

C56 20 821 −1414

C55 21 911 −1414

C54 22 1001 −1414

C53 23 1091 −1414

C53 (dummy) 24 1181 −1414

C52 (dummy) 25 1344 −1254

C52 26 1344 −1164

C51 27 1344 −1074

C50 28 1344 −948

C49 29 1344 −812

C48 30 1344 −722

C47 31 1344 −632

C46 32 1344 −542

C45 33 1344 −452

C44 34 1344 −362

C43 35 1344 −272

C42 36 1344 −182

C41 37 1344 −92

C40 38 1344 −2

C39 39 1344 88

C38 40 1344 178

C37 41 1344 268

C36 42 1344 358

C35 43 1344 448

C34 44 1344 538

C33 45 1344 628

C32 46 1344 718

C31 47 1344 808

C30 48 1344 898

C29 49 1344 1070

C28 50 1344 1160

C28 (dummy) 51 1344 1250

C27 (dummy) 52 1262 1414

C27 53 1172 1414

C26 54 1082 1414

C25 55 992 1414

C24 56 902 1414

C23 57 805 1414

C22 58 715 1414

C21 59 625 1414

C20 60 535 1414

C19 61 445 1414

C18 62 355 1414

C17 63 265 1414

C16 64 175 1414

C15 65 85 1414

C14 66 −5 1414

C13 67 −95 1414

C12 68 −185 1414

C11 69 −275 1414

C10 70 −446 1414

C9 71 −536 1414

C8 72 −626 1414

C7 73 −716 1414

C6 74 −806 1414

C5 75 −896 1414

SYMBOL PAD X Y

1998 May 11 53



C4 76 −986 1414

C3 77 −1076 1414

C3 (dummy) 78 −1166 1414

C2 (dummy) 79 −1344 1303

C2 80 −1344 1213

C1 81 −1344 1123

R8 82 −1344 1033

R7 83 −1344 943

R6 84 −1344 853

R5 85 −1344 763

R4 86 −1344 673

R3 87 −1344 583

R2 88 −1344 493

R1 89 −1344 403

R17 90 −1344 313

SCL 91 −1344 131

SDA 92 −1344 −9

E 93 −1344 −195

RS 94 −1344 −289

RW 95 −1344 −382

DB7 96 −1344 −476

DB6 97 −1344 −572

DB5 98 −1344 −668

DB4 99 −1344 −765

DB3 100 −1344 −861

DB2 101 −1344 −957

DB1 102 −1344 −1054

DB0 103 −1344 −1150

DB0 (dummy) 104 −1344 −1240

Rec. Pat. C1 1335 −1405

Rec. Pat. C2 −1335 1405

Rec. Pat. F −1340 −1397

SYMBOL PAD X Y Table 19 Bump specifications

PARAMETER SPECIFICATION UNIT

Bump variant N −Type galvanic; pure

aurum−

Bump width 60 ±6 µm

Bump length 90 ±6 µm

Bump height 17.5 ±5 µm

Height difference in onedie

<2 µm

Convex deformation <5 µm

Pad size; aluminium 80 × 100 µm

Passivation opening CBB 46 × 76 µm

Wafer thickness 380 ±25 µm

Minimum pitch 90 µm

1998 May 11 54



17 DEFINITIONS

18 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of theseproducts can reasonably be expected to result in personal injury. Philips customers using or selling these products foruse in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from suchimproper use or sale.

19 PURCHASE OF PHILIPS I2C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one ormore of the limiting values may cause permanent damage to the device. These are stress ratings only and operationof the device at these or at any other conditions above those given in the Characteristics sections of the specificationis not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use thecomponents in the I2C system provided the system conforms to the I2C specification defined byPhilips. This specification can be ordered using the code 9398 393 40011.

1998 May 11 55



NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1998 SCA60

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changedwithout notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any licenseunder patent- or other industrial or intellectual property rights.

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,Tel. +31 40 27 82785, Fax. +31 40 27 88399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,Tel. +64 9 849 4160, Fax. +64 9 849 7811

Norway: Box 1, Manglerud 0612, OSLO,Tel. +47 22 74 8000, Fax. +47 22 74 8341

Pakistan: see Singapore

Philippines: Philips Semiconductors Philippines Inc.,106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,Tel. +48 22 612 2831, Fax. +48 22 612 2327

Portugal: see Spain

Romania: see Italy

Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,Tel. +7 095 755 6918, Fax. +7 095 755 6919

Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,Tel. +65 350 2538, Fax. +65 251 6500

Slovakia: see Austria

Slovenia: see Italy

South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,Tel. +27 11 470 5911, Fax. +27 11 470 5494

South America: Al. Vicente Pinzon, 173, 6th floor,04547-130 SÃO PAULO, SP, Brazil,Tel. +55 11 821 2333, Fax. +55 11 821 2382

Spain: Balmes 22, 08007 BARCELONA,Tel. +34 93 301 6312, Fax. +34 93 301 4107

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,Tel. +46 8 5985 2000, Fax. +46 8 5985 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,Tel. +41 1 488 2741 Fax. +41 1 488 3263

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,Tel. +66 2 745 4090, Fax. +66 2 398 0793

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,Tel. +90 212 279 2770, Fax. +90 212 282 6707

Ukraine : PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,Tel. +1 800 234 7381

Uruguay: see South America

Vietnam: see Singapore

Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,Tel. +381 11 625 344, Fax.+381 11 635 777

For all other countries apply to: Philips Semiconductors,International Marketing & Sales Communications, Building BE-p, P.O. Box 218,5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825

Argentina: see South America

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,Tel. +61 2 9805 4455, Fax. +61 2 9805 4466

Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010,Fax. +43 160 101 1210

Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773

Belgium: see The Netherlands

Brazil: see South America

Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,51 James Bourchier Blvd., 1407 SOFIA,Tel. +359 2 689 211, Fax. +359 2 689 102

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,Tel. +1 800 234 7381

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,72 Tat Chee Avenue, Kowloon Tong, HONG KONG,Tel. +852 2319 7888, Fax. +852 2319 7700

Colombia: see South America

Czech Republic: see Austria

Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,Tel. +45 32 88 2636, Fax. +45 31 57 0044

Finland: Sinikalliontie 3, FIN-02630 ESPOO,Tel. +358 9 615800, Fax. +358 9 61580920

France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427

Germany: Hammerbrookstraße 69, D-20097 HAMBURG,Tel. +49 40 23 53 60, Fax. +49 40 23 536 300

Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,Tel. +30 1 4894 339/239, Fax. +30 1 4814 240

Hungary: see Austria

India: Philips INDIA Ltd, Band Box Building, 2nd floor,254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,Tel. +91 22 493 8541, Fax. +91 22 493 0966

Indonesia: PT Philips Development Corporation, Semiconductors Division,Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080

Ireland: Newstead, Clonskeagh, DUBLIN 14,Tel. +353 1 7640 000, Fax. +353 1 7640 200

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,Tel. +82 2 709 1412, Fax. +82 2 709 1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,Tel. +60 3 750 5214, Fax. +60 3 757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,Tel. +9-5 800 234 7381

Printed in The Netherlands 415106/1200/01/pp56 Date of release: 1998 May 11 Document order number: 9397 750 02649

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www.datasheetcatalog.com

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