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LFPAK 5x6
TAB
23
4
1
G4S123DTAB_LFPAK
D(TAB)
G(4)
S(1, 2, 3)
FeaturesOrder code V DS RDS(on) max ID
STK224N4F7AG 40 V 1.5 mΩ 100 A
• AEC-Q101 qualified • Among the lowest RDS(on) on the market• Excellent FoM (figure of merit)• Low Crss/Ciss ratio for EMI immunity• High avalanche ruggedness
Applications• Switching applications
DescriptionThis N-channel Power MOSFET utilizes STripFET™ F7 technology with anenhanced trench gate structure that results in very low on-state resistance, while alsoreducing internal capacitance and gate charge for faster and more efficient switching.
Product status
STK224N4F7AG
Product summary
Order code STK224N4F7AG
Marking 224N4F7
Package LFPAK 5x6
Packing Tape and reel
Automotive-grade N-channel 40 V, 1.2 mΩ typ., 100 A STripFET™ F7 Power MOSFET in a LFPAK 5x6 package
STK224N4F7AG
Datasheet
DS12550 - Rev 2 - January 2019For further information contact your local STMicroelectronics sales office.
www.st.com
1 Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
VDS Drain-source voltage 40 V
VGS Gate-source voltage ±20 V
ID (1) Drain current (continuous) at TC = 25 °C 100 A
ID (1) Drain current (continuous) at TC = 100 °C 100 A
IDM (2) Drain current (pulsed) 400 A
PTOT Total dissipation at TC = 25 °C 150 W
IAVAvalanche current, repetitive or not repetitive (pulse width limited by maximum junctiontemperature) 56 A
EASSingle pulse avalanche energy(starting TJ = 25 °C, ID = IAV, VDD = 25 V) 470 mJ
Tj Operating junction temperature range-55 to 175 °C
Tstg Storage temperature range
1. Drain current is limited by package, the current capability of the silicon is 224 A at 25 °C.2. Pulse width limited by safe operating area
Table 2. Thermal data
Symbol Parameter Value Unit
Rthj-pcb (1) Thermal resistance junction-pcb. 31.3 °C/W
Rthj-case Thermal resistance junction-case. 1.0 °C/W
1. When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s.
STK224N4F7AGElectrical ratings
DS12550 - Rev 2 page 2/13
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 3. On /off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSSDrain-source breakdownvoltage VGS = 0 V, ID= 1 mA 40 V
IDSSZero gate voltagedraincurrent VGS = 0 V, VDS= 40 V 1 µA
IGSS Gate-body leakage current VGS = 20 V, VDS = 0 V 100 nA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 μA 2 4 V
RDS(on)Static drain-source on-resistance VGS = 10 V, ID = 50 A 1.2 1.5 mΩ
Table 4. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitanceVDS = 25 V, f = 1 MHz,
VGS= 0 V
- 4060 - pF
Coss Output capacitance - 1100 - pF
Crss Reverse transfer capacitance - 300 - pF
Qg Total gate chargeVDD = 20 V, ID = 100 A,VGS = 0 to 10 V(see Figure 13. Testcircuit for gate charge behavior)
- 50 - nC
Qgs Gate-source charge - 23 - nC
Qgd Gate-drain charge - 9.8 - nC
Table 5. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD = 20 V, ID = 50 A,
RG = 4.7 Ω, VGS = 10 V(see Figure 12. Test circuit forresistive load switching timesandFigure 17. Switching time waveform)
- 25 - ns
tr Rise time - 20 - ns
td(off) Turn-off delay time - 48 - ns
tf Fall time - 31 - ns
Table 6. Source-drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSD (1) Forward on voltage ISD = 100 A, VGS = 0 V - 1.1 V
trr Reverse recovery time ID = 100 A, di/dt = 100 A/µsVDD = 20 V (see Figure 14. Testcircuit for inductive load switching anddiode recovery times)
- 41 ns
Qrr Reverse recovery charge - 32 nC
IRRM Reverse recovery current - 1.6 A
1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
STK224N4F7AGElectrical characteristics
DS12550 - Rev 2 page 3/13
2.1 Electrical characteristics curves
Figure 1. Safe operating area
ADG191220181216SOA
10 2
10 1
10 0
10 -1
10 -1 10 0 10 1
ID (A)
VDS (V)
Operation in this area is
limited by m
ax. RDS(on)
Tj = 175 °C Tc = 25 °C single pulse
tp = 10µs
tp = 100µs
tp = 1ms
tp = 10ms
Figure 2. Thermal impedance
ADG191220181217ZTH
10 -1
10 -2
10 -5 10 -4 10 -3 10 -2 10 -1
K
tp (s)
δ = 0.5
0.2
0.1
0.05
0.020.01
Single pulse
Figure 3. Output characterisics
ADG191220181217OCH
125
100
75
50
25
00 1 2 3 4 5
ID (A)
VDS (V)
VGS = 6 V
VGS = 5 V
VGS = 9, 10V
VGS = 7, 8 V
Figure 4. Transfer characteristics
ADG191220181218TCH
60
50
40
30
20
10
00 2 4 6 8
ID (A)
VGS (V)
VDS = 5 V
Figure 5. Static drain-source on resistance
ADG191220181218RID
1.10
10 20 40 60 80
RDS(on) [mΩ]
ID [A]
1.30
VGS = 10 V
Figure 6. Gate charge vs gate-source voltage
ADG191220181219QVG
12
10
8
6
4
2
00 10 20 30 40 50
VGS (V)
Qg (nC)
VDS = 20 V ID = 100 A
STK224N4F7AGElectrical characteristics curves
DS12550 - Rev 2 page 4/13
Figure 7. Capacitance variations
ADG191220181219CVR
10 4
10 3
10 2
10 1 0 10 20 30 40
C (pF)
VDS (V)
CISS
COSS
CRSS
Figure 8. Normalized gate threshold voltage vstemperature
ADG191220181220VTH
1.00
0.80
0.60
0.40
0.20-75 -25 25 75 125 175
VGS(th) (norm.)
Tj (°C)
ID = 250 µA
1.20
Figure 9. Normalized on resistance vs temperature
ADG191220181220RON
1.8
1.6
1.4
1.2
1
0.8
0.6-75 -25 25 75 125 175
RDS(on) (norm.)
Tj (°C)
VGS = 10 V ID = 50 A
Figure 10. Source-drain diode forward characteristic
ADG191220181221SDF
1.0
0.9
0.8
0.7
0.6
0.5
0.410 30 50 70 90
VSD (V)
ISD (A)
Tj = 25°C
Tj = 175°C
Tj = -55 °C
Figure 11. Normalized V(BR)DSS vs temperature
ADG191220181222BDV
1.06
1.04
1.02
1.00
0.98
0.96
0.94-75 -25 25 75 125 175
V(BR)DSS (norm.)
Tj (°C)
ID = 1 mA
STK224N4F7AGElectrical characteristics curves
DS12550 - Rev 2 page 5/13
3 Test circuits
Figure 12. Test circuit for resistive load switching times
AM01468v1
VD
RG
RL
D.U.T.
2200μF VDD
3.3μF+
pulse width
VGS
Figure 13. Test circuit for gate charge behavior
AM01469v1
47 kΩ1 kΩ
47 kΩ
2.7 kΩ
1 kΩ
12 V
IG= CONST100 Ω
100 nF
D.U.T.
+pulse width
VGS
2200μF
VG
VDD
Figure 14. Test circuit for inductive load switching anddiode recovery times
AM01470v1
AD
D.U.T.S
B
G
25 Ω
A A
B B
RG
GD
S
100 µH
µF3.3 1000
µF VDD
D.U.T.
+
_
+
fastdiode
Figure 15. Unclamped inductive load test circuit
AM01471v1
VD
ID
D.U.T.
L
VDD+
pulse width
Vi
3.3µF
2200µF
Figure 16. Unclamped inductive waveform
AM01472v1
V(BR)DSS
VDDVDD
VD
IDM
ID
Figure 17. Switching time waveform
AM01473v1
0
VGS 90%
VDS
90%
10%
90%
10%
10%
ton
td(on) tr
0
toff
td(off) tf
STK224N4F7AGTest circuits
DS12550 - Rev 2 page 6/13
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitionsand product status are available at: www.st.com. ECOPACK® is an ST trademark.
STK224N4F7AGPackage information
DS12550 - Rev 2 page 7/13
4.1 LFPAK 5x6 package information
Figure 18. LFPAK 5x6 package outline
00299525_A
STK224N4F7AGLFPAK 5x6 package information
DS12550 - Rev 2 page 8/13
Table 7. LFPAK 5x6 package mechanical data
Dim.mm
Min. Typ. Max.
A 1.01 1.20
A1 0.00 0.15
A2 0.95 1.10
A3 0.25
A4 0.50 0.55 0.65
b 0.35 0.50
b2 3.62 4.41
b3 2.0 2.20
b4 0.70 0.90
b5 0.7
c 0.19 0.20(1) 0.25
c2 0.24 0.30
D 3.80 4.10
D1 3.80 4.00 4.20
E 4.8 5.0
E1 3.1 3.3
e 1.27
H 5.8 6.2
L 0.40 0.85
L1 0.80 1.30
L2 0.80 1.3
w 0.25
y 0.10
ϴ 0° 8°
1. Dimension without plating
STK224N4F7AGLFPAK 5x6 package information
DS12550 - Rev 2 page 9/13
Figure 19. LFPAK 5x6 recommended footprint
00299525_FP_A
STK224N4F7AGLFPAK 5x6 package information
DS12550 - Rev 2 page 10/13
Revision history
Table 8. Document revision history
Date Revision Changes
09-Apr-2018 1 First release.
14-Jan-2019 2
Updated title in cover page, Section 1 Electrical ratings and Section 2 Electrical characteristics.
Added Section 2.1 Electrical characteristics curves
Minor text changes.
STK224N4F7AG
DS12550 - Rev 2 page 11/13
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.1 LFPAK 5x6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
STK224N4F7AGContents
DS12550 - Rev 2 page 12/13
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to STproducts and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. STproducts are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design ofPurchasers’ products.
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Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2019 STMicroelectronics – All rights reserved
STK224N4F7AG
DS12550 - Rev 2 page 13/13