David M. Harris and Sarah L. Harris - Harvey Mudd Collegepages.hmc.edu/harris/class/e85/Chapter_7_Lecture_Slides.pdf · series of shorter steps ... 31:25 24:20 19:15 14:12 11:7 6:0

Chapter 6 <1> Digital Design and Computer Architecture: RISC-V Edition Harris & Harris © 2020 ElsevierChapter 7 <1>

Digital Design and Computer Architecture, RISC-V Edition

Chapter 6

David M. Harris and Sarah L. Harris

Digital Design and Computer Architecture: RISC-V Edition Harris & Harris © 2020 ElsevierChapter 7 <2>

Chapter 7 :: Microarchitecture

• Introduction• Performance Analysis• Single-Cycle Processor• Multicycle Processor• Pipelined Processor• Advanced Microarchitecture


• Microarchitecture: how to implement an architecture in hardware

• Processor:– Datapath: functional blocks– Control: control signals

Introduction


• Multiple implementations for a single architecture:– Single-cycle: Each instruction executes in a

single cycle– Multicycle: Each instruction is broken up into

series of shorter steps– Pipelined: Each instruction broken up into series

of steps & multiple instructions execute at once

Microarchitecture


• Program execution timeExecution Time = (#instructions)(cycles/instruction)(seconds/cycle)

• Definitions:– CPI: Cycles/instruction– clock period: seconds/cycle– IPC: instructions/cycle = IPC

• Challenge is to satisfy constraints of:– Cost– Power– Performance

Processor Performance


• Consider subset of RISC-V instructions:– R-type instructions:

• add, sub, and, or, slt– I-type instruction:

• lw– S-type instruction:

• sw– B-type instructions:

• beq

RISC-V Processor


Determines everything about a processor:– Architectural state:• 32 registers• PC• Memory

Architectural State Elements


RISC-V Architectural State Elements

CLK

A RD

InstructionMemory

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

A RDData

MemoryWD

WEPCPCNext

CLK

R15

32 32 32 32

32

32

32

32

32

32

32

5

5

5


• Datapath• Control

Single-Cycle RISC-V Processor


• Datapath• Control



• R-type instructions: – add, sub, and, or, slt

• I-type instruction: – lw

• S-type instruction: – sw

• B-type instructions: – beq

RISC-V Processorfunct7 rs2 rs1 rd op

7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

R-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0

imm11:0 rs1 rd op12 bits 5 bits 3 bits 5 bits 7 bits

I-Typefunct3

31:20 19:15 14:12 11:7 6:0

imm11:5 rs2 rs1 imm4:0 op7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

S-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0

imm12,10:5 rs2 rs1 imm4:1,11 op7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

B-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0


Single-Cycle RISC-V Datapath

WD

A RD

WECLK

AInstructionMemory Data

Memory

A1

A3WD3

RD2

RD1WE3

A2

CLKCLK

PCNext PC InstrRD

RegisterFile


• Datapath: start with lw instruction• Example: lw t2, -8(s3)

lw rd, imm(rs1)



I-Typefunct3

31:20 19:15 14:12 11:7 6:0


STEP 1: Fetch instruction

Single-Cycle Datapath: lw fetch

WD

A RD

WECLK


Memory

A1

A3WD3

RD2

RD1WE3

A2

CLKCLK

PCNext PC InstrRD

RegisterFile


STEP 2: Read source operand (rs1) from RF

Single-Cycle Datapath: lw Reg Read

WD

19:15

A RD

WECLK


Memory

A1

A3WD3

RD2

RD1WE3

A2

CLKCLK

PCNext PC InstrRD

RegisterFile


I-Typefunct3

31:20 19:15 14:12 11:7 6:0

lw rd, imm(rs1)


STEP 3: Extend the immediate

Single-Cycle Datapath: lw Immediate

WD

19:15

31:20

A RD

WECLK

AInstructionMemory

Extend

DataMemory

A1

A3WD3

RD2

RD1WE3

A2

CLKCLK

PCNext PC InstrRD

ImmExt

RegisterFile


STEP 4: Compute the memory address

Single-Cycle Datapath: lw Address

WD

19:15

31:20

0

A RD

WECLK

A

010ALUControl2:0

InstructionMemory

Extend

DataMemory

ALU

A1

A3WD3

RD2

RD1WE3

A2ALUResult

MemWriteCLKCLK

PCNext PC InstrRDSrcA

SrcB

ImmExt

RegisterFile


STEP 5: Read data from memory and write it back to register file

Single-Cycle Datapath: LDR Mem Read

WD

19:15

31:20

11:7

WriteData

Zero

1 0

A RD

WECLK

A

010ALUControl2:0

InstructionMemory

Extend

DataMemory

ALU

A1

A3WD3

RD2

RD1WE3

A2

RegWrite

ALUResult ReadData

MemWriteCLKCLK

PCNext PC InstrRDSrcA

SrcB

ImmExt

RegisterFile


STEP 6: Determine address of next instruction

Single-Cycle Datapath: PC Increment

ImmExt

InstructionMemory

RegisterFile WD

Instr19:15

31:20

SrcB11:7

WriteData

SrcA

RegWrite

Zero

1 0

ExtendPCPlus4+

ALU

DataMemory

A RD

WE

ReadData

MemWriteCLKCLK

CLK

PCNext PC A RD

4

ALUResultA1

A3WD3

RD2

RD1WE3

A2

010ALUControl2:0

RegisterFile


Expand datapath to handle sw:• Write data in rs2 to memory• Example: sw t2, 0xc(s3)

sw rs2, imm(rs1)

Single-Cycle Datapath: sw


S-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0


• Immediate: now in {instr[31:25], instr[11:7]}• Add control signals: ImmSrc, MemWrite

Single-Cycle Datapath: Data-processing

sw rs2, imm(rs1)

ImmExt

CLK

A RDInstructionMemory

+

4

A1

A3WD3

RD2

RD1WE3

A2

CLK

Extend

A RDData

MemoryWD

WEPC Instr

19:15

24:20

31:7

SrcB11:7

ALUResult ReadData

WriteData

SrcA

MemWriteRegWrite

Zero

CLKALUControl2:0

ALU

ImmSrc

PCPlus4

PCNext

0 1 010 1

RegisterFile


S-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0


Single-Cycle Datapath: Immediate


S-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0

ImmSrc ImmExt Instruction Type0 {{20{instr[31]}}, instr[31:20]} I-Type1 {{20{instr[31]}}, instr[31:25], instr[11:7]} S-Type


I-Typefunct3

31:20 19:15 14:12 11:7 6:0


• Instructions: add, sub, and, or, slt, • Example: add s1, s2, s3

op rd, rs1, rs2

Single-Cycle Datapath: R-Type

funct7 rs2 rs1 rd op7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

R-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0


• Read from rs1 and rs2 (instead of imm)• Write ALUResult to rd

Single-Cycle Datapath: R-Type

add rd, rs1, rs2

ImmExt

CLK


+

4

A1

A3WD3

RD2

RD1WE3

A2

CLK

Extend

01

A RDData

MemoryWD

WEPC Instr

19:15

24:20

31:7

SrcB11:7

ALUResult ReadData

WriteData

SrcA

Result

MemWriteALUSrcRegWrite

Zero

CLKALUControl2:0

ALU

ImmSrc

PCPlus4

PCNext

1 X 0 varies 0 0

10

ResultSrc

RegisterFile

funct7 rs2 rs1 rd op7 bits 5 bits 5 bits 3 bits 5 bits 7 bits

R-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0


Calculate branch target address: PCTarget = PC + imm

Single-Cycle Datapath: beq

beq rs1, rs2, Label

ImmExt

CLK


+

4

A1

A3WD3

RD2

RD1WE3

A2

CLK

Extend

01

A RDData

MemoryWD

WEPC0

1

PCTarget

Instr19:15

24:20

31:7

SrcB11:7

ALUResult ReadData

WriteData

SrcA

Result

MemWriteALUSrcRegWrite

Zero

CLKALUControl2:0

ALU

ImmSrc1:0 ResultSrc

+

PCPlus4

PCNext

10

PCSrc1 0 10 0 110 0 X

RegisterFile


B-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0


Single-Cycle Datapath: ImmExtImmSrc1:0 ImmExt Instruction Type00 {{20{instr[31]}}, instr[31:20]} I-Type01 {{20{instr[31]}}, instr[31:25], instr[11:7]} S-Type10 {{19{instr[31]}}, instr[31], instr[7],

instr[30:25], instr[11:8], 1’b0}B-Type


I-Typefunct3

31:20 19:15 14:12 11:7 6:0


S-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0


B-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0



ImmExt

CLK


+

4

A1

A3WD3

RD2

RD1WE3

A2

CLK

Extend

RegisterFile

01

A RDData

MemoryWD

WEPC0

1

PCTarget

Instr19:15

24:20

31:7

6:0

SrcB11:7

ALUResult ReadData

WriteData

SrcA

Result

14:12

MemWrite

ALUSrc

RegWrite

funct3op

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

ImmSrc1:0

ResultSrc

+

PCPlus4

PCNext

funct7530

10


Single-Cycle Control

MainDecoder

ALUOp1:0

ALUDecoder

Op6:0

funct32:0 ALUControl2:0

ImmSrc1:0ALUSrc

ResultSrc1:0MemWrite

RegWrite

Branch

funct75

5

PCSrcZero


op Instruct RegWrite ImmSrc ALUSrc MemWrite ResultSrc Branch ALUOp

3 lw 1 00 1 0 1 0 00

35 sw 0 01 1 1 X 0 00

51 R-type 1 XX 0 0 0 0 10

99 beq 0 10 0 0 X 1 01

Control Unit: Main Decoder

MainDecoder

ALUOp1:0

ALUDecoder

Op6:0


ImmSrc1:0ALUSrc


RegWrite

Branch

funct75

5

PCSrcZero


Review: ALU

ALU

N N

N3

A B

Y

ALUControl

ALUControl2:0 Function000 A & B001 A | B010 A + B110 A - B111 SLT


Review: ALU

+

2 01

A B

Cout

Y

3

01

ALUControl2

ALUControl1:0

[N-1] S

NN

N

N

N NNN

N

2

Zero Extend

ALUControl2:0 Function000 A & B001 A | B010 A + B110 A - B111 SLT


Single-Cycle Control: ALU Decoder

MainDecoder

ALUOp1:0

ALUDecoder

Op6:0


ImmSrc1:0ALUSrc


RegWrite

Branch

funct75

5

PCSrcZero


ALUOp op5 funct3 funct75 Instruction ALUControl2:0

00 X X X lw, sw 010 (add)01 X X X beq 110 (subtract)10 X 000 0 add 010 (add)

1 000 1 sub 110 (subtract)

X 010 0 slt 111 (set less than)

X 110 0 or 001 (or)X 111 0 Slt 000 (and)

Control Unit: ALU Decoder

ALUOp1:0

ALUDecoder

op5funct32:0 ALUControl2:0funct75


op Instruct RegWrite ImmSrc ALUSrc MemWrite ResultSrc Branch ALUOp

51 R-type 1 XX 0 0 0 0 10

Example: or

ImmExt

CLK


+

4

A1

A3WD3

RD2

RD1WE3

A2

CLK

Extend

RegisterFile

01

A RDData

MemoryWD

WEPC0

1

PCTarget

Instr19:15

24:20

31:7

6:0

SrcB11:7

ALUResult ReadData

WriteData

SrcA

Result

14:12

MemWrite

ALUSrc

RegWrite

funct3op

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

ImmSrc1:0

ResultSrc

+

PCPlus4

PCNext

funct7530

10

01 001XX 000


Example: or

ImmExt

CLK


+

4

A1

A3WD3

RD2

RD1WE3

A2

CLK

Extend

RegisterFile

01

A RDData

MemoryWD

WEPC0

1

PCTarget

Instr19:15

24:20

31:7

6:0

SrcB11:7

ALUResult ReadData

WriteData

SrcA

Result

14:12

MemWrite

ALUSrc

RegWrite

funct3op

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

ImmSrc1:0

ResultSrc

+

PCPlus4

PCNext

funct7530

10

01 001XX 000


Extended Functionality: addiop Instruct RegWrite ImmSrc ALUSrc MemWrite ResultSrc Branch ALUOp

3 lw 1 00 1 0 1 0 00

35 sw 0 01 1 1 X 0 00

51 R-type 1 XX 0 0 0 0 10

99 beq 0 10 0 0 X 1 01

19 addi 1 00 1 0 0 0 10


Extended Functionality: addiop Instruct RegWrite ImmSrc ALUSrc MemWrite ResultSrc Branch ALUOp

19 addi 1 00 1 0 0 0 10

ImmExt

CLK


+

4

A1

A3WD3

RD2

RD1WE3

A2

CLK

Extend

RegisterFile

01

A RDData

MemoryWD

WEPC0

1

PCTarget

Instr19:15

24:20

31:7

6:0

SrcB11:7

ALUResult ReadData

WriteData

SrcA

Result

14:12

MemWrite

ALUSrc

RegWrite

funct3op

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

ImmSrc1:0

ResultSrc

+

PCPlus4

PCNext

funct7530

10


Extended Functionality: jal

MainDecoder

ALUOp1:0

ALUDecoder

Op6:0


ImmSrc1:0ALUSrc


RegWrite

Branch

funct75

5

PCSrcZero

PCUpdate

PCUpdate


Single-Cycle Datapath: ImmExtImmSrc1:0 ImmExt Instruction Type00 {{20{instr[31]}}, instr[31:20]} I-Type

01 {{20{instr[31]}}, instr[31:25], instr[11:7]} S-Type

10 {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1’b0}

B-Type

11 {{12{instr[31]}}, instr[19:12], instr[20], instr[30:21], 1’b0}

J-Type


I-Typefunct3

31:20 19:15 14:12 11:7 6:0


S-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0


B-Typefunct3

31:25 24:20 19:15 14:12 11:7 6:0

imm20,10:1,11,19:12 rd op20 bits 5 bits 7 bits

J-Type31:12 11:7 6:0


Extended Functionality: jalop Instruct RegWrite ImmSrc ALUSrc MemWrite ResultSrc Branch ALUOp PCUpdate

3 lw 1 00 1 0 10 0 00 0

35 sw 0 01 1 1 XX 0 00 0

51 R-type 1 XX 0 0 01 0 10 0

99 beq 0 10 0 0 XX 1 01 0

19 addi 1 00 1 0 01 0 10 0

111 jal 0 11 X 0 00 0 XX 1


Extended Functionality: jalop Instruct RegWrite ImmSrc ALUSrc MemWrite ResultSrc Branch ALUOp PCUpdate

111 jal 0 11 X 0 00 0 XX 1

ImmExt

CLK


4

A1

A3WD3

RD2

RD1WE3

A2

CLK

Extend

RegisterFile

01

A RDData

MemoryWD

WEPC0

1

PCTarget

Instr19:15

24:20

31:7

6:0

SrcB11:7

ALUResult ReadData

WriteData

SrcA

Result

14:12

MemWrite

ALUSrc

RegWrite

funct3op

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

ImmSrc1:0

ResultSrc1:0

+

PCPlus4+

PCNext

funct7530

100100


Program Execution Time = (#instructions)(cycles/instruction)(seconds/cycle)= # instructions x CPI x TC

Processor Performance


TC limited by critical path (lw)

Single-Cycle Performance

ImmExt

CLK


4

A1

A3WD3

RD2

RD1WE3

A2

CLK

Extend

RegisterFile

01

A RDData

MemoryWD

WEPC0

1

PCTarget

Instr19:15

24:20

31:7

6:0

SrcB11:7

ALUResult ReadData

WriteData

SrcA

Result

14:12

MemWrite

ALUSrc

RegWrite

funct3op

ControlUnit

Zero

PCSrc

CLK

ALUControl2:0

ALU

ImmSrc1:0

ResultSrc1:0

+

PCPlus4+

PCNext

funct7530

100100


• Single-cycle critical path:Tc1 = tpcq_PC + tmem + max[tmux + tRFread, text + tmux] + tALU + tmem + tmux + tRFsetup

• Typically, limiting paths are: – memory, ALU, register file – Tc1 = tpcq_PC + 2tmem + tRFread + tALU + 2tmux + tRFsetup

Single-Cycle Performance


Tc1 = ?

Single-Cycle Performance ExampleElement Parameter Delay (ps)Register clock-to-Q tpcq_PC 40Register setup tsetup 50Multiplexer tmux 25ALU tALU 120Decoder (Control Unit) tdec 70Memory read tmem 200Register file read tRFread 100Register file setup tRFsetup 60


Tc1 = tpcq_PC + 2tmem + tdec+ tRFread + tALU + 2tmux + tRFsetup= [50 + 2(200) + 70 + 100 + 120 + 2(25) + 60] ps= 840 ps

Single-Cycle Performance ExampleElement Parameter Delay (ps)Register clock-to-Q tpcq_PC 40Register setup tsetup 50Multiplexer tmux 25ALU tALU 120Decoder (Control Unit) tdec 70Memory read tmem 200Register file read tRFread 100Register file setup tRFsetup 60


Program with 100 billion instructions:

Execution Time = # instructions x CPI x TC= (100 × 109)(1)(840 × 10-12 s)= 84 seconds

Single-Cycle Performance Example


• Single-cycle:+ simple- cycle time limited by longest instruction (lw)- separate memories for instruction and data- 3 adders/ALUs

• Multicycle processor addresses these issues by breaking instruction into shorter stepso shorter instructions take fewer stepso can re-use hardwareo cycle time is faster

Multicycle RISC-V Processor


• Single-cycle:+ simple- cycle time limited by longest instruction (LDR)- separate memories for instruction and data- 3 adders/ALUs

• Multicycle:+ higher clock speed+ simpler instructions run faster+ reuse expensive hardware on multiple cycles- sequencing overhead paid many times



• Single-cycle:+ simple- cycle time limited by longest instruction (LDR)- separate memories for instruction and data- 3 adders/ALUs

• Multicycle:+ higher clock speed+ simpler instructions run faster+ reuse expensive hardware on multiple cycles- sequencing overhead paid many times


Same design steps as single-cycle: • first datapath• then control


Replace Instruction and Data memories with a single unified memory – more realistic

Multicycle State Elements

CLK

ARD

Instr / DataMemory

PC

WD

WE

CLK

EN

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

PCNext


STEP 1: Fetch instruction

Multicycle Datapath: Instruction Fetch

CLK

APC

WD

RD2A2

CLK

RegisterFile

Instr

CLK

EN

IRWrite

ENInstr / Data

Memory

WERD

CLK

A1

A3WD3

WE3RD1

PCNext


lw rd, imm(rs1)

Multicycle Datapath: lw get sources

STEP 2: Read source operand from RF and extend immediate


I-Typefunct3

31:20 19:15 14:12 11:7 6:0

ARDPC

Instr

WD

WEA1

A3WD3

WE3

A2

19:15

31:20

CLK

Instr / DataMemory

RegisterFile

Extend

CLK

Rs1

CLK

RD1

RD2

CLKCLK

EN

ImmExt

IRWrite

PCNextA


Multicycle Datapath: lw Address

STEP 3: Compute the memory address

ARDPC

InstrALUResult

SrcA

ALUOut

WD

WE CLKA1

A3WD3

WE3

A2

19:15

31:20

CLK

ALU

Instr / DataMemory

RegisterFile

Extend

ALUControl2:0

CLK

Rs1

CLK

RD1

RD2

CLKCLK

EN

ImmExt

SrcB

IRWrite

PCNextA

lw rd, imm(rs1)imm11:0 rs1 rd op12 bits 5 bits 3 bits 5 bits 7 bits

I-Typefunct3

31:20 19:15 14:12 11:7 6:0


Multicycle Datapath: lw Memory Read

STEP 4: Read data from memory

ARD Instr

ALUResult

SrcA

ALUOut

WD

WEA1

A3WD3

WE3

A2

19:15

31:20

CLK

ALU

Instr / DataMemory

RegisterFile

Extend

ALUControl2:0

CLK

Rs1

CLK

RD1

RD2

AAdr

CLK

EN

ImmExt

SrcB

IRWrite

PCPCNext

Data

CLK

ReadD

ata

CLK

01EN

AdrSrc

CLK


I-Typefunct3

31:20 19:15 14:12 11:7 6:0


Multicycle Datapath: lw Write Register

STEP 5: Write data back to register file

ARD Instr

ALUResult

SrcA

ALUOut

WD

WE CLKA1

A3WD3

WE3

A2

19:15

31:20

CLK

ALU

Instr / DataMemory

RegisterFile

Extend

ALUControl2:0

CLK

Rs1

CLK

RD1

RD2

AAdr

CLK

EN

ImmExt

SrcB

IRWrite

PCPCNext

Data

CLK

ReadD

ata

11:7 Rd

CLK

01EN

AdrSrc RegWrite

100100

ResultSrc1:0


I-Typefunct3

31:20 19:15 14:12 11:7 6:0


Multicycle Datapath: Increment PC

STEP 6: Increment PC: PC = PC+4

ARD Instr

ALUResult

SrcA

ALUOut

WD

WE CLKA1

A3WD3

WE3

A2

19:15

31:20

CLK

ALU

Instr / DataMemory

RegisterFile

Extend

ALUControl2:0

CLK

Rs1

CLK

RD1

RD2

AAdr

CLK

EN

ImmExt

SrcB

IRWrite

PCPCNext

Data

CLK

ReadD

ata

11:7 Rd

CLK

01EN

AdrSrc RegWrite ALUSrcA1:0

4

ALUSrcB1:0

PCWrite

0110

000110

00

ResultSrc1:0

Result

100100


Write data in rs2 to memory

Multicycle Datapath: sw

ARDPC 0

1

InstrALUResult

SrcA

ALUOut

MemWrite

Zero

ResultSrc1:0

WD

WE

CLK

4

CLK

IRWrite

A1

A3WD3

WE3

A2

19:15

11:7

31:7

24:20 000110

Result

Rs2

CLK

OldPC

Rd

000110

000110

ALU

WriteD

ata

Instr / DataMemory

RegisterFile

Extend

ALUSrcB1:0

ALUSrcA1:0 ALUControl2:0RegWrite ImmSrc1:0

CLK

Rs1

CLK

RD1

RD2

A

AdrSrcPCWrite

CLK

ENAdr

CLK

EN

ReadD

ata

DataImmExt

SrcB

PCNext


Write data in rs2 to memory

Multicycle Datapath: sw

ARDPC 0

1

InstrALUResult

SrcA

ALUOut

MemWrite

Zero

ResultSrc1:0

WD

WE

CLK

4

CLK

IRWrite

A1

A3WD3

WE3

A2

19:15

11:7

31:7

24:20 000110

Result

Rs2

CLK

OldPC

Rd

000110

000110

ALU

WriteD

ata

Instr / DataMemory

RegisterFile

Extend

ALUSrcB1:0

ALUSrcA1:0 ALUControl2:0RegWrite ImmSrc1:0

CLK

Rs1

CLK

RD1

RD2

A

AdrSrcPCWrite

CLK

ENAdr

CLK

EN

ReadD

ata

DataImmExt

SrcB

PCNext


Calculate branch target address: BTA = PC + imm

Multicycle Datapath: beq

ImmExt

CLK

ARD

Instr / DataMemory

PC 01

Instr

SrcB

ALUResult

SrcA

ALUOut

MemWrite ALUSrcA1:0RegWrite

Zero

ResultSrc1:0ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

AWriteD

ata

4

CLK

EN

ALUSrcB1:0

IRWriteAdrSrcPCWrite

ReadD

ata

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

19:15

11:7

31:7

24:20

Result

ImmSrc1:0

Extend

Rs1

Rs2

CLK

OldPC

Rd

EN

000110

000110

000110

PCNext

PC was already updated in Fetch stage, so need to save old PC



ImmExt

CLK

ARD

Instr / DataMemory

PC 01

Instr

SrcB

ALUResult

SrcA

ALUOut

MemWrite

ALUSrcA1:0

RegWrite

Zero

ResultSrc1:0

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

WriteD

ata

4

CLK

EN

ALUSrcB1:0

IRWrite

AdrSrcPCWrite

ReadD

ata

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

19:15

11:7

31:7

24:20 000110

Result

14:12

30 funct75funct3

Zero

6:0 op

ControlUnit

ImmSrc1:0

Extend

Rs1

Rs2

CLK

OldPC

Rd

EN

000110

100100

PCNext


Multicycle Control

MainFSM

ALUOp1:0

ALUDecoder

Op6:0


ImmSrc1:0ALUSrcA1:0

ResultSrc1:0ALUSrcB1:0

AdrSrc

Branch

funct75

5

Zero

IRWrite

RegWriteMemWrite

PCUpdate

ImmSrc1:0Instr

DecoderOp6:0

PCWritePCUpdate


Multicycle Control

MainFSM

ALUOp1:0

ALUDecoder

op6:0


ImmSrc1:0ALUSrcA1:0


AdrSrc

Branch

funct75

5

Zero

IRWrite

RegWriteMemWrite

PCUpdate

ImmSrc1:0Instr

Decoderop6:0

PCWritePCUpdate

ALU Decoder same as single-cycle


Multicycle Control: Instr Decoder

ImmSrc1:0Instr

Decoderop6:0

op Instruction ImmSrc3 lw 0035 sw 0151 R-type XX99 beq 10



ImmExt

CLK

ARD

Instr / DataMemory

PC 01

Instr

SrcB

ALUResult

SrcA

ALUOut

MemWrite

ALUSrcA1:0

RegWrite

Zero

ResultSrc1:0

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

WriteD

ata

4

CLK

EN

ALUSrcB1:0

IRWrite

AdrSrcPCWrite

ReadD

ata

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

19:15

11:7

31:7

24:20 000110

Result

14:12

30 funct75funct3

Zero

6:0 op

ControlUnit

ImmSrc1:0

Extend

Rs1

Rs2

CLK

OldPC

Rd

EN

000110

100100

PCNext


Multicycle Control: Main FSM

MainFSM

ALUOp1:0

op6:0ImmSrc1:0ALUSrcA1:0


AdrSrc

Branch

Zero

IRWrite

RegWriteMemWrite

PCUpdate

PCWritePCUpdate


Main Controller FSM: Fetch

S0: FetchAdrSrc = 0

IRWrite

Reset

ImmExt

CLK

ARD

Instr / DataMemory

PC 01

Instr

SrcB

ALUResult

SrcA

ALUOut

MemWrite

ALUSrcA1:0

RegWrite

Zero

ResultSrc1:0

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

WriteD

ata

4

CLK

EN

ALUSrcB1:0

IRWrite

AdrSrcPCWrite

ReadD

ata

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

19:15

11:7

31:7

24:20 000110

Result

14:12

30 funct75funct3

Zero

6:0 op

ControlUnit

ImmSrc1:0

Extend

Rs1

Rs2

CLK

OldPC

Rd

EN

000110

100100

PCNext

10 00 XX XXXXX XXXX0


Main Controller FSM: Decode

ImmExt

CLK

ARD

Instr / DataMemory

PC 01

Instr

SrcB

ALUResult

SrcA

ALUOut

MemWrite

ALUSrcA1:0

RegWrite

Zero

ResultSrc1:0

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

WriteD

ata

4

CLK

EN

ALUSrcB1:0

IRWrite

AdrSrcPCWrite

ReadD

ata

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

19:15

11:7

31:7

24:20 000110

Result

14:12

30 funct75funct3

Zero

6:0 op

ControlUnit

ImmSrc1:0

Extend

Rs1

Rs2

CLK

OldPC

Rd

EN

000110

100100

PCNext

0X 00 00 XXXXX XXXX0

S0: FetchAdrSrc = 0

IRWrite

S1: Decode

Reset


Main Controller FSM: Address

ImmExt

CLK

ARD

Instr / DataMemory

PC 01

Instr

SrcB

ALUResult

SrcA

ALUOut

MemWrite

ALUSrcA1:0

RegWrite

Zero

ResultSrc1:0

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

WriteD

ata

4

CLK

EN

ALUSrcB1:0

IRWrite

AdrSrcPCWrite

ReadD

ata

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

19:15

11:7

31:7

24:20 000110

Result

14:12

30 funct75funct3

Zero

6:0 op

ControlUnit

ImmSrc1:0

Extend

Rs1

Rs2

CLK

OldPC

Rd

EN

000110

100100

PCNext

0X 00 XX 01010 XX010

S0: FetchAdrSrc = 0

IRWrite

S1: Decode

Reset

S2: MemAdrALUSrcA = 10ALUSrcB = 01ALUOp = 00

op = lw OR

op = sw


Main Controller FSM: Read Memory

S0: FetchAdrSrc = 0

IRWrite

S1: Decode

S3: MemReadResultSrc = 10

AdrSrc = 1

Reset


op = lw OR

op = sw

op = lw



ImmExt

CLK

ARD

Instr / DataMemory

PC 01

Instr

SrcB

ALUResult

SrcA

ALUOut

MemWrite

ALUSrcA1:0

RegWrite

Zero

ResultSrc1:0

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

WriteD

ata

4

CLK

EN

ALUSrcB1:0

IRWrite

AdrSrcPCWrite

ReadD

ata

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

19:15

11:7

31:7

24:20 000110

Result

14:12

30 funct75funct3

Zero

6:0 op

ControlUnit

ImmSrc1:0

Extend

Rs1

Rs2

CLK

OldPC

Rd

EN

000110

100100

PCNext

01 00 XX XXXXX 10XX0


AdrSrc = 1


Main Controller FSM: Write RF

S0: FetchAdrSrc = 0

IRWrite

S1: Decode


AdrSrc = 1

Reset

S4: MemWBResultSrc = 01

RegWrite


op = lw OR

op = sw

op = lw


Main Controller FSM: Write RF

ImmExt

CLK

ARD

Instr / DataMemory

PC 01

Instr

SrcB

ALUResult

SrcA

ALUOut

MemWrite

ALUSrcA1:0

RegWrite

Zero

ResultSrc1:0

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

WriteD

ata

4

CLK

EN

ALUSrcB1:0

IRWrite

AdrSrcPCWrite

ReadD

ata

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

19:15

11:7

31:7

24:20 000110

Result

14:12

30 funct75funct3

Zero

6:0 op

ControlUnit

ImmSrc1:0

Extend

Rs1

Rs2

CLK

OldPC

Rd

EN

000110

100100

PCNext

0X 10 XX XXXXX 01XX0


RegWrite


Main Controller FSM: Fetch Revisited

S0: FetchAdrSrc = 0

IRWriteALUSrcA = 00ALUSrcB =10ALUOp = 00

ResultSrc = 00PCUpdate

Reset

• ALU isn’t being used• Use ALU to calculate PC+4



S0: FetchAdrSrc = 0



S1: Decode


AdrSrc = 1

Reset


RegWrite


op = lw OR

op = sw

op = lw



ImmExt

CLK

ARD

Instr / DataMemory

PC 01

Instr

SrcB

ALUResult

SrcA

ALUOut

MemWrite

ALUSrcA1:0

RegWrite

Zero

ResultSrc1:0

CLK

ALUControl2:0

ALU

WD

WE

CLK

Adr

Data

CLK

CLK

A

WriteD

ata

4

CLK

EN

ALUSrcB1:0

IRWrite

AdrSrcPCWrite

ReadD

ata

A1

A3WD3

RD2

RD1WE3

A2

CLK

RegisterFile

19:15

11:7

31:7

24:20 000110

Result

14:12

30 funct75funct3

Zero

6:0 op

ControlUnit

ImmSrc1:0

Extend

Rs1

Rs2

CLK

OldPC

Rd

EN

000110

100100

PCNext

10 00 XX 01000 00101

S0: FetchAdrSrc = 0



Reset • PC+4: shown in blue• Instr fetch: shown in gray

Documents

David M. Harris and Sarah L. Harris - Harvey Mudd Collegepages.hmc.edu/harris/class/e85/Chapter_7_Lecture_Slides.pdf · series of shorter steps ... 31:25 24:20 19:15 14:12 11:7 6:0