DC-DC Converter Design Phase Acceleration with Virtuoso ... · DC-DC Converter Design Phase Acceleration with Virtuoso® UltraSim Simulator • Mohamed Bouhamame, Didier Depreeuw

DC-DC Converter Design Phase Acceleration with Virtuoso® UltraSimSimulator

• Mohamed Bouhamame, Didier Depreeuw

• NXP Semiconductors Caen France

ROBUSPIC, M.Bouhamame September 22, 2006

2

Outline

MotivationsDC-DC converter topologyImplementation UltrasimDC-DC converter settingSimulation & measurement resultsConclusions


3

Motivations

A Controllable high voltage DC-DC Converter

High level of integration

Low power consumption

Tunable RF filter with High linearity and High selectivity


4

CsD1

Cs

C C

D2 D3

Cs CsDn-1 Dn

C C CoutRL

VoutVin

CkCkn

Where:- N is the number of commutating stages (N=20)- f is the operating frequency of the charge pump (f=16MHz)- Cs is the stray capacitance at each node (1fF)- Iout is the DC current required to drive the load for a given output voltage

How to decrease the output voltage rapidly?

+++−=

f*)s

CC(out

I

dV

ckV*

sCC

C*Nd

Vin

Vout

V --

DC-DC converter topology


5

Why Tunable RF Filter?

Tunable Filters are needed because of :

High dynamic range of the received signals

Wide input bandwidth (F=[50MHz…870MHz])

Tracking filter used in traditional TV tuner

)(vC

pC

vminCvmaxC

minfmaxf

>>=Provider by the DC-DC

L1

L2Cp

Cv RVtune=0.8V..28V

Antenna


6

C1

C’3 C’

2 C’1

C2 C3

VoutD1 D2 D3

D3 D2 D1

M diodes N diodes

CkupnCkupp

CkdwnCkdwp

DC-DC UP

DC-DC DOWN

Implementation

Dickson Charge pump is implemented in 2.8V Bi-CMOS 0.25µm

Technology (Break down voltage for collector substrate is Bvcs0=80V )

Stray capacitance Cs has been reduced by the shielding done by the poly layer

Vout < (N+M)*Vd (Vd is the forward bias voltage of the diode)

C

Fringe capacitor


7

VrefCkCkn

VckVck

C

R

15M

1M

ProgDAC

Vout=Vtune

+-

Implementation

Resistors used have a breakdown voltage more than 200V and have a sheet resistance of 2000 /square

Vref enables to tune the center frequency of the tracking filter(Vref =Vout/16)

Spectre simulation time is really long! (40000 switching periods are required to capture the power-up (the output voltage starts from 0 volt to reach the steady state of 24 volts)

How to decrease the time simulation?


8

UltraSim is a fast-spice hierarchical circuit simulator (Transistor level) which combines a variety of simulation technologies to allow high-capacity simulation of memories, digital, analog, RF and mixed-signal ICs with spice-like accuracy

What Is Ultrasim ?


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Cadence’s Slide

Ultrasim : Fast SPICE Technology


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Applications:

Full-chip simulation

Analog/MS/D/Memory

Pre-/Post Layout

Tran

1B+ device capacity

Applications:

Large Block Design

MS/Digital/Memory

Pre-/Post Layout

Tran

1M device capacity

Applications:

Block design

Analog/MS

Pre Layout

Tran, AC, Noise, RF

50K device capacity

Technologies:

Fast-SPICE technologies

Hierarchy

Isomorphism

Technologies:

Simplified Models: PWL, Table

Matrix Partitioning

Event-driven

Multi-rate

RC reduction

Technologies:

Compact models

Sparse Matrix Solver

Time step, Newton-raphson

Hier-SPICE:Fast-SPICE:SPICE:

Transistor Level Circuit Simulation Overview


11

Cadence’s Slide

UltraSim 3rd Generation Transistor Level Simulator


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UltraSim Simulation Modes


13

Different time steps for partitions

High frequency partition : small time step

Small frequency partition : bigger time step

UltraSim Multirate simulation


14

UltraSim Speed Options Cadence’s slide


15

Simkit MN11 and MOS9 are supportedin Ultrasim for the following models:

• DF• DA• A• Spice

The same study of theId_Vd & Id_VgdifferencesIs under investigation

UltraSim Simulation Models Overview


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Circuit inventory:Nodes 307Equations 796bjt504 76capacitor 57diode 101isource 2juncap 696mos1100e 278phy_res 78resistor 15vcvs 2vsource 6

cadence_ic 5.10.41.500.2.26cadence_ius 5.5.s001cadence_mmsim 6.0.1.174

the server define below is used :OS: Linux 2.4.21-15.ELhugemem i686Memory: available 4.1157 GB physical 8.3916 GBSwap: available 3.2410 GB physical 4.1784 GBCPU: CPU0 AMD Opteron(tm) Processor 250 2388.905MHzCPU1 AMD Opteron(tm) Processor 250 2388.905MHz

DC-DC converter setting

We need to set vdd=1.8 to get accurate table model creation!.usim_opt progress_p=1 vdd=1.8


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Simulation & measurement results

0

5

10

15

20

25

0 0,5 1 1,5 2t (ms)

Vout (V)

spectre

ultrasim

Ultrasim versus Spectre Less than 0.003% diff

0

5

10

15

20

25

0 0,4 0,8 1,2 1,6 2t (ms)

Vout (V)

spectreultrasimmeasurement

Simulation time result using local settingUsing Ultrasim, the circuit simulation time is six times faster with the same accuracy compare to Spectre


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Measurement results

19

21

23

25

27

29

31

1,4 1,75 2,1 2,45 2,8

Vref (V)

Vout

(V)

T=Tnom

T=85C

T=-20C

Voltage output range 0V … 30 V

Output current max 8 µA

Supply current max 1mA

When Iout=8µA, f=16MHz, N=20, Vd=0.6V, C=700fF and Cs=1fF, Vout =32V

The temperature dependency of the output voltage is negligible


19

Voltage regulation,Clock generation

DC/DC UP DC/DC DOWN

Die photograph

Technology : 0.25µm Bi-CMOS ft=40GHz

Area : 620µm*262µm


20

Ultrasim Pros & Cons

ProsTime saving with the same accuracy

Factor 6 with DC DC ConverterWould have been a great help on time saving during the design phase

ConsSpectre is the reference tool, take care of ultrasim simulation results of a

global system for which spectre simulation is not possibleSometimes prohibitive simulation time due to not optimized local settings

: use the activity reportTransient analog signal, no RF capabilitiesBipolar transistors not taken into account in the table model simplificationUltrasim-Verilog : not possible to save / load an intermediate step


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Conclusions

A Controllable High Voltage DC-DC converter has been presented

A novel solution has been used to decrease the output voltage rapidly

The new discharge system solves the problem of the high tuning voltage requirement for MEMS and SMD variable capacitors

The forward bias voltage Vd is the main limitation of the output voltage

Ultrasim have been a great help on time saving during the design phase

Ultrasim allows the exploration of more design configurations, the accuracy is excellent for such Bi-CMOS circuit

Ultrasim simulator is a very efficient to make possible bottom-up verification for all IC builder


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Acknowledgements

Jean Robert Tourret, NXP Semiconductors

Luca Lococo, NXP Semiconductors

Serge Toutain, IREENA

André Baguenier, Cadence

Thanks for your attention!

Any Question ?

Documents

DC-DC Converter Design Phase Acceleration with Virtuoso ... · DC-DC Converter Design Phase Acceleration with Virtuoso® UltraSim Simulator • Mohamed Bouhamame, Didier Depreeuw