DCS Printout

8/2/2019 DCS Printout

http://slidepdf.com/reader/full/dcs-printout 1/19

To implement the 4X1 Multiplexer

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

entity Mux is Port ( s1 : in STD_LOGIC;

s2 : in STD_LOGIC; d1 : in STD_LOGIC; d2 : in STD_LOGIC; d3 : in STD_LOGIC; d4 : in STD_LOGIC; y : out STD_LOGIC);

end Mux;

architecture Behavioral of Mux is

begin

y<= d1 when s1='0' and s2='0' else d2 when s1='0' and s2='1' else d3 when s1='1' and s2='0' else d4 when s1='1' and s2='1' ;

end Behavioral;





OUTPUT



To implement the Demultiplexer


entity Demux is Port ( s1 : in STD_LOGIC;

s2 : in STD_LOGIC; d : in STD_LOGIC; d1 : out STD_LOGIC; d2 : out STD_LOGIC; d3 : out STD_LOGIC; d4 : out STD_LOGIC);

end Demux;

architecture Behavioral of Demux is

begin

d1 <= d when s1='0' and s2='0';

d2 <= d when s1='0' and s2='1';

d3 <= d when s1='1' and s2='0';

d4 <= d when s1='1' and s2='1';

end Behavioral;





OUTPUT



To implement the Encoder


entity Encoder is Port ( s : in STD_LOGIC_VECTOR (3 downto 0);

y : out STD_LOGIC_VECTOR (1 downto 0)); end Encoder;

architecture Behavioral of Encoder is

begin

y <= "00" when s="0001" else "01" when s="0010" else "10" when s="0100" else "11" when s="1000";

end Behavioral;



OUTPUT



To implement the Decoder


entity Decoder is Port ( a : in STD_LOGIC;

b : in STD_LOGIC; enable : in STD_LOGIC; z0 : out STD_LOGIC; z1 : out STD_LOGIC; z2 : out STD_LOGIC; z3 : out STD_LOGIC);

end Decoder;

architecture Behavioral of Decoder is

begin

z3<= not( a and b and enable); z2<= not(a and (not b) and enable); z1<= not((not a) and b and enable); z0<= not((not a) and (not b) and enable);

end Behavioral;





OUTPUT



SR Flip Flop:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity sr1 is Port ( s : in STD_LOGIC;

r : in STD_LOGIC; q : inout STD_LOGIC; qn : out STD_LOGIC);

end sr1; architecture sr of sr1 is begin qn <= q when s='0' and r='0' else

'0' when s='0' and r='1' else '1' when s='1' and r='0';

Q <= '0' when s='0' and r='1' else '1' when s='1' and r='0';

end sr;



OUTPUT



JK Flip Flop:-

library IEEE;






--library UNISIM;


entity jk is Port ( j : in STD_LOGIC;

k : in STD_LOGIC; q : inout STD_LOGIC; qn : out STD_LOGIC);

end jk; architecture jk1 of jk is begin qn <= q when j='0' and k='0' else

'0' when j='0' and k='1' else '1' when j='1' and k='0' else (not q) when j='1' and k='1';

Q <= '0' when j='0' and k='1' else '1' when j='1' and k='0';

end jk1;



OUTPUT



T Flip Flop:-

library IEEE;







--library UNISIM;


entity T is Port ( t : in STD_LOGIC;

q : out STD_LOGIC; qbar : out STD_LOGIC);

end T; architecture Behavioral of T is begin q <= '0' when t='1' else

'1' when t='0'; qbar <= '1' when t='1' else

'0' when t='0'; end Behavioral;



OUTPUT



D Flip Flop:-

library IEEE;







--library UNISIM;


entity D is Port ( d : in STD_LOGIC;

q : out STD_LOGIC; qbar : out STD_LOGIC);

end D; architecture Behavioral of D is begin q <= '0' when d='0' else

'1' when d='1'; qbar <= '1' when d='0' else

'0' when d='1'; end Behavioral;



OUTPUT

Documents

DCS Printout