Monitor TilingIntroductionMonitor tiling is defined as arranging multiple displays in a tiled fashion intoone large display, or video wall, with each individual monitor displaying aportion (tile) of the whole image. The need for monitor tiling is driven by thepublic display market. The ability to have a large display within which you canchange content almost instantly appeals heavily to retailers, advertisers andothers who use public displays.

Applications for monitor tiling include: • Retail advertising • Tradeshow displays • Public information (airport) • High-impact presentations

Technologies used for monitor tilingMost monitor tiling technologies utilize one or more video cards that candrive multiple monitors. The amount of monitors, however, is limited by theoperating system. Windows® operating systems have the following limits:

Windows 98: up to 9 displays to one systemWindows 2000: up to 10 displays to one systemWindows NT: up to 20 displays to one system

The computer/operating software generates an image and sends it to the video card, which is responsible for sending theimages to the monitor/LCD screen. The operating software recognizes that there is more than one video card and sends theportions of the video to the respective video cards. Most monitors are passive devices that simply display what is sent. It isthe video card and the operating system that are really running the show.

The video card is an important component in any computer and plays an especially important role in multi-screen systems.The reason is that the video card can act as the bottleneck in the system and slow down what one sees. For applications thatrequire different high-resolution images on each tile, the best solution is still the video card method.

Tile MatrixTM is a technology built into some NEC-Mitsubishi monitors that can display the whole or a portion of the image asdetermined by the user. This technology allows the user to create a video wall using a video card, video splitter and monitors.A video splitter (commonly available in 4- , 8- and 16-output configurations) duplicates the video signal from one single inputto many outputs. They can be cascaded, making it is relatively easy to drive up to 100 monitors with a single video source.

By using video memory in the monitor, the intelligenceto split the screen into small portions is handled by themonitor and not the video card. TileMatrix can exceedthe limits of the operating system for monitors, allowingup to a 5 x 5 matrix (25 monitors) video wall. Eachmonitor requires the same input signal, for which aportion can be displayed on each monitor as determinedby the user. For a 2 x 2 matrix (4 monitors), the monitorin the upper left can be set to display the upper left ¼of the image and so on (see image at right)

The maximum number of monitors depends on theresolution of the source video signal, while the minimum

resolution of one block (tile) is 320 dots ( Hor. ) * 240 lines ( Ver. ). See the table below for more details.

Where is tiling technology headed?Newer operating systems will have the ability to use more video cards, and video card makers are making faster and lessexpensive multiple monitor display cards. The ability to run multiple monitors and display and update different images on eachis being reviewed by the VESA DPVL committee.

Digital Packet Video Link (DPVL) enables selective refresh on conventional digital display interfaces. The selective refreshallows the host to transmit only modified regions in the screen. Thus, the video transmission rate is decoupled from therefresh rate of the display device. The selective refresh allows multiple monitors to share a large virtual screen, so that DPVLcan support multiple monitors in a more flexible way than conventional interfaces. DPVL can be implemented withoutsignificant modifications in existing systems. Furthermore, the format of the video stream can be expanded to support moresophisticated formats, such as high-color format selective scaling and graphics commands.

Sources:http://www.vesa.org/membership_committees_DPVLC.html

This white paper was published in and based on information as of June 2004. Technical information is subject to change.