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Designing with DDS A high speed solution for portable and handheld applications

Jeff Keip - Analog Devices&

David Askins Avnet Electronics


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Agenda

Basic DDS reviewDDS engineDDS features

AD9913 ultra low power DDSComparing stand alone DDS vs. FPGA embedded DDSengine

Ease of implementationPerformance

CostProgrammable Modulus explained


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Quick Review of DDS

Direct Digital Synthesis is: A DIGITAL technique for generating sine waves from a fixed-frequency clock source

By using DDS:

The sine wave FREQUENCY is digitally tunable to sub-Hertzresolution

The sine wave PHASE is digitally adjustable

There are NO ERRORS from drift due to temperature or aging of

componentsThe synthesizer is AGILE; frequency and phase changes are madequickly with near-zero settling time

Frequency, phase and amplitude ramps are easy to implement


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p-bit Phase

Register FTW

Basic DDS System p-bit DDS with N-bit DAC

p-bitphase

resolution(p=6)

01

234

63

024

3129

N-bitamplituderesolution

(N=5)

p-bit Phase

Accumulator

(t ) = 2 INTM2p (t f Clk )

p N + 2~4

(t )

Phase Amplitude

Conversion

Clock

FTW = round (2p )f Outf Clk

N-bitDAC

N

1f Clk

s i n ( )


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5

1f Out

p-bit Phase

Register FTW


p-bitphase

resolution(p=6)

01

234

63

024

3129


(N=5)

p-bit Phase

Accumulator


p N + 2~4

(t )

Phase Amplitude

Conversion

Clock


N-bitDAC

N

1f Clk

s i n ( )

vector dataraw DDS-DAC output


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6

1f Out

p-bit Phase

Register FTW


p-bitphase

resolution(p=6)

01

234

63

024

3129


(N=5)

p-bit Phase

Accumulator


p N + 2~4

(t )

Phase Amplitude

Conversion

Clock


N-bitDAC

N

filtered output

To Mix er,Mod/Demod,

etc.

1f Clk

6~8 Order

OR

s i n ( )


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Useful DDS Features

Frequency Tuning ResolutionFiner tuning capability than even fractional N PLLsPhase Offset Word

Phase tuning implemented digitally to .022 resolution

Auxiliary (Sweep) accumulator Enables Frequency/phase/amplitude ramping and Programmable Modulus

Amplitude Scaling Factor Digital magnitude control on output

Profiles/Shift KeyingExtremely low settling times with no ringing

RAMOne way of implementing non-linear sweeps and shift keying

Matched LatencyFrequency, phase, and amplitude changes all affect the output simultaneously

Clear Phase Accumulator Can establish known phase on F/P/A changes


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Phase Tuning Resolution

POW (Phase Word -- K bits)Register value sets resolution

POW x 360

2K

POW x 2 2K

phase equation: out =

=

degrees

radians

p-bit PhaseAccumulator

p (t )sin(x)cos(x)

POW


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Auxiliary Accumulator

Ease of implementation for frequency sweeping makes DDSgood option in radar system

p-bit PhaseAccumulator

pM

(t )

q-bit DeltaRegister D q

D p-bit Aux.Accumulator

M

M is now a variablerather than a constant

sin(x)cos(x)

/KSampleClock


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Auxiliary Accumulator:Frequency Sweep

DDS

ReferenceOscillator

PLL

VCO2x

multPA

ANTENNA

frequency sweep

ReceiveMixer

ADCDSP

Micro-controller

X

UpconversionCircuitry if needed

Radar SystemBlock Diagram

Ease of implementation for frequency sweeping makes DDSgood option in radar system


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Matched Latency

Unmatched Matched

Output reflects Amplitude change

Output reflects Phase change

Output reflectsFrequency change

Output reflects A, , and Fchanges simultaneously


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Application Example Clear phaseaccumulator

Clear Phase accumulator function enables system to reset

the phase of the DDS to 0 easilyMay be made automatic when changing profile

GPSRCVR

AD9913I/O

Update

SYSCLK Ref

ADCMP607 AD9549

SYSCLK Ref

Application: GPS Synch

12.8 MHz 12.8 MHz

8 kHz

10MHz


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Useful DDS Features

REFCLK multiplier & PLL (Agile RF) Allows for output frequencies higher than the referenceMulti-chip Synchronization

Digital and precise

Zero Crossing BitEases system synchronization efforts

Comparator Allows for square wave output

Angle to Amplitude BypassDigital ramping output instead of sinusoid


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AD9913Primary Design considerationsLow Power


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The Greening of DDS for IF generation

P o w e r

C o n s u m p t

i o n - m

W

Bandwidth - MHz

25 50 100 200

50

100

200

150

AD9913

Existing DDSportfolio

Existing PLLportfolio

The AD9913 cuts asignificant swath in the

power/frequency gapthat exists betweenexisting DDS and PLLs


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AD9913 application examples

C o s

t S e n s i t

i v i t y

Power Sensitivity

Low

Low

High

High

Older GenerationDDS Devices AD9913

Apps served by FPGAEmbedded

RadarDetection Radio

Controllers

WirelessScanners

Soldier ofthe Future

WirelessMonitors

Portable

Instruments

UAV
http://www.futaba-rc.com/radios/futj9300.htmlhttp://www.futaba-rc.com/radios/futj9300.html


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FPGA

Where should I get my DDS function?

DDSEngine

DAC

C

From my FPGA?

Or on myDAC?

C

AD9913

FPGA


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Key factors when implementing a DDS in aFPGA

Ease of implementation

Amount of resources used, i.e. memory cells or logic blocks used.

Performance

Cost


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Ease of Implementation

Generating a DDS engine in an FPGA is straight forward andsimple

Utilize Core Gen tool to develop the engine

GUI interface makes it easyInput the desired DDS requirements and parametersF OUT , modulation scheme FSK, ASK, SFDR level, etcBuild or compile the core and load it into the FPGA

The Core Gen tool will build the DDS engine accordingly


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Amount of resources used

Resources in an FPGA are memory cells

FPGA logic implementation typically requires 3x to 4x the siliconcontent for the same IC implementation

Phase to amplitude conversion in a FPGA is done with a lookuptable

The table is sized according to desired SFDR levelThis can make the table very deep requiring a very large amount of

resourcesThe AD9913 utilizes a real time algorithm for the phase to amplitudeconversion


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Performance of the FPGA DDScontinued

Now lets look at some major design considerations

The FPGA DDS is the digital DDS engine only, an external DAC isrequired in order to generate the desired analog output

This is critical when implementing a DDS design for a couple ofreason

The interface between the DDS engine and the DACThe interface can be a source of noise generation and reduced performance

if not done properly

The choice of DACChoice of the DAC can greatly affect the overall system performanceSFDR and noise floor can degrade due to a low performance DAC


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Performance of the FPGA DDScontinued

With the AD9913 the DAC function is integrated onboard the deviceThe DAC is matched to the DDS core to maximize system performance

Design requirements are simplified for the engineer


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Cost of Implementation

The cost if implementing a FPGA DDS is higher due to

The increased amount of resources required to implement the same ICfunction, i.e. 3x to 4x silicon requirement

Lookup table depth

Requires an external DAC


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COS(X)FTW

PhaseOffsetRAM

RAM

ProfileRegisters

ProfileRegisters

SIN(X)

xsin(x)

RAM

Auxiliary Accumulator

POW

Prog.Modulus

Logic

Auxiliary Accumulator:Programmable Modulus

State of the art DDSCore block diagram

New DDS frequency equation: F out =FTW x F

SAMYY is any value between 2(FTW) and 2 Z, where Z is the # ofbits in the linear sweep accumulator, or select values between2 Z and 2 X+Z where X is the # of bits in the phase accumulator

When Programmable modulus mode is active, The divisor inthe DDS frequency equation becomes a user-definedvariable


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Tuning Resolution effect of ProgrammableModulus

Example using3 bit accumulators

0.25 0.50

Standard Tuning word options

1

2

3


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0.25 0.50

Standard Tuning word options

from 3 usable options


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0.25 0.50

Programmable ModulusStandard Tuning word options

To 70(+) usable options!


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Conclusion

The introduction of the AD9913 meansDDS is now significantly more usable in portable/handheldapplicationsDesigners relying on FPGA based DDS engines have a better

alternativeThe frequency tuning benefit of DDS has taken a quantum leapforward thanks to Programmable Modulus

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