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Faculty of Computer Science and Engineering HCMUT
SoC on FPGA Embedded SystemsFPGA Laboratory
Goal Understand the mechanism of the Altera Cyclone II
FPGA device.
Understand design flow on FPGA
Develop programmable interface for a Soc on
FPGA
Resource Altera Cyclone II 2C25 device
Prerequisites Embedded Systems Base Course
Theory
Equipment DE2 board
Quartus II, Nios 2 IDE, SOPC Builder
Duration 9h
1 Introduction
In this laboratory, the goals are to be able to understanding the embedded sstem design flow
based on a FPGA.
In the laboratory section, a short demonstration will be made at the beginning to instruct how
to use the tools with the DE2 board.
This final demonstration of this laboratory is to be able to realize a programmable interface
for Nios2 system on DE2 board.
2 Manipulation
2.1 Design with Quartus Schematic
Follow the tutorial tut_quartus_intro_schem to implement a simple logic function on DE2.
Using Switches and Leds on DE2 board as input and output.
2.2 Design with HDL
Follow the tutorial tut_quartus_intro_verilog or tut_quartus_intro_vhdl to implement the
same logic funtion on DE2 using a hardware design language (verilog or vhdl).
2.3 SOPC Builder and SoC on FPGA
On an embedded system, the realization of a programmable interface is the base of
specialized functionality. In this series of laboratories, the goal is to be able to analyze and
realize the design of a specific programmable interface in VHDL (or Verilog) from scratch.
The part consists of the construction of a simple embedded system with a processor (softcore
NIOSII), a memory (on chip SRAM) and some programmable interfaces provided by a
library of IP components.
We need to understand:
The relation between a bus (here the Avalon bus) and a programmable interfaceconnected to this bus.
The model of the programmable interface by the processor point of view. This is a
register view.
What has to be done in the interface when the processor accesses a certain addressand how the module reacts.
How to translate the characteristic of the interface in VHDL (Verilog).
How to implement that (entity/architecture).
How to integrate it in the full system.
To realize practically the system, we are using the DE2 board.
2.3.1 Simple Nios II Design
To start, we create a directory for the project.
Do NOT use SPACE in directory name and filename.
In Quartus II:
Create a Project and select a FPGA EP2C35F672C6
Open a schematic design file and save it (.bdf file)
Create a system NIOSII with SOPC Builder
Select the following components from the provided libraries:
o NIOS II /s processor, with 4k byte instruction cache
o Add on-chip memory SRAM, 32 kbytes with 32 bits width
o Add epcs controller
o Jtag interface: JTAG UART for debug purpose
o Parallel port In 8 bits
o Parallel port Out 8 bits
o Save
o Generate in VHDL (Verilog)
o Exit
What are the addresses of your different elements ?
2.3.2 Quartus II Design
The SOPC symbol has to be added to the schematic. Add Input and Output pins for Clk,
Reset and Input (Switch0) / Output (Switch1) parallel ports. Add pins number by the way of
the .cvs file.
What pins are you using for your design Clk? Which pins do you connected for parallel ports
In/Out?
Compile the design and correct the errors.
Connect the DE2 board on USB.
Download the .sof generated you are programming the hardware FPGA
Open again the NIOSII System (doube-click on the symbol)
Select NIOS IDE you will go to the Eclipse project manager.
2.3.3 NIOS II IDE
Create a Working Space in your account, but NOT in the project directly.
Create a “Hello World” project and try it. Select the small version!!
Search for IORD() and IOWR() functions on the library generated (search for a io.h file).
Search the system.h file and try to find the equivalence with the information provided in
SOPC Builder.
Modify your program for Reading the Switches and Writing the value to the LedR (as
Output) and loop. Try your program and debug It step by step with Eclipse.
How do you create the library?
How do you compile your project for debugging?
How do you specify the memory used for your program?
How your program is downloaded on the board?
2.4 Specific Programmable Interface
In this part, we have to design a specific parallel programmable interface module in VHDL
(Verilog). This module is on the Avalon bus in register mode, 8 bits width.
The designed interface has to be included in a NIOSII system, and tested with a small C
program.
2.4.1 Programmable Interface Specification
The Parallel Port to design has the following characteristics:
8 bits width
Programmable direction for each individual bit through a Data Direction Register
A direct Write/Read access to the Parallel Port Register
A Pin Register to read data at the pin level
A write access to specify selected bits to be modify as „1‟, and no change for the other
unselected bits. The selected bits are those when a „1‟ is write at the bit position, the
bits with a „0‟ are not modified. The Parallel Port Register is modified by this access.
Same as previous access but for putting a „0‟. A write with a „1‟ will modify the port
with a „0‟. The bits with a „0‟ writing are not changed.
What is the register map for your interface?
How many wait states you need for your design on the Avalon bus?
Create a new project to realize your programmable interface and simulate the read and
write accesses in Quartus using the simulator Tools and the waveform editor.
2.4.2 Nios II Design
On the simple NIOS II design with the following components, add your parallel port design.
For this function, you need to create your own library component.
On SOPC Builder Create new component and provide the needed information. Generate
the IP. Now it can be used as all the others components.
Select NIOS II /s processor, with 4k bytes instruction cache
Add SRAM 16kbytes with 32 bits width
Add epcs controller
Jtag interface
Your Parallel port 8 bits (ParPort0)
Your Parallel port 8 bits (ParPort1)
Save
Generate in VHDL (Verilog)
Exit
What are the addresses of your Parallel ports components?
2.4.3 Quartus Design
The SOPC symbol is added to the schematic.
Add pins for Clk, Reset and ParPort0 (SW[7..0]) / ParPort1 (LEDR[7..0]) parallel ports
Add pins number (search on the web site), they are the same as the previous laboratory.
Compile the design and correct the errors.
Connect the DE2 board on USB.
Download the .sof generated you are programming the hardware FPGA
Open again the NIOSII System (double-click on the symbol)
Select NIOS IDE you will go to the Eclipse project manager
2.4.4 NIOS IDE
Create a Working Space in your directory, but NOT in the project directly or use a previous
one.
Program a InitPort() Function to select ParPor0 as input and ParPor1 as Output.
Make a simple loop for Reading ParPort0 and copying on the ParPort1.
What is in your InitPort() function?
How do you make your copy loop?
Write a small program on NIOS IDE to implement a led river with your parallel port.
Good luck!