Philadelphia University

Department of Computer Engineering

Laboratory ExperimentEng. Hassan S. O. Migdadi

http://www.philadelphia.edu.jo/academics/hmigdadi/

TITLE: Computer Aided Design and Simulation of Digital Circuits

MODULE: Computer Design Laboratory (0630430)

REFERENCE: Exp 00~05 .

LEVEL: 1

SEMESTER: 1, 2013/2014

Objectives

1) To utilise a modern state of the art CAD system employing a variety of digital design entry methods.

2) To appreciate the importance of simulating digital circuits prior to fabrication in order to first identify and then eliminate critical timing problems.

3) To understand the operational principles of a variety of digital components based on combinatorial and synchronous logic and to see how the formal methods of circuit description encountered in lectures are used in practice.

4) To become familiar with the hierarchical approach to designing complex digital systems.

IMPORTANT

This is an open-ended double experiment which will require two laboratory sessions to complete. You should do as much as you can during the first session and pick up from where you left off at the start of the second session.

Pay attention to section 1.2 overleaf on “Marked activities and assessment”. You need to keep a record of your work. You can use a book and make hard copies, but that will mean you need to print out results and paste them in your book. It is probably easier to keep a word document as a record: you can paste electronically into this – simulation results, graphical and text circuit designs, etc.

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SECTION 1 INTRODUCTION

The design exercises described in this script will take up two laboratory sessions and can thus be regarded as open ended. In the practical classes you will first study some of the basic digital components which incorporate purely combinatorial logic as taught at the beginning of the Digital Electronics 1 lecture course. Two synchronous designs have also been included to provide valuable experience of circuits built around clocked flip flops. The main practical activity will centre on learning how to use a powerful CAD package for design capture and simulation. The software you will use is called Quartus II and is currently one of the most commonly used CAD packages for research, design prototyping, commercial design and circuit manufacture. The complete package is very large and sophisticated but in this laboratory session the emphasis will be on familiarisation with the CAD tools through the design of 6 different components.

Quartus II is probably the most flexible package which electronic engineers can employ for designing digital systems, since it is possible to enter designs as text (hardware description language) or circuit diagrams (schematic capture) and in addition an engineer can construct a desired circuit either from basic gates (AND, OR, NOT etc.) or from higher-level components (decoders, multiplexers, adders, etc.) held in libraries. In the design exercises described later in this script you will gain experience of all these different ways of creating working circuits and you will also learn how to simulate each design to ensure that it functions correctly before committing it to silicon as an integrated circuit. Although the use of Quartus II would normally lead to an implementation in the form of an ALTERA programmable logic device (PLD) or Field Programmable Gate Array (FPGA), the software is portable to other forms of hardware realisation.

1.1 Getting started

You must create a directory as described in the appendix that accompanies this document, telling you how to carry out the various tasks. Into this directory you must copy three files from http://www.philadelphia.edu.jo/academics/hmigdadi/:instructions are given the read_me.txt file, which is in the directory called “Computer Lab material”.

1.2 Marked activities and assessment

The assessment will be mainly (80%) based on how well you tackle the 14 tasks (some of which are very straightforward) clearly defined in the body of this script. To receive full marks you will need to complete all of these tasks but remember that two scheduled sessions have been allocated to the design work. Most of the designated tasks involve completing specified designs and simulations but a few will require you to measure time delays. About 20% of the assessment will come from the quality of your record of what you did, what results (including designs) you obtained and what conclusions you were able to draw from the experiments carried out. You will be able to get electronic figures (or print-outs) of designs and simulation results during the session and these should be included in your record. When writing conclusions, remember to include the important things you have learned along the way and what you have achieved as measured by successfully carrying out the identified tasks.

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SECTION 2 DESIGNING AND SIMULATING A SMALL MULTIPLEXER

2.1 Designing a 4 - 1 multiplexer using schematic capture

In general a multiplexer (or MUX for short) contains a number (x) of select lines, a number (2 x) input (or data) lines and 1 output line. The binary value (0 or 1) on the output line will at any time equal the value (0 or 1) on the particular input line selected by the particular combination of the values (0s and 1s) on the select lines. In this first design exercise the Quartus II design package will be used to create a graphics design file (.bdf) representation of the 4 - 1 multiplexer circuit illustrated in Figure 1. Here s0 and s1 are the two select signals, d[3..0] are the four data input signals and f is the output signal.

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Figure 1: Graphics Design of the 4-1 Multiplexer

Task 1: Write down the Boolean equation for output signal f for the multiplexer circuit in SOP form.

Task 2: Create the .bdf file for the 4 - 1 multiplexer circuit using the step by step instruction manual appearing in the appendix to this script: record your design.

2.2 Simulating the 4 - 1 multiplexer design

In order to check that your 4 - 1 MUX design functions correctly, it is necessary to use the simulation tools available in Quartus II. Essentially, simulation in this case requires the user to construct a simulation file (.vwf) containing an appropriate pattern of input data signals and select signals such as that shown in Figure 2.

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Figure 2: Appropriate input .vwf file for 4-1 MUX

Task 3: Simulate the 4 - 1 multiplexer using the step by step instructions listed in the appendix, confirm that output f switches properly in response to changes in the select signals s0 and s1, then include the simulation waveforms in your log book. Measure the time taken for output f to switch following a change in the select signals and record this propagation delay time also.

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SECTION 3 DESIGNING AND SIMULATING A LARGE MULTIPLEXER

3.1 Designing a 27 - 9 multiplexer using text (hardware description language) entry

In the second year of your course you will be designing a fairly complex digital system which incorporates a 27 - 9 multiplexer as one of its building blocks. This 27 - 9 multiplexer can be regarded as nine 4 - 1 multiplexers, each operating on 1 bit out of the 9 bits making up a signal bus. The aim of the next exercise in this laboratory session will be to design this component by means of text entry using AHDL (ALTERA Hardware Description Language) rather than schematic capture. Text entry quite often offers significant time saving compared with schematic capture and it is therefore important to be aware of its virtues in digital electronics design. The 27 - 9 multiplexer you will be designing can be represented in symbol form as illustrated in Figure 3. The multiplexer has two select signals s[1..0] to control which one of the three input 9-bit buses als9bit[8..0], ams9bit[17..9] and count[8..0] is switched at any given time to the output 9-bit bus addr[8..0]. The two 9-bit buses als9bit[8..0] and ams9bit[17..9] are the least significant 9 bits and most significant 9 bits respectively of an 18-bit input address bus but the splitting with different names has been done to help in sorting out the simulation results which you will obtain later. Quartus II deals with buses in exactly the same way as in this script e.g. addr[8..0] is the AHDL syntax for the group of 9 signals addr8, addr7, addr6, addr5, addr4, addr3, addr2, addr1 and addr0.

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9

9

9

9

als9bit[8..0]

ams9bit[17..9]

count[8..0]

s[1..0]

addr[8..0]

Figure 3: Symbolic representation of 27-9 MUX

There are several ways of creating a multiplexer using AHDL but the simplest is to use chained IF.... THEN....ELSIF statements. For example the following partially complete AHDL source code

IF s[1..0] == 0 THEN addr[8..0] = als9bit[8..0];

ELSIF s[1..0] == 1 THEN addr[8..0] = etc

END IF;

will switch input bus als9bit[8..0] to output bus addr[8..0] if both s0 and s1 are logic low and implement other switching operations if the select signals have different values. In practice you will need to prepare a complete text description file (.tdf) to represent your design and to do this you should follow the detailed instructions in the step by step manual in the appendix.

Task 4: Design the 27 - 9 multiplexer circuit using the mux27_9.tdf template file (copied from http://www.philadelphia.edu.jo/academics/hmigdadi/) and the step by step instructions in the appendix to this script. Remember to save your design when you have simulated it and are sure that it is correct.

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3.2 Simulating the 27 - 9 multiplexer

Essentially, simulation in this case requires the user to construct a simulation file (.vwf) containing an appropriate pattern of input group values and select signals such as that shown in Figure 4. Details on how to achieve this can be found in the appendix.

Figure 4: Appropriate input mux27_9.vwf file for 27-9 MUX

Task 5: Simulate the 27 - 9 multiplexer, confirm that the output switches properly in response to changes in the select signals s0 and s1, then include the simulation waveforms in your log book. Measure the time it takes the output signal addr[8..0] to switch following a change in the select signals and record this propagation delay time in your log book.

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SECTION 4 DESIGNING AND SIMULATING A DECODER

4.1 Designing a 3 line to 8 line decoder using AHDL truth table entry

In general a decoder (or demultiplexer) contains a number (x) of select lines, a number (2 x) of output lines and 1 enable line. Provided the enable line is asserted, one only of the output lines will be selected by the particular combination of the binary values (0s and 1s) on the select lines and asserted either high or low. In this decoder design exercise the Quartus II design package will be used to create the 3 line to 8 decoder illustrated symbolically in Figure 5. Here s[2..0] are the three select signals, y[7..0] are the eight output signals and e is the enable signal. The presence of small circles on the lines connecting the 8 output signals and the enable signal to the body of the symbol is the convention used to indicate that these signals employ active low assertion. This means that when e = 0 the output line selected by the values existing on s[2..0] will be driven low with the other 7 outputs being held at logic high. When e = 1 the decoder will not be enabled and all 8 outputs will be de-asserted, i.e. will be held at logic high.

s[2..0]

y[7..0]8

e

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Figure 5: Symbolic representation of 3 line to 8 line decoder

There are several ways of creating a decoder using AHDL but the simplest is to use truth table entry. Essentially all the user has to do is to enter the design exactly in the form of a truth table representation of the functionality of the component. For example the following partially complete AHDL source code will be the first few lines of the truth table entry for the required decoder.

TABLE% select , enable => outputs user friendly names %

s[2..0] , e => y[7..0]; % real signal names %

X , 1 => H”FF”; % HEX for 1111 1111 %

0 , 0 => H”FE”; % HEX for 1111 1110 %

1 , 0 => H”FD”; % HEX for 1111 1101 %

Note how the use of X to represent “don’t care” values for the select lines when the decoder is not enabled simplifies the design. As in the previous design exercise you will need to prepare a complete text description file (.tdf) to represent your design and to do this you should follow the detailed instructions in the step by step manual in the appendix.

Task 6: Design the 3 line to 8 line decoder circuit (include this in your log book) using the dec3_8.tdf template file and the step by step instructions in the appendix to this script.

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4.2 Simulating the 3 line to 8 line decoder

Essentially, simulation in this case requires the user to construct a simulation file (.vwf) containing an appropriate pattern of enable and select signals such as that shown in Figure 6. Details on how to achieve this can be found in the appendix to this script.

Figure 6: Appropriate .vwf file of the 3 line to 8 line decoder

Task 7: Simulate the 3 line to 8 line decoder, confirm that the output switches properly in response to changes in the select signals s0, s1 and s2 then save the simulation waveforms in your log book. Measure the time it takes for one of the output signals in the group y[7..0] to switch following a change in the select signals and record this propagation delay time in your log book.

4.3 Creating a 3 line to 8 line decoder using the ALTERA macrofunction (mf) libraries

The decoder you designed as Task 7 is actually very close in functionality to a discrete IC called the 74138 which is available from electronic component suppliers such as RS, Farnell and Maplin. ALTERA actually include many of the 74-series discrete IC designs as graphics design files which the user can access simply by opening a bdf drawing window then double clicking anywhere in it to gain access to the libraries. You will find (under others) the list of available macrofunctions which includes the 74138 version of the 3 line to 8 line decoder. You should bring a symbol for it into the drawing area and examine its internal structure by double clicking anywhere inside it. Inspect this circuit schematic and attempt to understand how the designer of this 74138 component has used a variety of gates to deal with the group of active low outputs and the group of three select lines. Obviously, the availability of macrofunctions to the designer can speed up the design process in some cases although this largely depends on whether the macrofunction component does exactly what is required.

Task 8: Describe in a sentence or two the main features of the logic contained in the schematic of the 74138.

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SECTION 5 DESIGNING AND SIMULATING A MAGNITUDE COMPARATOR

5.1 Designing an 8-bit magnitude comparator using AHDL

In general terms a magnitude comparator contains two n-bit input buses P[n-1..0] and Q[n-1..0] and two output signals P = Q and P > Q. Whenever the group values of P and Q are exactly equal, the output P = Q will be asserted whereas the P > Q output signal will be asserted whenever the group value of P is greater than Q. In this design exercise the Quartus II design package will be used to create the 8-bit magnitude comparator illustrated symbolically in Figure 7. Here p[7..0] and q[7..0] are the two buses to be compared and p_eq_q and p_gt_q are the required outputs, both of which are to be asserted active low as indicated by the small circles. The simplest way to design this component is to use IF .... THEN .... ELSIF statements as adopted in the design of the multiplexer described earlier. This AHDL design will be largely left for you to create by building on what you have learned previously but some helpful suggestions are included in the appendix.

p[7..0]8

p_eq_q

p_gt_qq[7..0]8

Figure 7: Symbolic representation of an 8-bit magnitude comparator

Task 9: Design the 8-bit magnitude comparator circuit using with the magcomp8.tdf template file as a starting point: record this in your log book.

5.2 Simulating the 8-bit magnitude comparator

Essentially, simulation in this case requires the user to construct a simulation file (.vwf) containing three different choices of group values for p[7..0] and q[7..0], one choice having them equal, one having p[7..0] > q[7..0] and the other having p[7..0] < q[7..0]. You will be expected to construct an appropriate magcomp8.vwf file based on what you have learned from the previous exercises.

Task 10: Simulate the 8-bit magnitude comparator, confirm that both outputs p_eq_q and p_gt_q switch properly in response to an appropriate pattern of input group values, then record the simulation waveforms in your log book. Measure and record the time it takes the output signals to switch following a change in the input group pattern.

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SECTION 6 DESIGNING AND SIMULATING A SIPO SHIFT REGISTER

Shift registers are a very important class of digital components which fall into a category called synchronous. Synchronous components differ from the combinatorial components studied earlier in this set of laboratory design exercises in that they require a clock signal, to the rising edge of which, all the outputs of the synchronous component are synchronised. All shift registers contain D-type flip flops. The family of shift registers is quite broad but the main types are:

PIPO Parallel In Parallel Out Used to store and output n-bit parallel data which is input on n input pins.

SIPO Serial In Parallel Out Used to convert serial data entering on 1 input pin to parallel stored data.

PISO Parallel In Serial Out Used to convert parallel stored data to serial data clocked out on 1 output pin.

FIFO First In First Out Used to store clocked input serial data prior to clocking it out in serial form.

In the following two design exercises a SIPO and a combined PIPO / SIPO shift register will be implemented and simulated.

6.1 Designing a basic 4-bit SIPO shift register using schematic capture

The main purpose of a 4-bit SIPO shift register, where SIPO stands for Serial In Parallel Out, is to convert an input serial data stream, organised as a group of 4 data bits (nibble) which are presented sequentially on 4 rising clock edges to the input pin of the SIPO, into the equivalent 4-bit parallel value after the 4th clock cycle is completed. You should now be very familiar with using the Quartus II design package to create digital designs either as graphics design file (.bdf) representations (schematic capture) or as text description files (.tdf). Schematic capture will be employed in this design of a 4-bit PISO for which an appropriate circuit diagram is illustrated in Figure 8.

Figure 8: Schematic diagram of 4-bit SIPO shift register

In this diagram the serial data bits are clocked in sequentially (most significant bit first) via the serial_in input pin and, after 4 clock cycles have been completed, the 4 flip flops will hold and be able to output the parallel version of the input serial data. The four components labelled DFF are identical D-type flip flops, each of which is triggered by the common clock signal which has been brought out as the external input signal clock in Figure 8. What a D-type flip flop does is to cause whatever signal level is on its D input pin to appear on its Q-output pin very shortly after the rising edge of the clock signal which triggers the transfer. Each DFF symbol held in the Altera primitives library contains two other pins, namely CLRN and PRN. The first of these is an active-low clear signal which sets the D-type’s Q output to logic low, irrespective of what is on its

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D pin, as soon as CLRN goes logic low. In Figure 8 you can see that the CLRN pins of all the flip flops are tied together and brought out as an external input signal called reset, so that all flip flops can be cleared together if required. The PRN pin is an active low preset signal which can be used to set the Q-output of the DFF component to logic high, irrespective of what is on its D pin, when PRN goes low. In this particular application there is no need to preset the flip flops so the PRN pins have all been tied together and connected to a VCC (logic high) symbol which will disable the preset facility.

The SIPO shift register shown in Figure 8 works by shifting each bit stored in a flip flop to the next flip flop on the right every time a rising clock edge occurs, unless the reset signal is logic low. If reset is held logic high, the input signal present on the serial_in pin gets transferred to the output of the first (left-most) flip flop on each rising clock edge whereas the value on the last (right-most) flip flop in the chain is lost on each rising clock edge.

Task 11: Create the sipo.bdf file for the basic 4-bit SIPO circuit and include your design in your electronic record or log book.

6.2 Simulating the basic SIPO design

In order to check that your 4-bit SIPO design functions correctly, use the simulation tools. Simulation in this case requires the user to construct a simulation file (.vwf) containing an appropriate pattern of input data signals and control signals such as that shown in Figure 9. There are a few important things to observe about the input waveforms employed in this simulation. First, note that the times at which input signals are, with one exception, chosen to change value are synchronised to the falling edge of the clock signal. This is a feature shared by all synchronous sequential systems. It is called two-phase clocking and the reason for choosing it is to ensure that the value appearing on each D-input of a D-type flip flop is stable when the rising clock edge appears, in order to avoid set-up and hold problems which can cause a flip flop to exhibit indeterminate behaviour. In order to illustrate this sort of problem behaviour, the reset signal has been deliberately set to change exactly on a rising clock edge at time 950 ns. The second thing to note is that the reset signal has been set logic low for the first clock cycle which will clear all the flip flop outputs to logic low. It is always a good idea to force a synchronous system such as this SIPO into a known initial state (usually the reset condition as here) before investigating how it responds to real input signal values. Finally, note that the particular 4-bit serial input sequences chosen for this simulation are 1 0 1 1 followed immediately by 0 1 0 1.

Figure 9:Appropriate sipo.vwf file for the 4-bit SIPO shift register

Task 12: Simulate the basic 4-bit SIPO: make sure you test all the functions. Confirm that four clock cycles after reset goes logic high the four flip flops hold the parallel version of the serial input nibble (4 bits) and that after a further four clock cycles the flip flops hold the parallel version of the second serially input nibble. Include the simulation results in your record. Measure the time taken for one of the flip flop outputs to change relative to the preceding rising clock edge and record this D-type propagation delay also. Observe what happens to the flip flop outputs immediately after the reset signal goes logic low and comment on your observations.

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SECTION 7 DESIGNING AND SIMULATING A MULTIFUNCTION SHIFT REGISTER

7.1 Designing a 4-bit multifunction shift register mf_shift_reg using schematic capture

In this last design exercise schematic capture will be employed to design a multifunction shift register which can be used either as a PIPO or a shift left SIPO or a shift right SIPO. The actual circuit diagram for the 4-bit multifunction shift register is illustrated in Figure 10. In this diagram there are four identical mux4_1 multiplexers which are exactly the same as the components you designed in Section 2 of this laboratory script. The purpose of each mux4_1 unit is to switch one of its four input signals to its single output depending on the signal levels appearing on the two common select lines which are brought out as external input signals sel1 and sel0.

The four external input pins labelled parallel_in0 to parallel_in3 shown on the left of Figure 10 represent the four parallel input signals which, depending on the values on sel1 and sel0, could be loaded into and stored in the four flip flops on the following rising clock edge. Following a short DFF propagation delay relative to the rising clock edge, these values would be available on the four parallel output pins q0, q1, q2, q3. This mode of operation is precisely that of a PIPO storage register.

The input pin labelled serial_right can, if sel1 and sel0 have appropriate values, be used to input four separate input data bits over four separate clock cycles, each bit being first stored in the uppermost (left-most) q0 flip flop before being shifted right to the next flip flop on each successive clock edge. After four clock cycles the four flip flops will hold and be able to output a parallel version of the input serial sequence. This mode of operation is exactly the same as the SIPO shift register you designed in Section 6.

The input pin labelled serial_left can be used in exactly the same way as serial_right except that the sel1 and sel0 signals would be chosen to load the serial bits first into the q3 flip flop and shift the bits to the left i.e. from DFF3 to DFF2 to DFF1 to DFF0 on four successive clock cycles. This mode of operation is that of a SIPO left shifting shift register. Left shift registers can be used in digital systems to perform integer multiplication by a factor of 2 per shift whereas right shift registers can perform integer divide operations by a factor of 2 per shift. The following table shows the four modes of operation of the multifunction shift register for the four combinations of the select sel1 and sel0 input signal values.

se11

sel0

serial_right

serial_left

parallel_in[3..0]

q[3..0] operation

0 0 X X X q[3..0] hold previous values

0 1 X X PI[3..0] PI[3..0] parallel data load1 0 I3 I2 I1 I0 X X I3 I2 I1 I0 shift data to right1 1 X I3 I2 I1 I0 X I0 I1 I2 I3 shift data to left

You should now be able to understand how the circuit shown in Figure 10 functions but if you can’t consult a demonstrator.

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Figure 10: Schematic for the multifunction shift register design

Task 13: Create the mf_shift_reg.bdf schematic for the multifunction shift register circuit shown in Figure 10 using the step by step instruction manual appearing in the appendix to this script. Record this in your log book.

7.2 Simulating the multifunction shift register design

As with the previous designs, simulation requires the user to construct a simulation file (.vwf) containing an appropriate pattern of input data signals and control signals. An appropriate set of input stimuli for this design is shown in Figure 11. All the points that were made for the simulation of the SIPO shift register, namely two phase clocking and initialising the flip flops to the reset condition apply to this multifunction shift register In this example note that the input pattern on the parallel_in lines is 1 0 1 1 whereas that fed to the serial_right input pin is 1 0 0 1 and that fed to the serial_left input pin is 0 1 1 1.

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Figure 11: Appropriate .vwf file for simulating the multifunction shift register design

Task 14: Simulate the multifunction shift register using the step by step instructions listed in the appendix and record your simulation results in your log book. Interpret the behaviour of the shift register, and explain this in your record.

END OF PROCEDURE FOR DOUBLE EXPERIMENT 06~08

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