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Decisions Behind the Design: LabVIEW for CompactRIO Sample Projects. Meghan Kerry Embedded Software Product Manager Certified LabVIEW Developer (CLD). Agenda. Keys to quality in a software architecture Software architecture overview I/O safe states Watchdog timers Message communication - PowerPoint PPT Presentation
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Decisions Behind the Design: LabVIEW for CompactRIO
Sample ProjectsMeghan Kerry
Embedded Software Product ManagerCertified LabVIEW Developer (CLD)
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Agenda
• Keys to quality in a software architecture• Software architecture overview• I/O safe states• Watchdog timers• Message communication• Error handling • System monitoring
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Keys to Quality in a Software Architecture
• Define software architecture and identify architecture components
• Create an architectural diagram• Consider key components such as data communication, error handling, etc.
• Learn the foundational design patterns• Create new design patterns as required by your application (requires experience)
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Data Communication Diagram
• Documents foundational components:• Processes (loops)• Data communication paths• Type of data transfer
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Data Communication Types
Tag Latest value data
Messages/Commands Intermittent data, low latency
Stream Continuous acquisition, high throughput
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Typical CompactRIO System Diagram
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LabVIEW for CompactRIO Sample Projects• Pre-built architectures for embedded control and monitoring applications
• Designed to ensure quality and scalability of a system
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Basic FPGA Diagram
Performs deterministic and/or high speed control
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State Machine for Hardware I/O and Control
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Failure Conditions that Initiate Safe States
• Examples (from Fail Safe Reference Design):
• RT Safe – indicates the RT system is ready
• Emergency Safe – tied to an emergency shut-off switch
• Watchdog Safe – monitors the Real-Time system
• Control Inputs Valid – monitors the inputs to the control algorithm
• Based on system requirements
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Basic FPGA Diagram
Detects software failures
Recovers from software failures
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Watchdogs
• A watchdog timer is a hardware counter that interfaces with the embedded software application to detect and recover from software failures
• A user can then:• Reboot real-time target automatically• Perform user-defined recovery actions
• Two types of watchdogs with NI Real-Time hardware:
• LabVIEW Real-Time Watchdog • Real-Time <-> FPGA Watchdog (FPGA Fail Safe Design)
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LabVIEW Real-Time Only Watchdog
• Uses hardware timer built into CompactRIO hardware
• “Reset = True” reboots system if the watchdog process is starved
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LabVIEW Real-Time Watchdog
• Enable occurrence in expiration actions• Configure appropriate watchdog timeout and Watchdog Whack loop period
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Real-Time <-> FPGA WatchdogReset timer
Put control loop into a safe state, and reset system
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Real-Time <-> FPGA Watchdog
• Pet the watchdog at a user-defined watchdog pet rate
• This resets the counter implemented in the FPGA VI
See Fail-Safe Control Reference Design whitepaper
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Basic FPGA Diagram - Summary
Detects software failures
Recovers from software failures
Performs deterministic and/or high speed control
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Basic Real-Time Processor Diagram
Periodically communicates
tags
Communicates messages with
clientSends messages to other processes or
targets
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Constructing a Message
Examples
DataVariant allows data-type to vary. Different messages may require different data
CommandString constant allows user to specify message
Command Data
Update Control Configuration
Cluster containing configuration data
Update FPGA State Enum
Update PID Setpoints Array of numerics
Send Error to UI Error cluster
Exit -
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Queued Message Handler API
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Queued Message Handler Framework
Message handling loop
Watchdog Loop
Monitoring Loop
Command ParserQueued Message Handler Setup
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Queued Message Handler Framework
Watchdog Loop
Monitoring Loop
Command ParserOne or more messages handled per case
Communicate messages between processes or targets
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Basic Real-Time Processor Diagram
Handles all error messages from
FPGA and RT target
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Error Messages
• Specific Error Handling• Code called in specific
locations to respond with an action to specific error codes
• Possible actions are retry, ignore, correct
• Central Error Handling• High-level code that checks
for errors in an entire system• Responds to classes of errors
rather than specific codes• Uses the classification to
determine which actions to take
QueueCentral Handler
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Central Error Handling Framework
UI message handling loop
Watchdog Loop
Monitoring Loop
Command Receiver Loop
Specific Handler
Specific Handler
Specific Handler
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Central Error Handling Framework
Watchdog Loop
Monitoring Loop
Command Receiver Loop
Specific Handler
Specific Handler
Specific Handler
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Central Error Handling Framework
Get next error based on priority
Return classification of error
Handle classified errors (update FPGA state and/or reboot system)
Log and send all errors to UI
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Basic Real-Time Processor Diagram
Communicates messages with
client
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Sending Commands Across the Network
• Network Streams are great for commands because are they are lossless
• Tips:• Use Flush with zero timeout to minimize latency• Add code to handle UI disconnections (see Sample
Project)
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System Monitoring
Disk Space RAM CPU Bandwidth
EFF
EC
T
Lost Data Crash Starvation
Embedded processors have limited….
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System Monitoring
Current value data can be sent to UI with Shared Variables
Monitor CPU usage per coreExecute loop
periodically
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Network Published Shared Variables
• When to use the Static API:• Small number of variables (less than a dozen)
• When to use the Programmatic API:• Iterate through a large number of variables• Dynamically change the IP address of the cRIO from the
client (client side only)
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Basic Real-Time Processor Diagram
Periodically communicates
tags
Communicates messages with
clientSends messages to other processes or
targets
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Basic HMI Diagram
Generates UI Events using the Event Structure
Processes UI Events and communicates messages with real-time system
Periodically updates UI
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Common Variant Architectures
• Other LabVIEW for CompactRIO Sample Projects• LabVIEW FPGA Control • LabVIEW FPGA Control with Real-Time Sequencer Engine • LabVIEW Real-Time Control (RIO Scan Interface) • LabVIEW FPGA Waveform Acquisition and Logging• LabVIEW Data Logging and Supervisory Control
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FPGA Control with Sequencer Sample Project
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Real-Time Control Sample Project
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FPGA Waveform Acquisition and Logging
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Demo – LabVIEW FPGA Control Sample Project
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LabVIEW for CompactRIO Sample Projects• Available in LabVIEW 2012 and later• Find more best practices at ni.com/compactriodevguide