Definition of g using transfer characteristic.site.iugaza.edu.ps/jtaha/files/2011/01/chapter-8-small...Robert L. Boylestad Title Fig. 8.1 Author James Ramsey Created Date 1/26/2011

Fig. 8.1 Definition of gm using transfer characteristic.

Robert L. Boylestad

Electronic Devices and Circuit Theory, 9e

Copyright ©2006 by Pearson Education, Inc.

Upper Saddle River, New Jersey 07458

All rights reserved.

Fig. 8.2 Calculating gm at various bias points.

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Fig. 8.3 Plot of gm versus VGS.

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Fig. 8.4 Plot of gm versus VGS for a JFET with IDSS = 8 mA and VP = -4 V.

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Fig. 8.5 Plot of gm versus ID for a JFET with IDSS = 8 mA and VGS = -4 V.

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Fig. 8.6 Definition of rd using FET drain characteristics.

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Fig. 8.7 Drain characteristics used to calculate rd in Example 8.5.

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Fig. 8.8 FET ac equivalent circuit.

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Fig. 8.9 FET ac equivalent model for Example 8.6.

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Fig. 8.10 JFET fixed-bias configuration.

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Fig. 8.11 Substituting the JFET ac equivalent circuit unit into the network of Fig. 8.10.

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Fig. 8.12 Redrawn network of Fig. 8.11.

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Fig. 8.13 Determining Zo.

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Fig. 8.14 JFET configuration for Example 8.7.

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Fig. 8.15 Self-bias JFET configuration.

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Fig. 8.16 Network of Fig. 8.15 following the substitution of the JFET ac equivalent circuit.

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Fig. 8.18 Self-bias JFET configuration including the effects of RS with rd = ∞ Ω.

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Fig. 8.19 Including the effects of rd in the self-bias JFET configuration.

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Fig. 8.20 Network for Example 8.8.

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Fig. 8.21 Parameters and equations for Example 8.8 using Mathcad.

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Fig. 8.22 JFET voltage-divider configuration.

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Fig. 8.23 Network of Fig. 8.22 under ac conditions.

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Fig. 8.25 JFET source-follower configuration.

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Fig. 8.26 Network of Fig. 8.25 following the substitution of the JFET ac equivalent model.

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Fig. 8.27 Network of Fig. 8.26 redrawn.

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Fig. 8.28 Determining Zo for the network of Fig. 8.25.

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Fig. 8.29 Network to be analyzed in Example 8.9.

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Fig. 8.30 JFET common-gate configuration.

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Fig. 8.31 Network of Fig. 8.30 following substitution of JFET ac equivalent model.

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Fig. 8.32 Determining Z'i for the network of Fig. 8.30.

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Fig. 8.34 D-MOSFET ac equivalent model.

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Fig. 8.36 AC equivalent circuit for Fig. 8.35.

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Fig. 8.37 Enhancement MOSFET ac small-signal model.

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Fig. 8.38 E-MOSFET drain-feedback configuration.

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Fig. 8.39 AC equivalent of the network of Fig. 8.38.

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Fig. 8.40 Determining Zo for the network of Fig. 8.38.

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Fig. 8.41 Drain-feedback amplifier from Example 8.11.

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Fig. 8.42 E-MOSFET voltage-divider configuration.

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Fig. 8.43 AC equivalent network for the configuration of Fig. 8.42.

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Fig. 8.44 Circuit for desired voltage gain in Example 8.13.

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Fig. 8.45 Network for desired voltage gain in Example 8.14.

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Fig. 8.46 JFET amplifier with Rsig and RL.

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Fig. 8.47 Network of Fig. 8.46 following the substitution of the ac equivalent circuit for the JFET.

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Fig. 8.48 Cascaded FET amplifier.

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Fig. 8.49 Cascade amplifier circuit for Example 8.16.

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Fig. 8.50 Cascaded JFET-BJT amplifier for Example 8.17.

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Fig. 8.51 Basic components of a three-channel JFET audio mixer.

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Fig. 8.52 (a) Application of a high- and a low-impedance source to the mixer of Fig. 8.51; (b) reduced equivalent

without the 100-kΩ isolation resistors; (c) reduced equivalent with the 100-kΩ resistors.

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Fig. 8.53 Demonstrating that for parallel signals, the channel with the least internal impedance and most power

controls the situation.

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Fig. 8.54 Battery-powered (9-V), two-station intercom: (a) external appearance; (b) internal construction.

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Fig. 8.55 Noise development due to mechanical switching.

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Fig. 8.56 Silent switching audio network: (a) JFET configuration; (b) with both signals present; (c) with one signal

on.

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Fig. 8.56 (continued) Silent switching audio network: (a) JFET configuration; (b) with both signals present; (c) with

one signal on.

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Fig. 8.56 (continued) Silent switching audio network: (a) JFET configuration; (b) with both signals present; (c) with

one signal on.

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Fig. 8.57 Specification sheet for a low-cost analog JFET current switch. (Copyright of Semiconductor Components

Industries, LLC. Used by permission.)

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Fig. 8.58 Phase-shift networks: (a) advance; (b) retard.

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Fig. 8.59 RC phase-advance network.

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Fig. 8.60 Passive infrared (PIR) motion-detection system.

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Fig. 8.61 Commercially available PIR motion-detection unit: (a) external appearance; (b) internal construction; (c) pet

option coverage.

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Fig. 8.61 (continued) Commercially available PIR motion-detection unit: (a) external appearance; (b) internal

construction; (c) pet option coverage.

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Fig. 8.62 Fixed-bias JFET configuration with an ac source.

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Fig. 8.63 Output file for the network of Fig. 8.62.

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Fig. 8.64 JFET voltage-divider configuration with an ac source.

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Fig. 8.65 The ac drain and gate voltage for the voltage-divider JFET configuration of Fig. 8.64.

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Fig. 8.66 Design Center network for analyzing cascaded JFET amplifiers.

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Fig. 8.67 Display of resulting JFET model definition.

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Fig. 8.68 PSpice output for the network of Fig. 8.66 (edited).

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Fig. 8.69 Display showing dc bias levels.

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Fig. 8.70 JFET self-bias network using Multisim.

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Fig. 8.71 JFET transfer characteristic for Problem 11.

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Fig. 8.72 JFET drain characteristic for Problem 12.

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Fig. 8.73 Fixed-bias amplifier for Problems 17 and 18.

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Fig. 8.74 Problems 19, 21, 22 and 46.

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Fig. 8.75 Self-bias configuration for Problems 20 and 47.

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Fig. 8.76 Problems 23 to 26 and 48.

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Fig. 8.77 Problems 27 and 28.

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Fig. 8.78 Problem 29.

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Fig. 8.79 Problems 30, 31, and 49.

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Fig. 8.86 Problems 41 and 42.

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Fig. 8.93 Problems 49 to 53.

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Fig. 8.94 Problems 54 to 56.

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Definition of g using transfer characteristic.site.iugaza.edu.ps/jtaha/files/2011/01/chapter-8-small...Robert L. Boylestad Title Fig. 8.1 Author James Ramsey Created Date 1/26/2011