DEMONSTRATION on

VLSI & EMBEDDED SYSTEMS LAB

By

Dr. S. MUNI RATHNAMPROFESSOR & H.O.D

DEPT. OF E.C.E, VEMU IT CHITTOOR

Topics to be discussed

• Vision, Mission, POs, PSOs & PEOs

• Syllabus & Course Outcomes (COs)

• Over view of FPGA SPATREN3 XILLINX s/w

• Code Composer Studio (CCS)

• Major Equipment List

• Lab Physical View

• Dos & Don’t

• Safety Precautions

Vision, Mission, POs, PSOs & PEOs

Vision of the institute

To be a premier institute for professionaleducation producing dynamic and vibrantforce of technocrat with competent skills,innovative ideas and leadership qualities toserve the society with ethical and benevolentapproach.

Mission of the institute

Mission_1: To create a learning environment with state-of-the art infrastructure, well equipped laboratories, researchfacilities and qualified senior faculty to impart high qualitytechnical education.

Mission_2: To facilitate the learners to foster innovativeideas, inculcate competent research and consultancy skillsthrough Industry-Institute Interaction.

Mission_3: To develop hard work, honesty, leadershipqualities and sense of direction in rural youth by providingvalue based education.

Vision of the Department

To become a centre of excellence in the fieldof Electronics and Communication Engineeringand produce graduates with Technical Skills,Research & Consultancy Competencies, Life-long Learning and Professional Ethics to meetthe challenges of the Industry and evolvingSociety.

Mission of the Department

Mission_1: To enrich Technical Skills of studentsthrough Effective Teaching and Learning practicesfor exchange of ideas and dissemination ofknowledge.Mission_2: To enable the students with researchand consultancy skill sets through state-of-the artlaboratories, industry interaction and training oncore & multidisciplinary technologies.Mission_3: To develop and instill creativethinking, Life-long learning, leadership qualities,Professional Ethics and social responsibilitiesamong students by providing value basededucation.

Programme Educational Objectives ( PEOs)

PEO_1: To prepare the graduates to be able to plan,analyze and provide innovative ideas toinvestigate complex engineering problems of industryin the field of Electronics and CommunicationEngineering using contemporary design and simulationtools.PEO_2: To provide students with solid fundamentals in core and multidisciplinary domain for successful implementation of engineering products and also to pursue higher studies. PEO_3: To inculcate learners with professional and ethical attitude, effective communication skills, teamwork skills, and an ability to relate engineering issues to broader social context at work place.

Programme Outcome (POs)PO_1: Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and

an engineering specialization to the solution of complex engineering problems.PO_2: Problem analysis: Identify, formulate, review research literature, and analyze complex engineering

problems reaching substantiated conclusions using first principles of mathematics, natural sciences, andengineering sciences.

PO_3: Design/development of solutions: Design solutions for complex engineering problems and designsystem components or processes that meet the specified needs with appropriate consideration for thepublic health and safety, and the cultural, societal, and environmental considerations.

PO_4: Conduct investigations of complex problems: Use research-based knowledge and research methodsincluding design of experiments, analysis and interpretation of data, and synthesis of the information toprovide valid conclusions.

PO_5: Modern tool usage: Create, select, and apply appropriate techniques, resources, and modernengineering and IT tools including prediction and modeling to complex engineering activities with anunderstanding of the limitations.

PO_6: The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal,health, safety, legal and cultural issues and the consequent responsibilities relevant to the professionalengineering practice.

PO_7: Environment and sustainability: Understand the impact of the professional engineering solutions insocietal and environmental contexts, and demonstrate the knowledge of, and need for sustainabledevelopment.

PO_8: Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of theengineering practice.

PO_9: Individual and team work: Function effectively as an individual, and as a member or leader in diverseteams, and in multidisciplinary settings.

PO_10: Communication: Communicate effectively on complex engineering activities with the engineeringcommunity and with society at large, such as, being able to comprehend and write effective reports anddesign documentation, make effective presentations, and give and receive clear instructions.

PO_11: Project management and finance: Demonstrate knowledge and understanding of the engineering andmanagement principles and apply these to one’s own work, as a member and leader in a team, to manageprojects and in multidisciplinary environments.

PO_12: Life-long learning: Recognize the need for, and have the preparation and ability to engage inindependent and life-long learning in the broadest context of technological change.

Programme Specific Outcome (PSOs)

PSO_1: Higher Education: Qualify in competitiveexaminations for pursuing higher education byapplying the fundamental concepts of Electronicsand Communication Engineering domains such asAnalog & Digital Electronics, Signal Processing,Communication & Networking, EmbeddedSystems, VLSI Design and Control Systems etc..

PSO_2: Employment: Get employed in alliedindustries through their proficiency in programspecific domain knowledge, specialized softwarepackages and Computer programming or becomean entrepreneur.

Syllabus & Course Outcomes (COs)

• Course Outcomes (COs)• C417.1:Design and simulate combinational and sequential logic circuits using VHDL.• C417.2:Design and Implement combinational and sequential logic circuits in FPGA kit• C417.3:Analysis of simulation results and schematic diagram of combinational and sequential logic circuits• C417.4:Develop programs for configuration of GPIO ports using TM4C 123GH6PM microcontroller• C417.5:Design and develop programs for interface modules with TM4C 123GH6PM microcontroller• PART A: VLSI (List of Experiments)• (For Laboratory Examination-Minimum of Six Experiments)• Realization of Logic Gates.• 3- to - 8Decoder- 74138.• 8 x 1 Multiplexer-74151 and 2 x 4 De-multiplexer-74155.• 4-Bit Comparator-7485.• D Flip-Flop-7474.• Decade counter-7490.• Shift registers-7495.• ALU Design.• PART B: Embedded Systems (List of Experiments)• (For Laboratory Examination-Minimum of Six Experiments)• Learn and understand how to configure EK-TM4C123GXL Launch pad digital I/O pins. Write a C program for

configuration of GPIO ports for Input and output operation (blinking LEDs, push buttons interface).• Learn and understand Timer based interrupt programming. Write a C program for EK- TM4C123GXL Launch pad

and associated Timer ISR to toggle onboard LED using interrupt programming technique.• Configure hibernation module of the TM4C123GH6PM microcontroller to place the device in low power state

and then to wake up the device on RTC (Real- Time Clock) interrupt.• Configure in-build ADC of TM4C123GH6PM microcontroller and interface potentiometer with EK-TM4C123GXL

Launch pad to observe corresponding 12- bit digital value.

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY ANANTAPUR

IV B.Tech. I-Sem (ECE)

(15A04712) VLSI & EMBEDDED SYSTEMS LABORATORY

• Learn and understand the generation of Pulse Width Module (PWM) signal by configuring and programming the in-build PWM module of TM4C123GH6PM microcontroller.Configure the PWM and ADC modules of TM4C123GH6PM microcontroller to control the speed of a DC motor with a PWM signal based on the potentiometer output.Learn and understand to connect EK-TM4C123GXL Launch pad to PC terminal and send an echo of the data input back to the PC using UART.Learn and understand interfacing of accelerometer in Sensor Hub Booster pack with EK-TM4C123GXL Launch pad using I2C.USB bulk transfer mode: Learn and understand to transfer data using bulk transfer mode with the USB2.0 peripheral of the TM4C123GH6PM device.Learn and understand to find the angle and hypotenuse of a right angle triangle using IQ math library of Tiva Ware.Learn and understand interfacing of CC3100 WiFi module with EKTM4C123GXL Launch pad and configuration of static IP address for CC3100 booster pack.Configure CC3100 Booster Pack connected to EK-TM4C123GXL Launch pad as a Wireless Local Area Network (WLAN) Station to send Email over SMTP.Configure CC3100 Booster Pack connected to EK-TM4C123GXL Launch pad as a HTTP server.

VEMU INSTITUTE OF TECHNOLOGY::P.KOTHAKOTANEAR PAKALA, CHITTOOR-517112

(Approved by AICTE, New Delhi & Affiliated to JNTUA, Anantapuramu)Department of Electronics &Communication Engineering

LIST OF EXPERIMENTS TO BE CONDUCTED

• PART A: VLSI (List of Experiments)

• Realization of Logic Gates.

• 3- to - 8Decoder- 74138.

• 8 x 1 Multiplexer-74151 and 2 x 4 De-multiplexer-74155.

• 4-Bit Comparator-7485.

• D Flip-Flop-7474.

• ALU Design.

• PART B: Embedded Systems (List of Experiments)

• Blinking led’s and push button interface using TM4CGH6PM.

• Timer based interrupt programming using TM4C123GXL

• Hibernation module for TM4C123GH6PM microcontroller

• In-Build ADC of TM4C123GH6PM & Potentiometer with TM4C123GXL

• PWM and ADC Modules of TM4C123GH6PM Microcontroller

• Sensor Hub booster pack with TM4C123GXL

•

• PART C: Additional Experiments

• 1.Implementation of JK- Flipflop using VHDL

• 2.Echo of the data input back to the PC using UART

•

VLSI Design Flow

VLSI Simulation Tools

• 1. Synthesis Tool: Xilinx Project NavigatorISE9.1i.

• 2. Simulation Tool: Modelsim Simulator.

VLSI Simulation Tools

• PROCEDURE:• 1. Open Xilinx ISE 9.1i.• 2. Create a new source file in a new project with suitable name.• 3. Create the file in VHDL/Verilog module.• 4. Select the appropriate input and output ports according to the requirements.• 5. Type the program and save it and synthesize the process.• 6. Select Synthesize XST, check for syntax errors and generate report and RTL • schematic. • 7. Create another new source.• 8. Select source type as Test bench wave form.• 9. Associate the test bench to the source.• 10. Assign clock and timing details.• 11. Give the input waveforms for the source.• 12. Save the input waveforms and perform behavioral simulation.• 13. The simulated output waveforms window will be shown.

VLSI Simulation Tools

• DUMPING PROCESS:

• 1. In the process window, go to ‘user constraints’ and select ‘assign package pins’ and after that double click on ‘implement design’.

• 2. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’ clock in startup options.

• 3. Select boundary scan in ‘impact window’ after double clicking on ‘configure Device’.

• 4. In ‘generate programming file’ double clicking on ‘programming file generation report. Bit file will be generated.

• 5. Xilinx boundary scan window will appear when the bit file is selected. Right click on Xilinx component and select program.

• 6. Programming properties will appear and finally program will be succeeded.

• 7. Thus the program can be dumped into FPGA kit and finally output can be seen on the kit.

SIMULATION AND IMPLEMENTATION OF XILINX TOOL

SIMULATION AND IMPLEMENTATION OF XILINX TOOL

SIMULATION AND IMPLEMENTATION OF XILINX TOOL

SIMULATION AND IMPLEMENTATION OF XILINX TOOL

SIMULATION AND IMPLEMENTATION OF XILINX TOOL

SIMULATION AND IMPLEMENTATION OF XILINX TOOL

SIMULATION AND IMPLEMENTATION OF XILINX TOOL

SIMULATION AND IMPLEMENTATION OF XILINX TOOL

SIMULATION AND IMPLEMENTATION OF XILINX TOOL

RTL Schematic:

Technological Schematic:

RTL Schematic:Technological Schematic:

• RTL View

• Viewing an RTL schematic opens an NGR file thatcan be viewed as a gate-level schematic.

• This schematic is generated after the HDLsynthesis phase of the synthesis process. It showsa representation of the pre-optimized design interms of generic symbols, such as adders,multipliers, counters, AND gates, and OR gates,that are independent of the targeted Xilinxdevice.

RTL Schematic:Technological Schematic:

• Technology View• Viewing a Technology schematic opens an NGC file that can

be viewed as an architecture-specific schematic.• This schematic is generated after the optimization and

technology targeting phase of the synthesis process. Itshows a representation of the design in terms of logicelements optimized to the target Xilinx device or"technology"; for example, in terms of of LUTs, carry logic,I/O buffers, and other technology-specific components.Viewing this schematic allows you to see a technology-levelrepresentation of your HDL optimized for a specific Xilinxarchitecture, which might help you discover design issuesearly in the design process.

FPGA Development Platform

• Safety Instructions

• Read the following safety instructions carefullybefore operating the instrument. To

• avoid any personal injury or damage to theinstrument or any product connected to it.

• Do not operate the instrument if suspect anydamage to it.

• The instrument should be serviced byqualified personnel only.

FPGA Development Platform

• 1. Explanation of System Architecture

• a. FPGA (XILINX Spartan3) Application Development Board (400K Gates, I/O

• ports 136, Number of pins 208.

• b. The I/O experiments board.

• c. Webpack 8.1 Development Software CD.

• d. Sample Code for Board Testing.

• e. Operational manual for reference.

FPGA Development Platform

• 1. Explanation of System Architecture

• a. FPGA (XILINX Spartan3) Application Development Board (400K Gates, I/O

• ports 136, Number of pins 208.

• b. The I/O experiments board.

• c. Webpack 8.1 Development Software CD.

• d. Sample Code for Board Testing.

• e. Operational manual for reference.

FPGA Development Platform• 2. Functional Explanation of Development Board

• a. The FPGA includes 400K gate count and its interior circuit uses the SRAM

• cells architecture.

• b. Therefore its speed has reached several hundred Mhz.

• c. Data can be stored in an EPROM as a final design depends on the circuit size.

• d. The connecting pins of FPGA could arbitrarily set, and the input / output port

• need not use the single wire to be connected for signal output in order to avoid

• the experimental mistake to destroy the board.

• e. It has four, 40pin IDC connector to interface the I/O board & any digital

• design.

• f. Mode select for downloading bit stream into FPGA or EPROM.

• g. On board user selectable clock up to 100MHz.

• h. Device can be program in Boundary scan mode.

FPGA Development Platform• Features & Specifications

• • Device: Xilinx FPGA (XC3S400 PQ208)

• • On board +5V, +3.3V, +2.5V supply to FPGA & other hardware circuit.

• • On board, 2 Crystal 8MHz & 25MHz.

• • Master Reset key for hardware reset

• • Program Key for FPGA reconfiguration

• • Onboard Flash EPROM for FPGA backup

• • JTAG Interface ( Boundary Scan )

• • PROM Interface (XCF02S)

• • 40 pin, 4 header connector for external I/O's

• • Number of I/O's 136

FPGA Architecture

XILINX Spartan III FPGAs:

1. Parallel JTAG

• FPGA Programming mode (Bypass PROM)• FPGA Startup Clock : JTAG Clock• Shunt Setting : M0 – 1-2 Short (short with VCC3V3)• PROM MCS file generation mode for FPGA U1• FPGA Startup clock : CCLK• Flash PROM Programming mode (Bypass FPGA)• FPGA Startup Clock : JTAG Clock• Shunt Setting : M0 – 1-2 Short (short with VCC3V3)• PROM to FPGA U1 Mode• Shunt Setting : M0 – 2-3 Short (short with DGND)

2. USB JTAG

• FPGA Programming mode (Bypass PROM)• FPGA Startup Clock : JTAG Clock• Shunt Setting : M0 – 1-2 Short (short with VCC3V3)• PROM MCS file generation mode for FPGA U1• FPGA Startup clock : CCLK• Flash PROM Programming mode (Bypass FPGA)• FPGA Startup Clock : JTAG Clock• Shunt Setting : M0 – 1-2 Short (short with VCC3V3)• PROM to FPGA U1 Mode• Shunt Setting : M0 – 2-3 Short (short with DGND)

• Embedded System Lab

Embedded System

• “It is a combination of Hardware and software which is used to perform a specific task with some real time constraints”

Embedded Hardware and Various Building Blocks

Components of Embedded System Hardware:

CPU

Sensors LCD LEDs FunctionKeypad

Communication

Interface

DAC

Clock Circuitry

CHIP SELECT

Watchdog Timer &

Reset Circuitry

Debug Port

ADC

Power Supply

Unit

RAM

ROM

Tiva C Series Launch Pad

Tiva C Series LaunchPad

Create a New Project from Project New Project

• Click the Resume button to run the code.• Click Suspend. to stop code execution in the middle

of the program.• To single-step into the code, click Step Into to help in

debugging the program and check if each line• of code is producing the desired result.• The Terminate button will terminate the active

debug session, close the debugger and return to the• "CCS Edit" perspective. It also sends a reset to the

LaunchPad board.

EK-TM4C123GXL LAUNCHPAD

EXPERIMENT 1:BLINK LED

FIGURE: functional block diagram

Gpio pin function and USB device connected

EXPERIMENT: 2 TIMER INTERRUPT

Figure: Block-diagram to change led status using timer interrupt

EXPERIMENT:3 HIBERNATION

Figure: Functional Block Diagram for Hibernation module and Wake-up of the Tiva Microcontroller

EXPERIMENT: 4 POTENTIOMETER

Figure: Functional block diagram for the experiment

Figure: Hardware setup

EXPERIMENT: 5 PWM

Figure: PWM output for Analog signal

Generate PWM signal

Design calculationsThe PWM clock is the system clock divided by a factor, and the factor is configured to 64 in thisprogram. To correlate with variation as a percentage change, the PWM period is set at 100. Thisallows the PWM period to change from 1 to 100.System Clock = 40MHzPWM Clock = System Clock /Dividing factor = 40MHz /64 = 625kHz The dividing factor can range from 2 to 64 for the PWM generator.PWM Period = 100PWM frequency = PWM Clock / PWM Period PWM frequency = 625 kHz / 100 = 6.25kHz

HARDWARE SETUP

DC MOTOR SPEED CONTROL USING PWM

PWM CLOCK AND FREQUENCY

HARDWARE SETUP

EXPERIMENT: 7 UART ECHO

Serial Terminal Settings

SENSOR HUB

FUNCTIONAL BLOCK DIAGRAM

EXPERIMENT: 9 USB BULK TRANSFER

OUTPUT

EXPERIMENT: 10 IQ MATH LIBRARY

EXPERIMENT: 11 IP CONFIGURATION

IP CONFIGURATION OUTPUT ON SERIAL TERMINAL

PINGING IP ADDRESS

EXPERIMENT: 12 EMAIL TRANSFER USING SMTP.

EXPERIMENT: 13 HTTP SERVER

OUTPUT ON SERIAL TERMINAL

S.No Name of the Equipment QuantityAmount

(Rs.)

1. FPGA Trainer Kits with Xilinx 05 92,500/-

2. CPLD Trainer Kits with Xilinx 05 74,750/-

3. Digital I/O Boards 10 25,000/-

4.NI Multisim (Version 14.1) 18 Users 2,33,640/-

5.

PC’s

System Configuration

1. HCL -33Nos

Mother Board -1280

P4 @ 2.6 GHz Processor

160GB Hard disk

2 GB RAM

HCL 15"inches Colour Monitor

HCL Keyboard, HCL mouse.

2. DELL -3Nos

Mother Board -1280

P4 @ 2.6 GHz Processor

360GB Hard disk

2 GB RAM

DELL 15"inches Colour Monitor

DELL Keyboard, HCL mouse.

36

33(HCL) 5,08,200/-

3(DELL) 54,900/-

Total 9, 88,640/-

Major Equipment Details

Lab Physical View

DOs & DON’TS

• Do not displace monitor, keyboard, mouse etc.

• Do not use personal pen drives without permission.

• Students should not attempt to repair, open, tamper or interfere with any of the computer, cabling, or other equipment in the laboratory.

Safety Precautions

• Data will be preserved using UPS Backup.

• Equipped with Fire Extinguishers.

• Students and Faculty are instructed to follow Safety Instructions Chart in the Laboratories.

• Before inserting USB Stick, the Pen drives have to be scanned for any malicious content.

• The Lab is under CC Camera surveillance.

• Keep all the Computers Updated with antivirus software.

• Make Sure the Firewalls are enabled on each and every Computer.

• Miniature Circuit Breaker’s (MCB’s).

• Students inserting USB Stick have to be scanned for any malicious content.

• Students should not attempt to repair, open, tamper or interfere with any of the computer, cabling, or other equipment in the laboratory.

• Do not displace monitor, keyboard, mouse etc.

• Do not use personal pen drives without permission.

THANK YOU