Department of Communication Engineering, NCTU 1 Unit 5 Programmable Logic and Storage Devices – RAMs and FPGAs

Department of Communication Engineering, NCTU 1

Unit 5 Programmable Logic and Storage Devices –RAMs and FPGAs


Unit 5-1 Static Random Access Memory (SRAM)


Digital CAS Unit 5 : SRAMs and FPGAs Sau-Hsuan Wu

Reason for using random access memory (RAM) Computers and other digital systems perform operations that

retrieve, manipulate, transform and store data Read only memories (ROMs) can not dynamically store data Registers support fast and random storage, but cannot be

used for mass storage because they are implemented with FFs and occupy too much physical area

RAM is faster and occupies less area than a register file Most RAMs are volatile- the information vanishes after

power is removed from the device There are two types of RAMs: static and dynamic

Dynamic RAMs need refresh and static RAMs don’t



Basic static RAM (SRAM) structureWord EN

Bit

_lin

e_N

Bit

_lin

e

cellCell_N

Word EN

Bit

_lin

e_N

Bit

_lin

e



module SRAM1 (data_out, data_in, CS_N,WE_N); 　 output data_out; input data_in; input CS_N, WE_N;

wire data_out = (CS_N==0) ? (WE_N==0) ? data_in : data_out : 1’bz;endmodule

Level-sensitive Verilog models of RAMs

A 32K 8 SRAM

data_outCS

WE

data_in

CSWEOE

MuxMux

Demux

D_IN

D_OUT

CSWEOE

MuxMux

Demux

D_IN

D_OUT

CSWEOE

MuxMux

Demux

D_IN

D_OUT

CSWEOE

MuxMux

Demux

D_IN

D_OUT

CSWEOE

MuxMux

Demux

D_IN

D_OUT

CSWEOE

MuxMux

Demux

D_IN

D_OUT

CSWEOE

MuxMux

Demux

D_IN

D_OUT

CSWEOE

MuxMux

Demux

D_IN

D_OUT

Decoder

data_in

data_out



Basic static RAM (SRAM) structure

A 16K SRAM

module SRAM2 (data, CS_N,WE_N,OE_N); 　 output data_out; input CS_N, WE_N,OE_N;

wire latch_out = ((CS_N==0) && (WE_N==0)&&(OE_N==1)) ? data : latch_out;

assign data = ((CS_N==0) && (WE_N==1)&&(OE_N==0)) ? latch_out : 1’bz;

endmodule

data

CS

OE

WE

Column Input/OutputColumn Input/Output

AA1010

AA99

AA00

AA33

AA22

AA11

AA00 DD7 7 DD6 6 DD5 5 DD44DD3 3 DD2 2 DD1 1 DD00


Unit 5-3 Altera FPGA Architecture



Architecture of Stratix Logic array blocks (LABs) :

10 logic elements (LEs) in each LAB Memory block structures

512 RAM: simple dual-port memory blocks (512 +parity =576) M4K RAM: true dual-port memory blocks (4K + parity =4608) M-RAM: true dual-port memory blocks (512K+parity=589,824)

DSP blocks 9×9- or 18×18- or 36×36-bit multiplier with add and subtraction 18-bit input shift registers

I/O element (IOE) : contains a bidirectional I/O buffer and six registers Supports single-ended, differential I/O standards and external

memory devices such as DDR-SDRAM





Logic elements (LE) : the smallest unit of logics in the Stratix architecture each of which contains : A four-input LUT A programmable register :

can be configured for D, T, JK and SR FFs Asynchronous data,

Support single bit addition and subtraction



















Single-Clock SRAM without read-through-write behavior

module ram_infer (q, a, d, we, clk);output reg [7:0] q;input [7:0] d;input [6:0] a;input we, clk;reg [7:0] mem [127:0];always @ (posedge clk) beginif (we)mem[a] <= d;q <= mem[a]; // q doesn't get d in this clock cycleendendmodule

clk

we

a A0 A1 A3

d d(A0)+ d(A1)+ d(A3)+

q d(A1)d(A0)

A2

d(A2)+

d(A2)



Single-Clock SRAM with read-through-write behavior

module ram_infer (q, a, d, we, clk);output [7:0] q;input [7:0] d;input [6:0] a;input we, clk;reg [6:0] read_add;reg [7:0] mem [127:0];always @ (posedge clk) beginif (we)mem[a] <= d;read_add <= a;endassign q = mem[read_add];endmodule

clk

we

a A0 A1 A3

d d(A0)+ d(A1)+ d(A3)+

q d(A1)+d(A0)+

A2

d(A2)+

d(A2)+


































Unit 5-4 Model Simulation Library



Choose a working directory that you want to store the compiled Choose a working directory that you want to store the compiled Libraries Libraries



Create a new library for the compiled libraryCreate a new library for the compiled library



Create the library named:stratix_atoms

Repeat the above two procedures For the following two librariesaltera_mf 220model



Compile the Compile the stratix_atomsstratix_atoms

Library Library



Choose the Choose the stratix_atoms.vstratix_atoms.v

filefile



Notice the difference fromNotice the difference from

Map the stratix_atoms Map the stratix_atoms to the compiled stratix_atomsto the compiled stratix_atoms

librarylibrary


Unit 5-5 Simulation with Altera mega-functions



Load Altera_mflibrary



Load Altera_mf

Then you are done


Unit 5-5 Post Layout Simulation



Specify options for Generating output filesFor modelsimFile name : *.vo



Import top-level Test bench andtop-level design*.vo only



Load Stratix_atomslibrary



Load Stratix_atomslibrary



Notice!! the Instance name of the top-level design, not its module nameNotice!! the Instance name of the top-level design, not its module name

Load *.sdo fileFrom the SDFOption andapply it to the Top-level design

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Department of Communication Engineering, NCTU 1 Unit 5 Programmable Logic and Storage Devices – RAMs and FPGAs