DEPARTMENT OF ELECTRICAL &ELECTRONICS …users.okan.edu.tr/burak.kelleci/Classes/Digital_Design/Mathematical Operations.pdfIn VHDL, there is a resize function to change bit sizes of

DIGITAL DESIGN

DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING

Assoc. Prof. Dr. Burak Kelleci

Spring 2020

OUTLINE

○ Unsigned and signed numbers

○ Addition and subtraction

○ Multiplication

○ Division

Mathematical Operations 2

MATHEMATICAL OPERATIONS

○ Mathematical operations are used to realize various algorithms.

○ Most used operations are addition and subtraction.

○ Multiplication and especially division are also used but they consume significant area.

○ Therefore, if possible these algorithms are avoided in algorithms.

○ For other mathematical operations, such as trigonometric calculations, special algorithms such as Cordic are developed.

○ Usually these algorithms require significant resources, so if possible they are avoided.


UNSIGNED AND SIGNED NUMBERS

○ In base 10 a minus sign is put to indicate negative numbers.

○ In digital systems there is no minus sign, so a bit is reserved to indicate negative numbers.

○ This method also creates ambiguity.

○ Therefore, in digital systems the numbers are separated as unsigned and signed numbers.

○ In unsigned numbers, there is no sign bit and the number is assumed as a positive number.

○ In signed numbers, one bit is reserved for the sign and depending on the coding, such as sign and magnitude, two’s complement, excess-N, of bits the rest of the bits indicate the magnitude.



○ In sign and magnitude representation one of the bits indicates the sign and the rest indicates the magnitude of the number.

○ Usually the most significant bit is the sign bit.

○ Number zero uses two codes.



○ The zero problem is solved using two’s complement.

○ The MSB shows the sign.

○ Logic 1 of MSB indicates a negative number.

○ To find the magnitude of a negative number, all bits of the number is inverted and one added to the result.

○ All VHDL versions support two’s complement numbers.

○ Verilog supports two’s complements numbers since Verilog-2001 standard.



○ In excess-N method, N is subtracted from the number.

○ For example, unsigned value of 1111 is 15.

○ In excess-7 representation, 7 is subtracted from 15 to find the number.

○ Number N is equal to zero.



○ VHDL and Verilog support only two’s complement representation.

○ In VHDL, numeric_stdpackage must be included.

○ There is no limit for the bit size of signed and unsigned numbers.


○ In VHDL, unsigned and signed types are used.

○ In Verilog, the numbers are unsigned by default. Signed keyword is used to define signed number


○ In VHDL, integer numbers are defined using integer type.

○ If the limits of an integer number are not defined, synthesizer realizes these numbers as 32-bit number.

○ RANGE <lower limit> TO <upper limit>should be given in order to synthesize integer number correctly.

○ In Verilog inputs and outputs can be defined as signed or unsigned similar to wires.

○ If signed keyword is not used Verilog assumes unsigned.

○ To define signed signedkeyword must be used.




○ In Verilog numbers are defined as size’base value

○ size: the number of bits in the number. Omitting size creates 32 bit numbers

○ base: radix and sign property

○ For negative numbers it is possible to add minus sign if the number is written in decimal format.


○ In VHDL, the conversion among unsigned, signed, std_logic_vector and integer is often used.

○ To convert unsigned and signed to std_logic_vector

○ To convert std_logic_vector to unsigned and signed

○ To convert unsigned and signed to integer

○ To use to_integer command IEEE.numeric_std.all package must added.



○ To Convert from integer to signed and unsigned, the bit size of destination must be given.

○ For example to convert an integer number to 8 bit signed or unsigned number

○ There is no direct conversion between std_logic_vector and integer. Conversion is performed in two steps by first converting the number to unsigned or signed.



○ Every bit of signed, unsigned and std_logic_vector is std_logic.

○ Therefore, following assignments are legal.

○ The following assignment is also legal, because individual bits are std_logic.



○ If unsigned and signed numbers are used in conditional operations, the result is interpreted differently.

○ For example, for two 8-bit numbers

○ If they are unsigned, the a>b and a<b operations assume that a and b are between 0 and 255.

○ If they are signed, the a>b and a<b operations assume that a and b are between -128 and 127.

○ In Verilog, there is also arithmetic shift operation to take the sign bit into account during shift operation.

○ If -6 (1010) is shifted, the sign bit not saved and the result is 5 (0101).

○ If arithmetic shift is used, the result ,is -3 (1101).


ADDITION AND SUBTRACTION

○ Addition and subtraction are basic mathematical operations and supported by synthesizers.

○ In VHDL, all operands must be the same type.

○ It is not allowed to mix signed and unsigned numbers



○ To subtract unsigned numbers and convert the result to signed number, the unsigned number is either converted first std_logic_vector then signed number or first integer then signed number.

○ Since unsigned numbers do not have sign bit, a sign bit must be added before conversion to signed number.



○ In VHDL, sometimes a binary representation is not clear whether it is a signed or unsigned number.

○ In this example, the value of “1010” is not clear. If it is a signed number than its value is -6. If it is an unsigned number than its value is 10.

○ To avoid this ambiguity, signed’ is used.

○ Instead of using bits integer number can be used. In that case synthesizer automatically perform correct conversion.



○ In Verilog, the types during addition and subtraction is not strictly controlled as VHDL.

○ For example, the following addition gives the same result.

○ If the number of bits of the signal is greater than the number, than the bit size of the number is increased. In that case if the number is signed number, than the sign bit is repeated. If the number is unsigned than 0 is added to increase the number of bits.



○ Addition of two N-bit numbers results in a N+1 bit number.

○ VHDL requires that all numbers bit sizes in a addition equal each other.

○ If the result does not fit the target bit size, VHDL assigns bits starting from LSB.

○ In order not to get correct result, bit sizes must be resized.



○ In VHDL, there is a resize function to change bit sizes of numbers.

○ For example, the size of a and b are changed to match bit size of c.

○ c’length gives the size of c vector. If the size of c is changed, the parameters of resize is automatically changed.

○ In Verilog, vector operations are used to change the bit size.

○ 8{a[7]} command repeats a[7] value 8 times.



○ Addition and subtraction operations may be used successively.

○ If number of bits is increased at every operation, the required number of bits is increase significantly.

○ To prevent number of bit expansion, the bit number of the result should be restricted.

○ There are two methods to limit the number of bits

○ One is to throw away the MSB bits.

○ The other to equal the result to maximum or minimum allowable value.



○ The minimum of an unsigned number is zero and the maximum is all one.

○ The sign bit of the minimum of signed number is 1 and the rest of the bits are 0. For maximum number, the sign bit is 0 and the rest is 1.


MULTIPLICATION

○ Multiplication operator * is supported by VHDL and Verilog, and many synthesizer.

○ Since multiplication requires more area than addition, if possible it is avoided.

○ In algorithms, multiplication is used either to multiply a signal by a constant or to multiply two signals.

○ To multiply a signal with constant, shift and addition operation are used instead of using a multiplier.

○ To multiply a signal by 2N, the signal is shifted to left by N bits.

○ For example, to multiply 2 (10) by 2 a bit left shift operation gives 4 (100).


MULTIPLICATION

○ Shift and addition is used to multiply a signal with a constant.

○ For example, to multiply a signal by 100, the constant is converted to binary to determine the powers.

○ 100 in base 10 is equal to “1100100” in Base 2.

○ Assuming the power of LSB zero, 100 is written as

○ Multiplication by 100 is addition of 6-bits shifted, 5-bits shifted and 2-bits shifted version of the signal.

○ The following Verilog code multiplies unsigned signal A by 100.


MULTIPLICATION

○ If subtraction is also used to multiply by constant, the number of operations may reduce.

○ For example, to multiply by 63 (111111)2

○ As seen from this example, instead of using 5 adder, the same operation can be performed using 1 subtractor.

○ To realize the multiplication with minimum number of addition and subtraction Canonic Signed Digit (CSD) technique is used.

○ In CSD, the addition is represented using +1, subtraction -1 and no operation 0.

○ First the constant is written in base 2.

○ Then starting from LSB table is used to determine c value for the next bit and the operation.


MULTIPLICATION


○ For example, the operation to multiply by 63 is calculated using CSD technique.

○ The result indicate 1 for the 6th bit and -1 for the 0th bit.

○ Therefore, the operation is

MULTIPLICATION

○ Some synthesizers detect the multiplication by constant and automatically uses CSD technique.

○ In that case * operator may be used to multiply by constant.

○ The number of bits required for the result is the summation of number of bits of the signals.

○ If two 16 bit signals are multiplied the result is 32 Bit.


MULTIPLICATION

○ The coding of multiplication of two signals is similar to the coding of multiplication by constant.

○ The number of bits of the result variable should be equal to the sum of number of bits of signals.


MULTIPLICATION

○ Although multiplication is supported by many synthesizers, it can be also realized by partial summation using for loop.


DIVISION

○ General division requires more hardware than addition, subtraction and multiplication.

○ Therefore, if possible it is avoided.

○ Division by power of two is realized using right shift operations.

○ For example, 14 (1110)2 is divided by 4 (22).

○ Right shift of 14 is 3 (11)2 and the remainder is 2 (10)2.

○ To divide arbitrary numbers classical division algorithm is used.


DIVISION


○ The division algorithm can be implemented using combinational circuit or finite state machine.

DIVISION


DIVISION

○ Division algorithm is implemented as combinational circuit using for loop.

○ n1:=(others => ‘0’) is used to set all bits of n1 to logic 0. This technique does not require the length of the signal. Therefore, it is not necessary to change the code if there is any change of signal width.


Documents

DEPARTMENT OF ELECTRICAL &ELECTRONICS …users.okan.edu.tr/burak.kelleci/Classes/Digital_Design/Mathematical Operations.pdfIn VHDL, there is a resize function to change bit sizes of