(Department of Electronics and Communication Engineering ...gvpce.ac.in/mtechregsyl18-19/9.VDES_18-19.pdfstudent shall re-register and repeat those courses as and when they are offered

ACADEMIC REGULATIONS

COURSE STRUCTURE AND SYLLABI

M.TECH.

VLSI DESIGN AND EMBEDDED SYSTEMS

(Department of Electronics and Communication Engineering)

2018 – 2019

(Choice Based Credit System)

GAYATRI VIDYA PARISHAD

COLLEGE OF ENGINEERING

(AUTONOMOUS)

Re-Accredited by NAAC with A Grade with a CGPA of 3.47/4.00

Affiliated to JNTUK-Kakinada

MADHURAWADA, VISAKHAPATNAM – 530 048

VISION

To evolve into and sustain as a Centre of Excellence in

Technological Education and Research with a holistic approach.

MISSION

To produce high quality engineering graduates with the requisite

theoretical and practical knowledge and social awareness to be able

to contribute effectively to the progress of the society through their

chosen field of endeavor.

To undertake Research & Development, and extension activities in

the fields of Science and Engineering in areas of relevance for

immediate application as well as for strengthening or establishing

fundamental knowledge.

FOREWORD

The GVP college of Engineering (Autonomous) has entered into a new

phase as it completed one cycle of autonomy. Recently the Autonomy

has been extended for six more years(2014-2020) by UGC, the

affiliating University JNTU-K. The experiences with the experiments

and innovations brought into the curriculum with the help of autonomy

are proving successful and encouraging.

The paradigm shift in the curriculum design has been brought into the

system in 2013 in the form of Out Come Based Education (OBE) and

the systems and processes are stabilized in this regard.

Recently, the Choice Based Credit System (CBCS) has been introduced

along with the grading system as per the guidelines of UGC, to offer

more choice, facilitate the cross mobility and uniformity across the

country.

The concepts of Pedagogical training and Industrial training are also

introduced after II semester as an elective to enable the graduates

sharpen their skills.

Credits are introduced for Dissertation work to infuse more seriousness

and as a qualitative measure of the work carried out.

I thank all the expert members, Industry representatives, University

representatives and all other members on Boards of Studies, Academic

Council who helped us in brining a good shape to the curriculum.

I also thank the members of the Governing Body for their constant

support and guidance in all our academic endeavors.

I hope with these changes, the curriculum will be more beneficial to the

students to make them ready to face the elite society and the challenges

ahead.

PRINCIPAL

DEPARTMENT OF Electronics and

communication ENGINEERING

Vision

The vision of Electronic and Communication Engineering Department

is to be in the lead to create and develop professional and intellectual

human capital in electronics and communication engineering and

applications in order to foster the technological, economic and social

enrichment of the state and the nation and to contribute to global

village connectivity

Mission

To play professional role to create, develop, organise and manage

complex technologies and products, contribute to the betterment of

society and evolve better quality of living in a world increasingly

influenced by scientific and technological innovation.

To provide students of E &C Engineering an environment of

academic freedom that will insure the exchange of ideas and the

dissemination of knowledge in this discipline.

To Recognize as a place that encourages research excellence and

diversity in thought and endeavor in multidisciplinary applications

MEMBERS ON THE BOARD OF STUDIES

IN

ELECTRONICS AND COMMUNICATION

ENGINEERING

Dr. N. Bala Subrahmanyam Chairman BoS

Professor, Department of Electronics and Communication

Engineering, G.V.P. College of Engineering (A), Visakhapatnam

Dr. M.V.S. Sairam Professor & Head, Department of Electronics and Communication

Engineering, G. V. P College of Engineering (A), Visakhapatnam

Dr. A. Mallikarjuna Prasad Professor of ECE & Vice Principal, University College of

Engineering Kakinada (Autonomous), JNTU Kakinada, Kakinada,

Dr. K. Rajgopal Professor, Department of Electrical Engineering, IISc- Bengaluru,

Bengaluru, Karnataka

Dr. S.K. Patra Director, IIIT - Vadodara, Gandhinagar, Gujarat,

Sri D.V.R. Murty Vice-President, INVECAS, Plot 90, Road No. 2, Banjara Hills,

Hyderabad

Sri M.S. Abhishek IC Design Engineer, Broadcom India Research Pvt. Ltd., Varthur

Hobil, Bengaluru, Karnataka,

All Faculty members of the Department

M.Tech. vlsi design and

embedded systems

Programme Educational

Objectives (PEOs):

After 3-5 years of graduation the graduate shall be able to

PEO1 Comprehend frontier areas of knowledge and instill appetite

for higher learning and research in Embedded Systems and

VLSI Design areas.

PEO2 Gain breadth of Engineering & Technological knowledge to

comprehend analyze, design and create novel products &

solutions for real life problems.

PEO3 Be a professional to perform with academic excellence,

leadership and ethical guidelines needed for a lifelong

productive career.

Program Outcomes:

At the end of the programme the student shall be able to

1. Apply the knowledge of Electronics and Communication

Engineering to solve complex problems in Embedded Systems

and VLSI Design.

2. Identify, formulate and analyze problems related to Embedded

Systems and VLSI Design area and substantiate the conclusions

using the first principles of sciences and engineering.

3. Design solutions for Embedded Systems and VLSI Design

problems and design system components and processes that meet

the specified needs with appropriate consideration for public

health and safety.

4. Perform analysis and interpretation of data by using research

methods such as design of experiments to synthesize the

information and to provide valid conclusions.

5. Select and apply appropriate technique from the available

resources and modern tools, and will be able to predict and model

complex engineering activities with an understanding of the

practical limitations.

6. Collaborate with engineers of other disciplines and work on

projects which require multi-disciplinary skills.

7. Demonstrate knowledge and understanding of the engineering

and management principles and apply the same while managing

projects in multidisciplinary environments.

8. Communicate fluently on complex engineering activities with the

engineering community and society, and will be able to prepare

reports and make presentations effectively.

9. Engage themselves in independent and life-long learning in the

broadest context of technological change while continuing

professional practice in the Embedded Systems and VLSI Design.

10. Transform into responsible citizens by resorting to professional

ethics and norms of the engineering practice.

11. Carry out tasks by working independently and also in a group of

members.

PROGRAMME SPECIFIC OUTCOMES

1 Analyze, design and implement different techniques to evaluate the

performance metrics for VLSI – System on Chip.

2 Specify, design, prototype and test hardware and software for real

time embedded system applications.

GVP COLLEGE OF ENGINEERING (A) 2018

M.TECH-VDES i


M.TECH-VDES ii

ACADEMIC REGULATIONS (UNDER CHOICE BASED CREDIT SYSTEM EFFECTIVE FROM 2015-16 ADMITTED BATCH)

The M.Tech. Degree of Jawaharlal Nehru Technological University

Kakinada shall be recommended to be conferred on candidates who

are admitted to the program and fulfill all the following requirements

for the award of the Degree:

1.0 ELGIBILITY FOR ADMISSION: Admission to the above program shall be made subject to the

eligibility, qualifications and specialization as per the guidelines

prescribed by the APSCHE and AICTE from time to time.

2.0 AWARD OF M.TECH. DEGREE:

a. A student shall be declared eligible for the award of the M.Tech.

degree, if he pursues a course of study and completes it

successfully for not less than two academic years and not more

than four academic years from the year of first admission.

b. A student, who fails to fulfill all the academic requirements for the

award of the Degree within four academic years from the year of

his admission, shall forfeit his seat in M.Tech. programme.

3.0 STRUCTURE OF THE PROGRAMME:

Semester No. of courses Credits

I 5 THEORY + PE-I + 1 LAB +

ATCSL 6*3 + 2*2 22

II 5 THEORY + PE-II + 1 LAB 6*3 + 1*2 20

PEDAGOGY TRAINING / INDUSTRIAL TRAINING 2

III DISSERTATION 36

IV DISSERTATION (contd.)

TOTAL 80

PE: Professional Elective; ATCSL: Advanced Technical

Communication Skills Lab (in I/II semester)


M.TECH-VDES iii

Each course is normally assigned a certain number of credits as

follows:

3 credits for 3 lecture periods per week.

2 credits for 3 laboratory periods per week.

4.0 REGISTRATION: A student shall register for courses in each

semester at the beginning, from I semester onwards according to the

choice provided and courses offered by the concerned department.

5.0 ATTENDANCE REQUIRMENTS

a. The attendance shall be considered course wise.

b. A candidate shall be deemed to have eligibility to write his/her end

semester examinations in a course if he has put in at least 75% of

attendance in that course.

c. Shortage of attendance up to 10% in any course (i.e. 65% and

above and below 75%) may be condoned by a Committee on

genuine and valid reasons on representation by the candidate with

supporting evidence.

d. Shortage of attendance below 65% shall in no case be condoned.

e. A student who gets less than 65% attendance in a maximum of two

courses in any semester shall not be permitted to take the end-

semester examination in which he/she falls short. His/her

registration for those courses will be treated as cancelled. The

student shall re-register and repeat those courses as and when they

are offered next.

f. If a student gets less than 65% attendance in more than two courses

in any semester he/she shall be detained and has to repeat the entire

semester.

g. The attendance requirements are also applicable to Industrial

training and Pedagogy training.

6.0 METHOD OF EVALUATION: The performance of a student in each semester shall be evaluated

course-wise with a maximum of 100 marks each for theory, practical

course.


M.TECH-VDES iv

6.1 Theory: The assessment shall be for 40 marks through

Continuous Internal evaluation and 60 marks through end-semester

examination of three hours duration.

6.2 Continuous Internal evaluation: One part of the internal

evaluation shall be made based on the average of the marks secured in

the two internal examinations of 30 marks each conducted one in the

middle of the Semester and the other at the end of the semester. Each

mid-term examination shall be conducted for duration of 90 minutes

with 3 questions without any choice. The remaining 10 marks are

awarded through an average of continuous evaluation of assignments /

seminars / any other method, as notified by the teacher at the

beginning of the semester.

6.3 End-semester examination: For 80% of the theory courses, the

question paper shall be set externally and valued both internally and

externally. A chief examiner appointed for each course shall monitor

the valuation process. If the difference between the first and second

valuations is less than or equal to 9 marks, the better of the two

valuations shall be awarded. If the difference between the first and

second valuation is more than 9 marks, the chief examiner shall value

the script. The marks given by the chief examiner shall be final. For

the remaining 20% of the theory courses (as notified by the Principal),

the end semester evaluation shall be totally internal.

6.4 Laboratory: All Laboratory courses, in I and II Semesters, shall

be evaluated for 100 marks, out of which for 50 marks, through

external examination at the end of the semester and for 50 marks

through internal evaluation. The 50 internal marks are distributed as

25 marks for day-to-day work in two cycles and 25 marks for internal

examination. The internal examination shall be conducted by the

teacher concerned and another faculty member of the same

department once for each cycle of instruction period and average of

the two shall be considered for award of marks. 10 out of 12 to 16

experiments/exercises shall be completed in a semester.


M.TECH-VDES v

6.5 Pedagogy training shall be for a period of atleast 4 weeks and

evaluation shall be totally internal for 100 marks based on the

performance during the training.

6.6 Industrial training shall be for a period of atleast 4 weeks and a

report has to be submitted by the end of III semester. The assessment

shall be carried out for 100 marks during IV semester by an internal

evaluation committee comprising Head of the Department and two

faculty of the department including the project Supervisor.

6.7 Supplementary examinations: Supplementary examinations for

the odd semester shall be conducted with the regular examinations of

even semester and vice versa.

A student who failed in the end examination shall be given one

chance to re-register for each course provided the internal marks

secured by him in that course is less than 50%. In such a case, the

student must re-register for the course(s). In the event of re-

registration, the internal marks and end examination grades obtained

in the previous attempt are nullified.

7.0 EVALUATION OF DISSERTATION WORK:

Every candidate shall be required to submit the dissertation after

taking up a topic approved by the Departmental Research Committee

(DRC).

a. A Departmental Research Committee (DRC) shall be constituted

with the Chairman nominated by the Principal, two senior faculty as

Members along with the supervisor to oversee the proceedings of

the dissertation work from allotment of topic to submission.

b. A Central Research Committee (CRC) shall be constituted with a

Professor as Chair Person, Heads of the Departments that are

offering the M.Tech. programs and two other senior faculty

members.

c. Registration of Dissertation Work: A candidate shall register for the

Dissertation work in the beginning of the second year, only after

satisfying the attendance requirement of all the courses upto II


M.TECH-VDES vi

semester. The duration of the Dissertation work is for two

semesters.

d. After satisfying 7.0 c, a candidate has to submit, in consultation

with his supervisor, the title, objective and plan of action of his

project work to the DRC for its approval. Only after obtaining the

approval of DRC the student can initiate the Dissertation work.

e. If a candidate wishes to change his/her supervisor or topic of the

Dissertation work he can do so with the approval of the DRC. If so,

his date of registration for the Dissertation work shall start from the

date of change of Supervisor or topic as the case may be whichever

is earlier.

f. Evaluation of the dissertation shall be done twice, one at the end of

the III Semester and the other during the IV Semester.

g. The evaluation at the end of III semester shall be carried out by

DRC1 for 10 marks based on the presentation made by student on

the topic selected, literature survey and the progress of the work.

The student shall be permitted to proceed for the remaining work in

IV semester if he / she getsatleast 5 marks. Otherwise, the student

shall reappear for DRC1 with improvised work.

h. The evaluation during IV semester shall be carried out through

DRC2, DRC3, and CRC respectively each for 10 marks.

i. A candidate shall be permitted to submit his/her dissertation only

after successful completion of all theory and practical course with

the approval of CRC but not earlier than 40 weeks from the date of

registration of the project work. The candidate shall make an oral

presentation before the CRC and after the approval by CRC,

plagiarism checkshall be conducted for the Dissertation and shall

submit a draft copy to the Principal through the concerned Head of

the Department.

j. Three copies of the dissertation certified by the Supervisor shall be

submitted to the College after approval by the CRC.

k. For the purpose of adjudication of the dissertation, an external

examiner shall be selected by the Principal from a panel of 5

examiners who are experienced in that field proposed by the Head

of the Department in consultation with the supervisor.


M.TECH-VDES vii

l. The final evaluation, i.e., viva-voce examination, for 60 marks,

shall be conducted by a board consisting of the supervisor, Head of

the Department and the external examiner.

m. A student is deemed to be failed, if he secures less than 30

marks in the external viva-voce examination or less than 50 marks

from both internal and external viva-voce examination put together

and shall be awarded Fail grade (F). In such a case, the candidate

shall revise and resubmit the dissertation, in a time frame prescribed

by the CRC. If the student fails once again, the dissertation shall be

summarily rejected and the candidate shall change the topic and go

through the entire process afresh.

8. ACADEMIC REQUIREMENTS:

a. In case of theory courses having both internal and end semester

examination, a student is deemed to be failed if he secures less than

24 marks in the end semester examination or less than 50 marks

from both internal and end semester examination put together. For

all courses having examination at the end, a student is deemed to

be failed if he secures less than 50 marks.

b. In case of Practical courses having both internal and end semester

examination/evaluation, a student is deemed to be failed if he

secures less than 25 marks in the end semester examination or less

than 50 marks from both internal and end semester examination put

together. A student is deemed to be failed in dissertation, if he

secures less than 30 marks in the external viva-voce examination or

less than 50 marks from both internal and external viva-voce

examination put together. In case of Pedagogy Training / Industrial

Training / Advanced Technical Communication Skills Lab having

examination / evaluation at the end, a student is deemed to be

failed if he secures less than 50 marks.

9.0 Grading System: Absolute grading system shall be followed for

the award of grades.

9.0.1Grade Point: It is a numerical weight allotted to each letter

grade on a 10-point scale.

9.0.2 Letter Grade: It is an index of the performance of students in a

said course. Grades are denoted by letters O, A+, A, B+, B and F.


M.TECH-VDES viii

Based on the marks secured, a Grade Point is awarded for each theory

course / lab course / dissertation work / Pedagogy Training / Industrial

Training along with a corresponding Letter Grade as per the

following:

Grades and Grade Points

Letter Grade Grade

Point

Marks range

Theory Practical/Training/

Dissertation

O (Outstanding) 10 90-100 90-100

A+ (Excellent) 9 80-89 80-89

A (very good) 8 70-79 70-79

B+ (Good) 7 60-69 60-69

B (Above average) 6 *50-59 *50-59

F (Fail/Detained) 0 - -

Ab (Absent) 0 - -

* Pass mark

9.0.3. Credit Point: It is the product of grade point and number of

credits for a course.

9.0.4.The award of class and division after acquiring eligibility for the

award of M.Tech., degree is as per the following:

First class with distinction CGPA ≥ 7.75

First class 6.75 ≤ CGPA <7.75

Second class 6.00 ≤ CGPA <6.75

9.0.5. CGPA to Percentage of Marks Conversion:

At the end of the Programme,

Equivalent percentage of marks = (CGPA-0.75)*10

9.1 Computation of Semester Grade Point Average (SGPA) and

Cumulative Grade Point Average (CGPA):

The SGPA is the ratio of sum of the product of the number of credits

with the grade points scored by a student in all the courses taken by a


M.TECH-VDES ix

student and the sum of the number of credits of all the courses

undergone by a student in a semester, i.e

SGPA (Si) = Σ(Ci x Gi) / ΣCi

Where Ci is the number of credits of the ith

course and Gi is the grade

point scored by the student in the ith

course.

The CGPA is also calculated in the same manner taking into account

all the courses undergone by a student over all the semesters of a

programme, i.e.

CGPA = Σ(Ci x Si) / Σ Ci

where Si is the SGPA of the ith

semester and Ci is the total number of

credits in that semester. The SGPA and CGPA shall be rounded off to

2 decimal points and reported in the transcripts.

Transcript for each semester shall be issued containing letter grades

and grade points along with attendance grade, for each of the courses

registered, SGPA of that semester and CGPA up to that semester.

Marks will not be displayed on the transcript.

A consolidated transcript indicating the performance in all semesters

shall also be issued.

Note: The CGPA ranges for the award of class or division shall be as

decided by the affiliating University.

9.2 AWARD OF THE M.TECH. DEGREE: A student shall secure

a pass in all courses corresponding to 80 credits to be eligible for the

award of the M.Tech. degree.

9.3 PROVISION FOR IMPROVEMENT OF CGPA: A student

shall be permitted to improve his class or division from PASS CLASS

to SECOND CLASS or SECOND CLASS to FIRST CLASS after

successful completion (passing all the courses) of the programme. He

/ She may be allowed to appear for supplementary examinations and

earn grade points for improvement from at the most two courses of

his / her choice. The improvement provision shall be limited to one

attempt.


M.TECH-VDES x

10. WITHHOLDING OF RESULTS:

If the candidate has not paid any dues to the college or if any case of

indiscipline is pending against him, the result of the candidate shall be

withheld and he will not be allowed into the next higher semester.

The recommendation for the issue of the degree shall be liable to be

withheld in all such cases.

11. TRANSITORY REGULATIONS:

a. A candidate who has discontinued or has been detained for want of

attendance or who has failed after having studied the course, is

eligible for admission to the same or equivalent course(s) as and

when course(s) is/are offered, subject to 5.0 and 2.0.

b. Credit equivalences shall be drawn for the students re-admitted into

2015 regulations from the earlier regulations. A Student has to

register for the substitute / compulsory / pre-requisite courses

identified by the respective Boards of Studies.

c. The student has to register for substitute courses, attend the classes

and qualify in examination and earn the credits.

d. The student has to register for compulsory courses, attend the

classes and qualify in examination.

e. The student has to register for the pre-requisite courses, attend the

classes for which the evaluation is totally internal.

12.0 General:

i. Where the words ‗he‘, ‗him‘, ‗his‘, occur, they imply ‗she‘, ‗her‘,

‗hers‘, also.

ii. The academic regulation should be read as a whole for the purpose

of any interpretation.

iii. In the case of any doubt or ambiguity in the interpretation of the

above rules, the decision of the Chairman, Academic Council is

final.

The college may change or amend the academic regulations or syllabi

from time to time and the changes or amendments made shall be

applicable to all the students with effect from the dates notified by the

college.


M.TECH-VDES 1

M.TECH- VLSI DESIGN & EMBEDDED SYSTEMS

COURSE STRUCTURE

SEMESTER-I

COURSE

CODE

NAME OF THE COURSE L P C

15EC2201 Embedded System Concepts 3 0 3

15EC2202 VLSI Technology & Design 3 0 3

15EC2203 Digital Design through HDL 3 0 3

15EC2204 Microcontrollers and Applications 3 0 3

15EC2102 Advanced Digital Signal Processing 3 0 3

15EC2205

15EC2206

15EC2207

15EC2101

Elective – I

1. CPLD and FPGA Architecture and

Applications

2. System On Chip Architecture

3. System Modeling and Simulation

4. Data Communications

3 0 3

15HE2101 Advanced Technical Communication Skills 0 3 2

15EC2208 HDL Programming Laboratory 0 3 2

TOTAL 22

SEMESTER-II

COURSE

CODE


15EC2209 Embedded Computing Systems 3 0 3

15EC2210 Analog IC Design 3 0 3

15EC2211 Low Power VLSI Design 3 0 3

15EC2212 Digital IC Design 3 0 3

15EC2113 DSP Processors and Architecture 3 0 3

15EC2213

15EC2110

15EC2116

15EC2214

Elective – II

1. Electronic Design Automation Tools

2. Image and Video Processing

3. Neural Networks and Fuzzy Logic

Control

4. Algorithms for VLSI Design

Automation

3 0 3


M.TECH-VDES 2

15EC2215 Embedded Systems Lab 0 3 2

TOTAL 20

PEEDAGOGY TRAINING / INDUSTRIAL TRAINING

DURING THE BREAK PERIOD

AFTER II SEMESTER BEFORE III SEMESTER

SEMESTER-III

COURSE

CODE


15EC22DW Dissertation Work

15EC22PT/

15EC22IT

Pedagogy Training / Industrial Training 2

TOTAL 2

SEMESTER-IV

COURSE

CODE


15EC22DW Dissertation Work (contd.) 36

Syllabi for

I-Semester


M.TECH-VDES 3

EMBEDDED SYSTEM CONCEPTS

Course Code:15EC2201 L P C

3 0 3

Prerequisites: Requires pre-knowledge of Digital logic design,

FPGAs, Microprocessors and Microcontrollers, Computer

organization.

Course Outcomes: At the end of the course the student will be able to

CO1: Analyze various hardware and software units that comprise an

embedded system.

CO2: Describe the various buses and protocols.

CO3: Comprehend concepts of interrupt procedures and device

drivers.

CO4: Acquire knowledge in different Embedded Programming

Languages.

CO5: Design the programming modeling concepts and synthesize

Hardware and Software Co-Design.

UNIT I (10-Lectures)

INTRODUCTION:

Embedded systems, Processor embedded into a system, embedded

hardware units and devices in a system, embedded software in a

system, Examples of embedded systems, embedded system-on-chip

(Soc) and use of VLSI circuit design technology, Processor selection,

Memory selection.

UNIT II (10-Lectures)

DEVICES, BUSES AND PROTOCOLS:

I/O types and examples, Serial communication devices, Parallel

device ports, Sophisticated interfacing features in a device ports,

Wireless devices, Timer and counting devices, Watchdog timer, Real

time clock, Sensors, Analog to Digital Converters, Actuators.


M.TECH-VDES 4

Defining Buses and Protocols, On-board buses for Embedded

Systems, External Buses, Automotive Buses and Wireless

Communication Protocols.

UNIT III (10-Lectures)

DEVICE DRIVERS AND INTERRUPTS SERVICE

MECHANISM:

Programmed-I/O busy-wait approach without interrupt service

mechanism, ISR concept, Interrupt sources, Interrupt servicing

(Handling) mechanism, Multiple Interrupts, Context and the periods

for context switching, interrupt latency and deadline, Classification of

processors Interrupt service mechanism from context-saving angle,

Device driver programming.

UNIT IV (10-Lectures)

PROGRAMMING CONCEPTS AND EMBEDDED

PROGRAMMING IN C, C++ AND JAVA:

Software programming in Assembly language (ALP) and in High

level language ‗C‘, C program elements: Header and source files and

preprocessor directives, Program elements: Macros and functions

Program elements: Data types, data structures, modifiers, statements,

loops and pointers, Object-Oriented programming, embedded

programming in C++, Embedded programming in Java.

UNIT V (10-Lectures)

PROGRAM MODELLING CONCEPTS :

Program Models, DFG Models, and State Machine Programming

Models for Event-controlled Program Flow, Modeling of

Multiprocessor systems.

DESIGN TECHNOLOGY

Systems Synthesis and Hardware/Software Co-Design, Verification,

Hardware/Software co-simulation.

TEXTBOOKS:

1. Raj Kamal, ―Embedded systems: Architecture, programming and

design‖, TMH, 2nd Edition, 2007.

2. Lyla B. Das, ―Embedded Systems an Integrated Approach‖,

Pearson, First Impression, 2013.


M.TECH-VDES 5

REFERENCES:

1. Frank Vahid, Tony D. Givargis, ―Embedded System Design – A

Unified Hardware/Software Introduction‖, John Wiley, 2002.

2. Arnold S Burger, ―Embedded system Design‖, CMP books, 2010.

3. David Simon, ―An embedded software primer‖, PEA, 2008.

4. Steve Heath, ―Embedded systems Design‖, ELSEVIER, 2nd

Edition, 2005.


M.TECH-VDES 6

VLSI TECHNOLOGY & DESIGN


3 0 3

Pre requisites:

Electronics Devices and Circuits, Switching Theory and Logic

Design.

Course Outcomes:

CO1: Distinguish different IC technologies and analyze basic

electrical properties of MOS, CMOS & Bi-CMOS circuits.

CO2: Draw layouts for logic gates.

CO3: Analyze the concepts of alternate gate circuits, interconnect

delays, Gate and Network Testing.

CO4: Outline the concepts of memory cells, clocking disciplines,

power optimization, design validation & testing.

CO5: Acquire knowledge of floor-plan methods, High level

synthesis, CAD systems and Methodologies for chip design.

UNIT-I (10-Lectures)

BASIC ELECTRICAL PROPERTIES OF MOS, CMOS &

BICMOS CIRCUITS:

Review of Microelectronics: (MOS, CMOS, Bi CMOS) Technology

trends and projections, Ids-Vds relationships, Threshold voltage Vt,

Gm, GdsandWo, Pass Transistor, MOS, CMOS &Bi-CMOS Inverters,

Zpu/Zpd, MOS Transistor circuit model, Latch-up in CMOS circuits.

UNIT-II (10-Lectures)

LAYOUT DESIGN AND TOOLS:

Transistor structures, Wires and Vias, Scalable Design rules, Layout

Diagrams for NMOS and CMOS Inverters and Gates, Layout Design

tools.

UNIT-III (10-Lectures)

LOGIC GATES &COMBINATIONAL LOGIC NETWORKS:

Static complementary gates, switch logic, Alternative gate circuits,

low power gates, Resistive and Inductive interconnect delays.


M.TECH-VDES 7

Layouts, Simulation, Network delay, interconnect design, power

optimization, Switch logic networks, Gate and Network testing.

UNIT-IV (10-Lectures)

SEQUENTIAL SYSTEMS:

Memory cells and Arrays, clocking disciplines, Design, power

optimization, Design validation and testing.

UNIT-V (10-Lectures)

FLOOR PLANNING &CHIP DESIGN:

Floor planning methods, off-chip connections, High-level synthesis,

Architecture for low power, SOCs and Embedded CPUs, Architecture

testing. Introduction to cad systems (algorithms) and chip design -

Layout Synthesis and Analysis, Scheduling and binding,

Hardware/Software Co-design, chip design methodologies- A simple

Design example.

TEXTBOOKS:

1. Kamran Eshraghian, Eshraghian Dougles and A.Pucknell,

―Essentials of VLSI circuits and systems‖, 3rd

Edition, PHI, 2005.

2. Wayne Wolf, ―Modern VLSI Design‖, Pearson Education, 3rd

Edition, 2008.

REFERENCES:

1. Weste and Eshraghian, ―Principles of CMOS VLSI Design‖,

Pearson Education, 3rd Edition, 1999.

2. Fabricius, ―Introduction to VLSI Design‖, MGH International

Edition, 1990.

3. Baker and Li Boyce, ―CMOS Circuit Design, Layout and

Simulation‖, PHI, 2004.


M.TECH-VDES 8

DIGITAL DESIGN THROUGH HDL


3 0 3

Pre requisites: Switching Theory and Logic Design.

Course Outcomes:

At the end of the Course, Students will be able to:

CO1: Distinguish dataflow, behavioral and structural design

elements in VHDL.

CO2: Outline the basic concepts of Verilog language.

CO3: Classify gate level modeling and dataflow level modeling.

CO4: Distinguish behavioral level modeling and switch level

modeling.

CO5: Design Finite state machines and comprehend concepts of

functions, tasks, and user defined primitives.


COMBINATIONAL AND SEQUENTIAL LOGIC DESIGN

USING VHDL:

Data flow design elements, behavioral design elements, Structural

design elements, simulation and synthesis, decoders, multiplexers,

comparators, ALUs. Latches and flip-flops, counters, shift registers.


INTRODUCTION TO VERILOG:

Verilog as HDL, Levels of Design Description, Concurrency,

Simulation and Synthesis, Functional Verification, System Tasks,

Programming Language Interface (PLI), Module, Simulation and

Synthesis Tools, Test Benches. Language Constructs and

Conventions: Introduction, Keywords, Identifiers, White Space

Characters, Comments, Numbers, Strings, Logic Values, Strengths,

Data Types, Scalars and Vectors, Parameters, Memory, Operators.

System Tasks, Functions, and Compiler Directives: Parameters, Path

Delays, Module Parameters, System Tasks and Functions, File-Based


M.TECH-VDES 9

Tasks and Functions, Compiler Directives, Hierarchical Access,

General Observations.


GATE LEVEL MODELING:

Introduction, AND Gate Primitive, Module Structure, Other Gate

Primitives, Illustrative Examples, Tri-State Gates, Array of Instances

of Primitives, Additional Examples, Design of Flip-flops with Gate

Primitives, Delays, Strengths and Contention Resolution, Net Types,

Design of Basic Circuits.

DATA FLOW LEVEL MODELING:

Introduction, Continuous Assignment Structures, Delays and

Continuous Assignments, Assignment to Vectors, Operators.


BEHAVIORAL MODELING:

Introduction, Operations and Assignments, Functional Bifurcation,

Initial Construct, Always Construct, Examples, Assignments with

Delays, Wait construct, Multiple Always Blocks, Designs at

Behavioral Level, Blocking and Non-blocking Assignments, The case

statement, Simulation Flow. Iƒ and iƒ-else constructs, assign-deassign

construct, repeat construct, for loop, the disable construct, while loop,

forever loop, parallel blocks, force-release construct, Event.

SWITCH LEVEL MODELING:

Introduction, Basic Transistor Switches, CMOS Switch, Bi-

directional Gates, Time Delays with Switch Primitives, Instantiations

with Strengths and Delays, Strength Contention with Trireg Nets.


FUNCTIONS, TASKS AND USER-DEFINED PRIMITIVES:

Introduction, Function, recursive functions, Tasks, User- Defined

Primitives (UDP)- combinational UDPs, sequential UDPs, FSM

Design -Moore and Mealy Machines .

TEXT BOOKS:

1. John F.Wakerly, ―Digital Design Principles &Practices‖,

PHI/Pearson Education Asia, 3rd

Ed., 2005.


M.TECH-VDES 10

2. T.R.Padmanabhan and B.Bala Tripura Sundari, ―Design through

Verilog HDL‖, WSE, 2004, IEEE Press.

REFERENCE BOOKS:

1. J.Bhasker, ―VHDL Primer‖, Pearson Education/PHI, 3rd edition.

2. Michael D.Ciletti, ―Advanced Digital Design with Verilog HDL‖,

PHI, 2005.


M.TECH-VDES 11

MICROCONTROLLERS AND APPLICATIONS


3 0 3

Pre requisites:

Requires pre-knowledge of switching theory and logic design,

microprocessors and interfacing

Course Outcomes:

At the end of the course the student will be able to

CO1: Comprehend the architecture and instruction set of

microcontrollers.

CO2: Acquire knowledge on real time control interrupts & timers.

CO3: Able to interface control peripherals and high power devices.

CO4: Analyze real time operating system for MCUs & MCU based

industrial applications.

CO5: Comprehend the architecture of 16-bit (8096/80196) & ARM

microcontrollers.

UNIT- I (10-Lectures)

8051 FAMILY MICROCONTROLLERS INSTRUCTIONSET: Architecture of 8051microcontroller- internal and external memories,

Basic assembly language programming – Data transfer instructions –

Data and Bit manipulation instructions – Arithmetic instructions –

Instructions for Logical operations on the Bytes among the Registers,

Internal RAM, and SFRs – Program flow control instructions –

Interrupt control flow

UNIT- II (10-Lectures)

REAL TIME CONTROL: INTERRUPTS:

Interrupt handling structure of an MCU – Interrupt Latency and

Interrupt deadline – Multiple sources of the interrupts – Non-

maskable interrupt sources – Enabling or Disabling of the sources –

Polling to determine the Interrupt source and assignment of the

priorities among them –Interrupt structure in Intel 8051.


M.TECH-VDES 12

REAL TIME CONTROL: TIMERS

Programmable Timers in the MCUs – Free running counter and real

time control – Interrupt interval and density constraints.

UNIT- III (10-Lectures)

SYSTEMS DESIGN :

Synchronous serial-cum-asynchronous serial communication – ADC

Circuit Interfacing – DAC Circuit Interfacing – stepper motor -

Digital and Analog Interfacing Methods, Switch, Keypad and

Keyboard interfacings – LED and Array of LEDs – LCD interface –

Programmable instruments interface using IEEE 488 Bus –

Interfacing with the Flash Memory – Interfaces –Interfacing to High

Power Devices – Analog input interfacing – Analog output

interfacing.

UNIT- IV (10-Lectures)

REAL TIME OPERATING SYSTEM FOR MICRO

CONTROLLERS:

Real Time operating system – RTOS of Keil (RTX51) – Use of

RTOS in Design – Software development tools for Microcontrollers.

MICROCONTROLLER BASED INDUSTRIAL APPLICATIONS

Optical motor shaft encoders – Industrial control – Industrial process

control system – Prototype MCU based Measuring instruments.


16/32 - BIT MICROCONTROLLERS:

8096/80196 Family: Hardware – Memory map in Intel 80196 family

MCU system – I/O ports – Programmable Timers and High-speed

outputs and input captures – Interrupts.

ARM 32 Bit MCUs: Introduction to 16/32 Bit processors – ARM

architecture and organization – ARM / Thumb programming model –

ARM / Thumb instruction set.

TEXT BOOKS:

1. Raj Kamal, ―Microcontrollers Architecture, Programming,

Interfacing and System Design‖, 2nd Edition, Pearson Education,

2005.


M.TECH-VDES 13

2. Mazidi and Mazidi, ―The 8051 Microcontroller and Embedded

Systems‖, 4th impression, PHI, 2000.

REFERENCE BOOKS:

1. Kenneth J. Ayala, ―The 8051 Microcontroller‖, 3rd ed., Cengage

Learning, 2007.

2. A.V. Deshmukh, ―Microcontrollers (Theory & Applications)‖–,

6th Reprint, TMH, 2007.

3. John B. Peatman, ―Design with PIC Microcontrollers‖, 2nd

Edition,

Pearson Education, 2005.


M.TECH-VDES 14

ADVANCED DIGITAL SIGNAL PROCESSING


3 0 3

Pre requisites: Digital Signal Processing

Course Outcomes:At the end of the course the student will be able to

CO1: Comprehend the DFTs and FFTs.

CO2: Design and Analyze the digital filters.

CO3: Acquire the basics of multi rate digital signal processing.

CO4: Analyze the power spectrum estimation.

CO5: Comprehend the Finite word length effects in Fixed point DSP

Systems.


DISCRETE AND FAST FOURIER TRANSFORMS:

Properties of DFT, Linear Filtering methods based on the DFT,

Overlap-save, and Overlap -Add methods, frequency analysis of

signals, Radix-2 FFT and Split- Radix FFT algorithms The Goertzel

and Chirp Z transform algorithms.


DESIGN OF IIR AND FIR FILTERS:

Design of IIR filters using Butterworth &Chebyshev approximations,

frequency transformation techniques, structures for IIR systems –

cascade, parallel, lattice & lattice-ladder structures, Fourier series

method, Windowing techniques, design of digital filters based on least

– squares method, pade approximations, least squares design, wiener

filter methods, structures for FIR systems –cascade, parallel, lattice &

lattice-ladder structures.


MULTI RATE SIGNAL PROCESSING:

Decimation by a factor D, Interpolation by a factor I, Sampling rate

conversion by a rational factor I/D, Filter design & Implementation


M.TECH-VDES 15

for sampling rate conversion, filter bands, sub band coding, polyphase

filters.


POWER SPECTRAL ESTIMATION:

Estimation of spectra from finite duration observation of signals,

Non-parametric methods: Bartlett, Welch & Blackman & Tukey

methods. Relation between auto correlation & model parameters,

Yule-Waker & Burg Methods, MA & ARMA models for power

spectrum estimation.


ANALYSIS OF FINITE WORD LENGTH EFFECTS IN FIXED-

POINT DSP SYSTEMS:

Fixed, Floating Point Arithmetic – ADC quantization noise & signal

quality – Finite word length effect in IIR digital Filters – Finite word-

length effects in FFT algorithms.

TEXTBOOKS:

1. J.G.Proakis&D.G.Manolokis, ―Digital Signal Processing –

Principles, Algorithms Applications‖, PHI.

2. Alan V Oppenheim & Ronald W Schaffer, ―Discrete Time signal

processing‖, PHI.

REFERENCE BOOKS:

1. S.M.Kay, ―Modern spectral Estimation techniques‖, PHI,

1997.Emmanuel C. Ifeacher Barrie. W. Jervis, ―DSP – A Practical

Approach‖, Pearson Education.


M.TECH-VDES 16

CPLD AND FPGA ARCHITECTURE AND APPLICATIONS

(ELECTIVE – I)

Course Code: 15EC2205 L P C

3 0 3

Pre requisites: Programmable logic devices, combinational and

sequential logic circuit design.


CO1: Acquire Knowledge about various architectures and device

technologies of PLD‘s

CO2: Comprehend FPGA Architectures.

CO3: Describe FSM and different FSM techniques like petrinets&

different case studies.

CO4: Comprehends FSM Architectures and their applications.

CO5: Analyze System level Design and their application for

Combinational and Sequential Circuits.


PROGRAMMABLE LOGIC DEVICES:

COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLD):

ROM, PLA, PAL, PLD, PGA – Features, programming and

applications using complex programmable logic devices Altera series

– Max 5000/7000 series and Altera FLEX logic – 10000 series CPLD,

AMD‘s – CPLD (Mach 1 to 5); Cyprus FLASH 370 Device

Technology, Lattice LSI‘s Architectures – 3000 Series – Speed

Performance and in system programmability.

Field Programmable Gate Arrays (FPGA)

Field Programmable Gate Arrays – Logic blocks, routing architecture,

Design flow, Technology Mapping for FPGAs.


FPGA/CPLD ARCHITECTURES:

Xilinx XC4000 & ALTERA‘s FLEX 8000/10000 FPGAs: AT & T –

ORCA‘s (Optimized Reconfigurable Cell Array): ACTEL‘s – ACT-1,

2, 3 and their speed performance.


M.TECH-VDES 17


FINITE STATE MACHINES (FSM):

Top Down Design – State Transition Table, state assignments for

FPGAs. Problem of initial state assignment for one hot encoding.

Derivations of state machine charges. Realization of state machine

charts with a PAL.

Alternative realization for state machine chart using

microprogramming. Linked state machines. One – Hot state

machine, Petrinets for state machines – basic concepts, properties,

extended petrinets for parallel controllers. Finite State Machine –

Case Study, Meta Stability, Synchronization.


FSM ARCHITECTURES:

Architectures centered around non-registered PLDs. State machine

designs centered around shift registers. One – Hot design method.

Use of ASMs in One – Hot design. Application of One – Hot

method.


SYSTEM LEVEL DESIGN:

Controller, data path and functional partitions, Parallel adder cell,

parallel adder sequential circuits, counters, multiplexers, parallel

controllers.

TEXT BOOKS:

1. P.K.Chan& S. Mourad, ―Digital Design Using Field

Programmable Gate Array‖, prentice Hall (Pte), 1994.

2. S.Brown, R.Francis, J.Rose, Z.Vransic, ―Field Programmable Gate

Array‖, Kluwer Publications, 1992.

REFERENCE BOOKS:

1. J. Old Field, R.Dorf, ―Field Programmable Gate Arrays‖, John

Wiley & Sons, New York, 1995.

2. S.Trimberger, Edr. ―Field Programmable Gate Array Technology‖,

Kluwer Academic Publications, 1994.

3. Bob Zeidman, ―Designing with FPGAs &CPLDs‖,CMPBooks,

2002.


M.TECH-VDES 18

SYSTEM ON CHIP ARCHITECTURE

(ELECTIVE – I)


3 0 3

Pre requisites: Micro controllers, Embedded Systems


CO1: Comprehend abstraction in Hardware, SOC of ARM

Processor.

CO2: Evaluate and analyze system on chip RISC Machine, 3and5

stage Pipeline.

CO3: Develop programs on ARM Processor.

CO4: Knowledge of Memory Hierarchy ARM Interface.

CO5: Integrate the Knowledge of ARM for applications of System

on Chip.


INTRODUCTION TO PROCESSOR DESIGN:

Abstraction in hardware design, MUO a simple processor, Processor

design trade off, Design for low power consumption.


ARM PROCESSOR AS SYSTEM-ON-CHIP:

Acorn RISC Machine – Architecture inheritance –ARM programming

model – ARM development tools – 3 and 5 stage pipeline ARM

organization – ARM instruction execution and implementation –

ARM Co-processor interface.


ARM ASSEMBLY LANGUAGE PROGRAMMING:

ARM instruction types – data transfer, data processing and control

flow instructions – ARM instruction set – co-processor instructions.

Architectural Support for High Level Language - Data types –

Abstraction in software design – Expressions – Loops – Functions

and Procedures – Conditional Statements – Use of Memory.


M.TECH-VDES 19


MEMORY HIERARCHY:

Memory size and speed –on chip memory –caches-cache design an

example-Memory management

Architectural Support for System Development-Advanced

Microcontroller bus architecture-ARM Memory Interface-ARM

Reference Peripheral specification –Hardware System Prototyping

tools – Emulator –Debug architecture.


ARCHITECTURAL SUPPORT FOR OPERATING SYSTEM:

An introduction to Operating Systems-ARM System Control

coprocessor-CP15 Protection unit registers-ARM protection unit-

CP15 MMU registers-ARM Architecture-Synchronization-Context

Switching input and output.

TEXT BOOKS:

1. Steve Furber, ―ARM system on chip Architecture‖, 2nd

ed., Addison

Wesley Professional, 2000.

REFERENCES:

1. Michael J Flynn,Wayne Luck, ―Computer System Design: System

onChip‖, Wiley India Edition.

2. PrakashRashinkar, Peter Paterson and Leena Singh L., ―System on

Chip Verification – Methodologies and Techniques‖, Kluwer

Academic Publisher, 2001.

3. Ricardo Reis, ―Design of System on a Chip: Devices and

Components‖ 1st ed., Springer, 2004.


M.TECH-VDES 20

SYSTEM MODELLING&SIMULATION

(ELECTIVE – I)


3 0 3

Course Outcomes: At the end of the course the student will be able

to

CO1: Predict the modeling and simulation concepts for dynamic

systems using variety of formalisms.

CO2: Interpret various simulation packages with programming

languages to increase model Validity and credibility.

CO3: Demonstrate various timing models and event driven models

to effectively simulate queuing systems.

CO4: Extrapolate different markov processes to illustrate the

behavior of probabilistic Systems and state machines.

CO5: Justify the importance of system optimization using modeling

and simulation methods.


INTRODUCTION:

Basic Simulation Modeling, Systems, Models and Simulation,

Discrete Event Simulation, Simulation of single server queing system,

Simulation of Inventory System, Alternative approach to modeling

and simulation.


SIMULATION SOFTWARE AND MODELS:

Comparison of simulation packages with Programming languages,

Classification of Software, Desirable Software features, General

purpose simulation packages – Arena, Extend and others, Object

Oriented Simulation, Examples of application oriented simulation

packages.

Guidelines for determining levels of model detail, Techniques for

increasing model validity and credibility.


M.TECH-VDES 21


TIME AND EVENT DRIVEN MODELS:

Modeling input signals, delays, System integration, Linear Systems,

Motion control models, Numerical Experimentation.

Simulation diagrams, Queing theory, simulating queing systems,

Types of Queues, Multiple servers.


MARKOV PROCESS:

Disturbance signals, State Machines, Petri Nets & Analysis, System

encapsulation.

Probabilistic systems, Discrete Time Markov processes, Random

walks, Poisson processes, the exponential distribution, simulating a

poison process, Continuous-Time Markov processes.


SYSTEM OPTIMIZATION:

System Identification, Searches, Alpha/beta trackers,

Multidimensional Optimization, Modeling and Simulation

methodology.

TEXT BOOKS:

1. Frank L. Severance, ―System Modeling & Simulation, an

Introduction‖, John Wiley & Sons, 2001.

2. Averill M. Law, W. David Kelton, ―Simulation Modeling and

Analysis‖, TMH, 3rd

Edition, 2003.

REFERENCE BOOKS:

1. Geoffery Gordon, ―Systems Simulation‖, PHI, 1978.


M.TECH-VDES 22

DATA COMMUNICATIONS

(ELECTIVE – I)


3 0 3


CO1: Describe various transmission modes, Network topologies and

Error detection and correction methods.

CO2: Design Multiplexing techniques such as TDM and FDM.

CO3: Explain Switching mechanisms for data transmission.

CO4: Demonstrate Data communication protocols.

CO5: Discuss Line Protocols and Congestion Protocols.


DATA COMMUNICATION METHODS: Data Communication Circuits, point-to-point, Multi-point

configurations and Topologies, Broadcasting, multicasting

configuration, transmission modes, 2-wire and 4-wire operations,

Codes, Error detection methods, Error correction methods, Character

synchronization.


SWITCHING TECHNIQUES: Circuit Switching, Message Switching and Packet Switching

principles, Virtual circuit and datagram techniques, X.25 and frame

relay.


DIGITAL MULTIPLEXING: Multiplexers, Statistical multiplexer, Concentrator, front-end

communication processor, Digital PBX, long haul communication

with FDM, Hybrid data, TDM, T1, E1 carrier systems, CCITT-TDM

carrier system, CODEC chips, Digital hierarchy, Line Encoding,

Frame Synchronization.


M.TECH-VDES 23


DATA COMMUNICATION PROTOCOLS:

Asynchronous protocols, Synchronous protocols, Bisync Protocol,

SDLC, HDLC-Frame format, ATM Frame format, Flow control and

error control.

UNIT – V (10-Lectures)

LINE PROTOCOLS AND CONGESTION CONTROL: Line protocols: Basic mode, Half-duplex point-to-point protocol,

Half-Duplex Multi-Point Protocol, Full-Duplex Protocols, Polling,

Roll Call and Hub Polling, Traffic management, Congestion control

in packet switching networks and Frame relay.

TEXT BOOKS:

1. W. TOMASI, ―Advanced Electronic Communications Systems‖,

PHI.

2. William Stallings, ―Data and Computer Communications‖, 8/e,

PEI, 2007.

REFERENCE BOOKS:

1. T. HOUSELY, ―Data Communications and Teleprocessing

Systems‖, PHI.

2. B.A.Forouzon, ―Data and Computer Networking

Communications‖,3rd

TMH.

3. B.Gerd Keiser, ―Optical Communications‖, PHI.


M.TECH-VDES 24

ADVANCED TECHNICAL COMMUNICATON SKILLS

Course Code: 15HE2101 L P C

0 3 2

Course Outcomes:

CO1: Use language fluently, accurately and appropriately in group

discussions and debates

CO2: Comprehending listening to communicate effectively in cross-

cultural contexts.

CO3: Write project proposals, reports, dissertations

CO4: Demonstrate interview skills learnt.

CO5: Demonstrate soft skills learnt.

SYLLABUS:

1. Group Discussion

2. Debate

3. Technical presentation

4. Situational dialogues for Negotiation and conflict resolution

5. Interview Skills

6. Report Writing

7. Project Proposal

8. Detailed project Report

9. Research Article writing

10. Dissertation

11. Telephonic communication

REFERENCES:

Sharon Gerson, Steven Gerson, Technical Communication: Process

and Product Paperback Longman edition, 2013.

Simon Sweeny, “English for Business Communication”, CUP,

FirstSouthAsianEdition,2010.

Stella Cottrel, Dissertations and Project Reports: A Step by Step

Guide, Palgrave Macmillan Paperback, 2014.

James D. Lester, James D. Lester Jr.Writing Research Papers: A

http://www.amazon.com/s/ref=dp_byline_sr_book_1?ie=UTF8&field-author=James+D.+Lester+%28Deceased%29&search-alias=books&text=James+D.+Lester+%28Deceased%29&sort=relevancerank

http://www.amazon.com/s/ref=dp_byline_sr_book_2?ie=UTF8&field-author=James+D.+Lester+Jr.&search-alias=books&text=James+D.+Lester+Jr.&sort=relevancerank


M.TECH-VDES 25

Complete Guide ,Longman,15th Edition, 2014.

M.AshrafRizvi, “Effective Technical Communication”, Tata

McGraw-Hill Publishing Company Ltd. 2005.

Meenakshi Raman &Sangeeta Sharma, “Technical

Communication”,OxfordUniversityPress,2012.


M.TECH-VDES 26

HDL PROGRAMMING LABORATORY


0 3 2

Pre requisites: VHDL, Verilog, Switching Theory and Logic Design.

Course outcomes:At the end of the Course, Students will be able to

CO1: Design, simulate and synthesize combinational and sequential

circuits using VHDL.

CO2: Design, simulate and synthesize digital circuits using Verilog

HDL.

CO3: Get hands on experience on XILINX software.

CO4: Calculate delay and area for digital circuits using CADENCE

software tool.

CO5: Implement digital systems on FPGAs.

LIST OF EXPERIMENTS

1. 16 X 1 MULTIPLEXER

2. 4-Bit ALU

3. 8-Bit UP/DOWN COUNTER

4. 32 X 8 ROM

5. SEQUENCE DETECTOR 101( using Mealy Machine)

6. SEQUENCE DETECTOR 1011( using Moore Machine)

7. DECODERS

8. 8-Bit SHIFT REGISTER

9. BCD ADDER

10. PARITY CHECKER

11. SEQUENCE GENERATOR

12. 8-BIT COMPARATOR

13. BARREL SHIFTER

14. UNIVERSAL SHIFT REGISTER

STEPS FOLLOWED DURING EXPERIMENTATION

1. Digital Circuits Description using Verilog and VHDL

2. Verification of the Functionality of Designed circuits using

function Simulator.


M.TECH-VDES 27

3. Timing simulation for critical path time calculation.

4. Synthesis of Digital circuits.

5. Implementation of Designed Digital Circuits using FPGA and

CPLD devices.

Syllabi for

II-Semester


M.TECH-VDES 28

EMBEDDED COMPUTING SYSTEMS


3 0 3

Pre requisites: Microcontroller & Embedded Systems.


CO1: Comprehend concepts of UML architectures, CPU

architectures BUS architectures for Embedded computations.

CO2: Design of generic compilers for Embedded systems and its test

procedures.

CO3: Elucidate operating system concepts.

CO4: Synthesize real time task scheduling context switching.

CO5: Optimize design aspects of real-time operating system,

modeling and working on real-time environment.


INTRODUCTION TO DESIGN AND ARCHITECTURE:

Requirements, specifications, structural and behavioral descriptions,

UML; Embedded Processors: RISC, super scalar, and VLIW

architectures, memory organization and Instruction level parallelism;

CPU architectures: Input/output, interrupts, modes, cache memories

Embedded bus architectures: Bus architectures and transactions,

Serial interconnects, Networked embedded systems: Bus protocols,

I2C bus and CAN bus; Internet-Enabled Systems, Design Example-

Elevator Controller.


DESIGN OF COMPILERS:

Compilers and optimization, Testing, Performance Analysis,

Hardware Accelerators: FPGA architectures, RISC IP Cores, Verilog

HDL.


M.TECH-VDES 29


OPERATING SYSTEMS &RTOS-I:

Operating system concepts: Embedded operating systems ,Network

operating systems, Layers, functions kernel, Tasks, Scheduling

Thread, Interrupt process, communication, Device drivers, codes,

pseudo codes for OS.Introduction, Modeling Timing constraints

Scheduling Real-Time Tasks: Types of Schedulers Table-driven

scheduling cyclic schedulers EDF RMA.


OPERATING SYSTEMS & RTOS-II:

Handling Resource sharing among real-time tasks Scheduling Real-

Time Tasks in Multiprocessor and Distributed systems Commercial

Real-time operating systems: Tasks, context switches, Operating

system support (inter-process communication, networking),

Scheduling, and Development environment.

UNIT-V (10-Lectures) DESIGN COMPUTATIONS & EMBEDDED SYSTEM APPLICATION:

Database Systems, Product design process and testing Design

Computations Design challenge – optimizing design metrics,

processor technology, design technology; real time-operating system:

system modeling, static scheduling, Priority drive scheduling,

Synchronization & mutual exclusion (real-time and non-real-time);

H/W and S/W co-design; embedded multiprocessor.

TEXT BOOKS:

1. W. Wolf, ―Computers as Components: Principles of Embedded

Computer System Design‖

2. LYLA B DAS,‖Embedded Systems‖, Pearson Education,1ST

Edition,2012.

REFERENCES:

1. Rajib Mall, ―Real-Time Systems: Theory and Practice,‖ Pearson,

2008.

2. Jane W. Liu, ―Real-Time Systems‖ Pearson Education, 2001.

3. Krishna and Shin, ―Real-Time Systems,‖ Tata McGraw Hill. 1999.


M.TECH-VDES 30

ANALOG IC DESIGN


3 0 3

Pre requisites: Electronic devices and circuits, Linear IC

Applications.

Course Outcomes:At the end of the Course, Students will be able to

CO1: Analyze small signal modeling of single stage MOSFET

amplifiers with current mirrors.

CO2: Design two stage CMOS operational amplifiers.

CO3: Illustrate advanced current mirrors and comparators.

CO4: Outline concepts of sample& Hold circuits and switched

capacitor circuits.

CO5: Design and analyze CMOS A/D and D/A data converters of

different types.


MOS MODELING AND CURRENT MIRRORS:

Large Signal and Small Signal Modeling of MOSFET, Advanced

MOS Modeling, Simple CMOS Current Mirror, Common Source,

Common Drain, Common Gate amplifiers, Source degenerated

current mirrors, High Output Impedance Current Mirrors, cascade

gain stage, MOS Differential pair and gain stage, frequency response.


BASIC OPERATIONAL AMPLIFIER DESIGN AND

COMPENSATION:

Two Stage CMOS Operational Amplifier, opamp gain, frequency

response, slew rate, systematic offset voltage, Feedback and

Operational Amplifier Compensation-linear settling time, opamp

compensation, compensating the two stage opamp, lead

compensation, compensation independent of process and temperature.


Advanced Current Mirrors & Comparators: Advanced Current


M.TECH-VDES 31

Mirrors Folded-Cascode Operational Amplifier, Current Mirror

Operational Amplifier, Linear settling time revisited, Fully

Differential Operational Amplifier. Common Mode Feedback

Circuits, Current Feedback Operational Amplifier. Comparators:

using an opamp for a comparator, Charge Injection Error, Latched

Comparators, CMOS and Bi CMOS Comparators.


SAMPLE AND HOLD &SWITCHED CAPACITOR CIRCUITS:

Sample & Hold Circuits: Performance of Sample & Hold Circuit,

MOS Sample and Hold Circuits, CMOS, BiCMOS Sample and Hold

Circuits. Switched Capacitor Circuits: Basic Operation and Analysis,

First Order and Biquard Filters, Charge Injection, Switched Capacitor

Gain Circuit, Correlated Double Sampling Techniques. Other

Switched Capacitor Circuits.


NYQUIST RATE D/A &A/D CONVERTERS:

Introduction to ideal data converters, Quantization Noise,

Performance Limitations, Nyquist rate D/A converters: Decoders

Based Converters, Binary Scaled Converters, Thermometer-code

converters, Hybrid Converters. Nyquist rate A/D converters:

Integrating, Successive Approximation, Cyclic, Flash Type, Two

Step, Interpolating, Folding, Pipelined A/D Converters.

TEXT BOOKS:

1. D.A.John& Ken Martin, ―Analog Integrated Circuit Design‖, John

Wiley, 1997.

REFERENCE BOOKS:

1. Paul R Gray &Robert G Meyer,‖ Analysis and Design of Analog

Integrated Circuits‖, second edition John Wiley & Sons, 4th

edition,

2009.

2. BehzadRazavi, ―Design of Analog CMOS Integrated Circuits‖, The

McGraw Hill, reprint 2008.

3. Gregolian&Temes, ―Analog MOS Integrated Circuits‖, John

Wiley, 1986.

LOW POWER VLSI DESIGN


M.TECH-VDES 32


3 0 3

Pre requisites: Electronic Devices and Circuits, Digital

ICApplications, VLSI Design.

Course outcomes:At the end of the course the student will be able to

CO1: Illustrate the Design limitations of Low Power Design and

Evolution of SOI Technologies.

CO2: Describe various integration and isolation techniques for

MOS/Bi-CMOS Technologies.

CO3: Obtain Proficiency in parameter extraction of Bi-polar,

MOSFETs using SPICE and Advanced MOSFET models.

CO4: Design and analyze Conventional CMOS and Bi-CMOS Logic

Gates

CO5: Design low voltage, low power Bi-CMOS logic circuits to

achieve High Performance.

UNIT- I (10-Lectures)

INTRODUCTION TO LOW POWER DESIGN: Introduction, Low Power design- an overview, low power design

limitations: power supply voltage, threshold voltage, scaling,

interconnect wires, Silicon-on-Insulator (SOI) From Devices to

Circuits.


MOS/BI-CMOS PROCESS TECHNOLOGY AND

INTEGRATION:

The Realization of Bi-CMOS processes, Bi-CMOS manufacturing

and Integration Considerations, Isolation in Bi-CMOS, Deep

submicron processes, Future trends and directions of CMOS/Bi-

CMOS processes.


M.TECH-VDES 33

UNIT-III (10-Lectures) DEVICE BEHAVIOR AND MODELING:

The MOS (FET) Transistor, The Bipolar (Junction) transistor,

MOSFET SPICE models, Advanced, Bipolar Spice models, MOSFET

in Hybrid Mode Environment-Surface p-Channel for Sub-Half-

Micron Devices, Device Fabrication, Model Parameters Extraction,

Sub-Half-Micron D.C. Model Formulation.


CONVENTIONAL CMOS AND BI-CMOS LOGIC GATES:

Conventional CMOS Logic Gates, Conventional Bi-CMOS Logic

Gate, Bi-CMOS Circuits Utilizing Lateral pnp BJTs in pMOS

structures, Performance evaluation and Comparison.


LOW- VOLTAGE, LOW POWER LOGIC CIRCUITS:

Merged Bi-CMOS digital circuits, Full-Swing Multi Drain/Multi

collector Complementary Bi-CMOS Buffers, Quasi-Complementary

Bi-CMOS Digital Circuits, FULL-Swing Bi-CMOS/Bi-NMOS

Digital circuits employing Schottky Diodes, Feedback-Type Bi-

CMOS Digital Circuits, High-Beta Bi-CMOS Digital Circuits,

Transiently Saturated Full-Swing Bi-CMOS Digital Circuits,

Bootstrapped-type Bi-CMOS Digital circuits, ESD-free Bi-CMOS

Digital circuit -circuit operation and comparative Evaluation.

Evolution of Latches and Flip-Flops, Quality Measures for Latches

and Flip-Flops, Design perspective.

TEXT BOOK:

1. KiatSeng Yeo, Samir S. Rofail, Wang-Ling Goh, ―CMOS/Bi

CMOS ULSI Low Voltage Low Power‖, Pearson Education Asia

1st Indian reprint, 2002.

REFERENCE BOOKS:

1. J.Rabaey, ―Digital Integrated circuits‖, PH. N.J 1996, 2nd Edition

2. Sung-mokang and yusufleblebici, ―CMOS Digital ICs‖, TMH,

3rd

Edition, 2003.

3. Parhi, ―VLSI DSP Systems‖, John Wiley & sons, 2003 Reprint


M.TECH-VDES 34

DIGITAL IC DESIGN


3 0 3

Pre requisites: VLSI Technology and Design.


CO1: Describe the various design entities.

CO2: Analyze the depth of designing a Digital IC and use the

concept of logical effort for Transistor sizing.

CO3: Describe the static and dynamic behavior of CMOS.

CO4: Distinguish between Static CMOS design and Dynamic

CMOS design.

CO5: Design Logic gates, Flip-flops and Registers.


INTRODUCTION:

Historical Perspective, Issues in Digital Integrated Circuit Design,

Quality Metrics of a Digital Design: Cost of an Integrated Circuit,

Functionality and Robustness, Performance, Power and Energy

Consumption.


MOS TRANSISTOR:

The MOS Transistor under Static Conditions, Dynamic Behavior, The

Actual MOS Transistor—Some Secondary Effects, SPICE Models for

the MOS Transistor, Method of Logical Effort for transistor sizing.

WIRE:

Introduction, A First Glance, Interconnect Parameters - Capacitance,

Resistance, and Inductance, Electrical wire models, SPICE wire

models.


THE CMOS INVERTER:

Introduction, The Static CMOS Inverter — An Intuitive Perspective,

Evaluating the Robustness of the CMOS Inverter: The Static

Behavior, Switching Threshold, Noise Margins, Robustness


M.TECH-VDES 35

Revisited, Performance of CMOS Inverter: The Dynamic Behavior,

Computing the Capacitances, Propagation Delay: First-Order

Analysis, Propagation Delay from a Design Perspective, Power,

Energy, and Energy-Delay: Dynamic Power Consumption, Static

Consumption, Perspective: Technology Scaling and its Impact on the

Inverter Metrics .


DESIGNING COMBINATIONAL LOGIC GATES IN CMOS:

Introduction, Static CMOS Design: Complementary CMOS, Ratioed

Logic, Pass-Transistor Logic, Dynamic CMOS Design: Dynamic

Logic- Basic Principles, Speed and Power Dissipation of Dynamic

Logic, Issues in Dynamic Design, Cascading Dynamic Gates,

Perspectives: How to Choose a Logic Style, Designing Logic for

Reduced Supply Voltages


DESIGNING SEQUENTIAL LOGIC CIRCUITS:

Introduction, Timing Metrics for Sequential Circuits, Classification of

Memory Elements, Static Latches and Registers: The Bistability

Principle, Multiplexer-Based Latches Master-Slave Edge-Triggered

Register, Low-Voltage Static Latches, Static SR Flip-Flops—Writing

Data by Pure Force, Dynamic Latches and Registers: Dynamic

Transmission-Gate Edge-triggered Registers ,C2MOS—A Clock-

Skew Insensitive Approach, True Single-Phase Clocked Register

(TSPCR).Pipelining: An approach to optimize sequential circuits,

Latch- vs. Register-Based Pipelines, NORA-CMOS—A Logic Style

for Pipelined Structures, Non-Bistable Sequential Circuits: The

Schmitt Trigger, Monostable Sequential Circuits, Astable Circuits,

Perspective: Choosing a Clocking Strategy.

TEXT BOOKS:

1. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, ―Digital

Integrated Circuits – A design perspective‖, Second Edition, PHI,

2003.


M.TECH-VDES 36

REFERENCES:

1. Jackson & Hodges, ―Analysis and Design of Digital Integrated

circuits‖. 3rd Ed. TMH Publication, 2005.

2. Ken Martin, ―Digital Integrated Circuit Design‖, Oxford

Publications, 2001.

3. Sedra and Smith, ―Microelectronic Circuits‖ 5/e, Oxford

Publications, 2005.

4. S. M. Kang & Y. Leblebici,”CMOS Digital Integrated Circuits‖,

Third Edition, McGraw Hill, 2003.


M.TECH-VDES 37

DSP PROCESSORS & ARCHITECTURE


3 0 3

Pre requisites: Knowledge of signals and systems, convolution

methods, digital signal processing concepts must be known.

Course Outcomes: At the end of the course the student will be able

to

CO1: Comprehends the knowledge & concepts of digital signal

processing techniques.

CO2: Acquire knowledge of DSP computational building blocks and

knows how to achieve speed in DSP architecture or processor.

CO3: Implementation of basic DSP algorithms using DSP

processors.

CO4: Acquire knowledge about various addressing modes of DSP

TMS320C54XX and able to program DSP processor.

CO5: Learn about interfacing of serial and parallel communication

devices.


INTRODUCTION:

Introduction, Digital signal-processing system, the sampling process,

discrete time sequences. Discrete Fourier Transform (DFT) and Fast

Fourier Transform (FFT), Linear time-invariant systems, Digital

filters, Decimation and interpolation, Number formats for signals and

coefficients in DSP systems, Dynamic Range and Precision, Sources

of error in DSP implementations, A/D Conversion errors, DSP

Computational errors, D/A Conversion Errors.


ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES:

Basic Architectural features, DSP Computational Building Blocks,

Bus Architecture and Memory, Data Addressing Capabilities, Address

Generation Unit, Programmability and Program Execution, Speed

Issues, Hardware looping, Interrupts, Stacks, Relative Branch support,


M.TECH-VDES 38

Pipelining and Performance, Pipeline Depth, Interlocking, Branching

effects, Interrupt effects, Pipeline Programming models.


PROGRAMMABLE DIGITAL SIGNAL PROCESSORS:

Commercial Digital signal-processing Devices, Data Addressing

modes of TMS320C54XX DSPs, Data Addressing modes of

TMS320C54XX Processors, Memory space of TMS320C54XX

Processors, Program Control, TMS320C54XX instructions and

Programming, On-Chip Peripherals, Interrupts of TMS320C54XX

processors, Pipeline Operation of TMS320C54XX Processors.


IMPLEMENTATIONS OF BASIC DSP ALGORITHMS:

The Q-notation, FIR Filters, IIR Filters, Interpolation Filters,

Decimation Filters, PID Controller, Adaptive Filters, An FFT

Algorithm for DFT Computation, A Butterfly Computation, Overflow

and scaling, Bit-Reversed index generation, An 8-Point FFT

implementation on the TMS320C54XX, Computation of the signal

spectrum.


INTERFACING MEMORY AND I/O PERIPHERALS TO

PROGRAMMABLE DSP DEVICES:

Memory space organization, External bus interfacing signals,

Memory interface, Parallel I/O interface, Programmed I/O, Interrupts

and I/O, Direct memory access (DMA).

A Multichannel buffered serial port (McBSP), McBSP Programming,

a CODEC interface circuit, CODEC programming, A CODEC-DSP

interface example.

TEXT BOOKS:

1. Avtar Singh and S. Srinivasan, ―Digital Signal Processing‖

Thomson Publications, 2004.

2. Lapsley et al., ―DSP Processor Fundamentals, Architectures &

Features‖, S. Chand & Co, 2000.


M.TECH-VDES 39

REFERENCES

1. B. Venkata Ramani and M. Bhaskar, ―Digital Signal Processors,

Architecture, Programming and Applications‖ TMH, 2004.

2. Jonatham Stein, ―Digital Signal Processing‖, John Wiley, 2000


M.TECH-VDES 40

ELECTRONIC DESIGN AUTOMATION TOOLS

(ELECTIVE – II)


3 0 3

Prerequisites:PSPICE, VERILOG, VHDL


CO1: Illustrate different simulations and delay models which are

available for HDL.

CO2: Classify the different synthesis using CAD tools.

CO3: Design and Analyze Analog and Digital Circuits Using

PSPICE model of Transistor.

CO4: Describe about Analog, Digital & Mixed Signal Simulators.

CO5: Illustrate PCB Design and also describe the tools used for

PCB design.


SIMULATION USING HDLS:

Simulation-Types of Simulation, Logic Systems, Working of Logic

Simulation, Cell Models, Delay Models State Timing Analysis,

Formal Verification, Switch-Level Simulation, Transistor-Level

Simulation.


SYNTHESIS USING HDLS:

Verilog and Logic Synthesis, VHDL and Logic Synthesis, Memory

Synthesis, FSM Synthesis, Memory Synthesis, Performance-Driven

Synthesis.

CAD Tools for Simulation and Synthesis: Modelsim and Leonardo

Spectrum


CIRCUIT DESIGN AND SIMULATION USING PSPICE:

Pspice Models For Transistors, A/D & D/A Sample And Hold

Circuits etc., And Digital System Building Blocks, Design And

Analysis Of Analog And Digital Circuits Using PSPICE.


M.TECH-VDES 41


AN OVERVIEW OF MIXED SIGNAL VLSI DESIGN:

Fundamentals Of Analog And Digital Simulation, Mixed Signal

Simulator Configurations, Understanding Modeling, Integration To

CAD Environments.


TOOLS FOR PCB DESIGN AND LAYOUT:

An Overview of High Speed PCB Design, Design Entry, Simulation

and Layout Tools for PCB.Introduction to Orcad PCB Design Tools.

TEXTBOOKS:

1. J.Bhaskar, ―A Verilog Primer‖, BSP, 2003.

2. J.Bhaskar, ―A Verilog HDL Synthesis‖, BSP, 2003

3. M.H.RASHID, ―SPICE FOR Circuits and Electronics Using

PSPICE‖, (2/E) (1992) Prentice Hall.

REFERENCE BOOKS:

1. ORCAD: Technical Reference Manual, Orcad, USA.

2. SABER, ―Technical Reference Manual‖, Analogy Nic, USA.

3. M.J.S.SMITH, ―Application-Specific Integrated Circuits‖, (1997).

Addison Wesley

4. J.Bhaskar, ―A VHDL Synthesis Primer‖, BSP, 2003.


M.TECH-VDES 42

IMAGE AND VIDEO PROCESSING

(ELECTIVE – II)


3 0 3

Pre requisites: Signals and Systems, Digital Signal Processing.


CO1: Comprehend the image processing fundamentals and

enhancement techniques in spatial and frequency domain.

CO2: Describe the color image fundamentals, models and various

restoration techniques.

CO3: Design and Analyze the image compression systems.

CO4: Outline the various image segmentation and morphology

operations.

CO5: Comprehend the basics of video processing and video coding.


INTRODUCTION AND IMAGE ENHANCEMENT:

Digital image fundamentals, Concept of pixels and gray levels,

Applications of image processing, Introduction to image

enhancement, spatial domain methods: point processing - intensity

transformations, histogram processing, image averaging, image

subtraction, Spatial filtering- smoothing filters, sharpening filters,

Frequency domain methods: low pass filtering, high pass filtering,

Homomorphic filtering.


IMAGE RESTORATION:

Introduction to Image restoration, Degradation model, Restoration in

the presence of Noise only-Spatial Filtering, Periodic Noise reduction

by Frequency domain Filtering, Algebraic approaches- Inverse

filtering, Wiener filtering, Constrained Least squares restoration.

Color Image processing:

Introduction, Fundamentals of Color image processing: color models -

RGB, CMY, YIQ, HSI, Pseudo color image processing - intensity


M.TECH-VDES 43

slicing, gray level to color transformation, Basics of Full Color image

processing.


IMAGE COMPRESSION:

Introduction, Need for image compression, Redundancy in images,

Classification of redundancy in images, image compression scheme,

Classification of image compression schemes, Huffman coding,

Arithmetic coding, Predictive coding, Transformed based

compression, Image compression standards, Wavelet-based image

compression.


IMAGE SEGMENTATION:

Introduction to image segmentation, Detection of discontinuities -

point, line and edge and combined detection; Edge linking and

boundary description - local and global processing using Hough

transform Thresholding -Region oriented segmentation - basic

formulation, region growing by pixel aggregation, region splitting and

merging.

Image Morphology:

Introduction to Morphology, Dilation and Erosion, Opening and

Closing, Hit-or-Miss Transformation, Some Basic Morphological

Algorithms.


DIGITAL VIDEO & CODING:

Basics of Video, Time-varying Image formation Models, Spatio-

Temporal Sampling, Optical flow, General methodologies, Overview

of coding systems, Video Compression Standards.

TEXT BOOKS:

1. R.Gonzalez, R.E.Woods, ―Digital Image Processing‖, 3rd

Edition,

Pearson Education, India, 2009.

2. M. Tekalp, ―Digital Video Processing‖, Prentice-Hall, 1995.


M.TECH-VDES 44

REFERENCES:

1. Rafael C. Gonzalez, Richard E Woods and Steven L. Eddins,

―Digital Image Processing using MAT LAB‖ , Pearson Edu., 2004.

2. Bovik, ―Handbook of Image & Video Processing‖, Academic

Press, 2000

3. Yao Wang, JornOstermann and Ya Qin Zhang, ―Video Processing

and Communications‖, Prentice Hall Publishers, 2002.


M.TECH-VDES 45

NEURAL NETWORKS AND FUZZY LOGIC CONTROL

(ELECTIVE – II)


3 0 3

Pre requisites:Set Theory


CO1: Comprehend the concepts of feed forward neural networks

CO2: Analyze the various feedback networks.

CO3: Comprehend the concept of fuzziness involved in various

systems and fuzzy set theory.

CO4: Understand the fuzzy logic control and adaptive fuzzy logic

and to design the fuzzy Control using genetic algorithm.

CO5: Analyze the application of fuzzy logic control to real time

systems.

UNIT - I (10-Lectures)

ARCHITECTURES

Introduction –Biological neuron-Artificial neuron-Neuron modeling-

Learning rules-Single layer-Multi layer feed forward network-Back

propagation-Learning factors.

UNIT - II (10-Lectures)

NEURAL NETWORKS FOR CONTROL

Feedback networks-Discrete time hop field networks-Schemes of

neuro –control, identification and control of dynamical systems-case

studies (Inverted Pendulum, Articulation Control).


FUZZY SYSTEMS Classical sets-Fuzzy sets -Fuzzy relations- Fuzzification –

Defuzzification- Fuzzy rules.


M.TECH-VDES 46

UNIT - IV (10-Lectures)

FUZZY LOGIC CONTROL

Membership function – Knowledge base-Decision –making logic –

Optimizations of membership function using neural networks-

Adaptive fuzzy systems-Introduction to generate to genetic algorithm.

UNIT - V (10-Lectures)

APPLICATION OF FLC

Fuzzy logic control-Inverted pendulum-Image processing-Home

Heating system-Blood pressure during anesthesia-Introduction to

neuro fuzzy controller.

TEXT BOOKS:

1. Kosko, B,Neural Networks and Fuzzy Systems:A Dynamical

Approach to Machine Intelligence‖ Prentice Hall,New Dehli,2004.

2. Timothy J Ross, ―Fuzzy Logic with Engineering Applications,‖

John Willey and Sons, West Sussex, England, 2005.

REFERENCE BOOKS:

1. Jack M. Zurada, ―Introduction to Artificial Neural Systems,‖ PWS

Publishing Co., Boston, 2002.

2. Klir G.J. &Folger T.A., ―Fuzzy sets,Uncertainty and Information”

Prentice –Hall of India Pvt. Ltd., New Delhi,2008.

3. Zimmerman H.J., ―Fuzzy set theory and its Applications,‖ Kluwer

Academic Publishers Dordrecht, 2001.

4. Driankov,Hellendroonb , ―Introduction to fuzzy control‖,Narosa

Publishers,2001

5. LauranceFausett,Englewood cliffs. N.J., ―Fundamentals of Neural

Networks,‖ Pearson Education,New Delhi,2008.


M.TECH-VDES 47

ALGORITHMS FOR VLSI DESIGN AUTOMATION

(ELECTIVE – II)


3 0 3

Prerequisites: VLSI Design


CO1: Modify the CAD design problems using algorithmic

paradigms

CO2: Illustrate Backend Design Concepts

CO3: Illustrate about Modeling and Simulation of Digital Circuits

CO4: Summarize about different Logic Synthesis and its

verification

CO5: Analyze physical design problems of FPGA,MCM


PRELIMINARIES& GENERAL PURPOSE METHODS FOR

COMBINATIONAL OPTIMIZATION:

Introduction to Design Methodologies, Design Automation tools,

Algorithmic Graph Theory, Computational Complexity, Tractable and

Intractable Problems

General Purpose Methods for Combinational Optimization:

Backtracking, Branch and Bound, Dynamic Programming, Integer

Linear Programming, Local Search, Simulated Annealing, Tabu

search, Genetic Algorithms.

UNIT- II (10-Lectures)

LAYOUT COMPACTION:

Design Rules, Symbolic Layout, Problem Formulation, Algorithms

for Constraint –graph Compaction.

Placement and Partitioning:

Circuit Representation, Wire-length Estimation, Types of Placement

Problem, Placement Algorithms, Partitioning

Floor Planning:

Floor Planning Concepts, Shape Functions and Floor plan Sizing


M.TECH-VDES 48

Routing:

Types of Local Routing Problems, Area Routing, Channel Routing,

Introduction to Global Routing, Algorithms for Global Routing.


MODELLING AND SIMULATION:

Gate Level Modeling and Simulation, Switch level modeling and

simulation.

UNIT- IV (10-Lectures)

LOGIC SYNTHESIS AND VERIFICATION:

Basic issues and Terminology, Binary –Decision diagram, Two –

Level Logic Synthesis.

High Level Synthesis: Hardware Models, Internal representation of

the input algorithm, Allocation, Assignment and Scheduling, Some

Scheduling Algorithms, Some aspects of Assignment problem, High –

level Transformations.

UNIT- V (10-Lectures)

PHYSICAL DESIGN AUTOMATION OF FPGA’S AND

MCM’S:

FPGA technologies, Physical Design cycle for FPGA‘s partitioning

and routing for segmented and staggered models.

Physical Design Automation of MCM’s:

MCM technologies, MCM physical design cycle, Partitioning,

Placement – Chip array based and full custom approaches, Routing –

Maze routing, Multiple stage routing, Topologic routing, Integrated

Pin –Distribution and routing, routing and programmable MCM‘s.

TEXT BOOKS:

1. S.H.Gerez, ―Algorithms for VLSI Design Automation‖, WILEY

student edition, Johnwiley& Sons (Asia) Pvt.Ltd. 1999.

2. NaveedSherwani, ―Algorithms for VLSI Physical Design

Automation‖, Springer International Edition 3rd

edition, , 2005


M.TECH-VDES 49

REFERENCES:

1. Hill &Peterson, ―Computer Aided Logical Design with Emphasis

on VLSI‖, John Wiley, 1993.

2. Wayne Wolf, ―Modern VLSI Design: Systems on silicon‖, Pearson

Education Asia,2ND

Edition, 1998.


M.TECH-VDES 50

EMBEDDED SYSTEMS LAB


0 3 2

Pre requisites: Microcontrollers Theory, Embedded Systems Theory

Course outcomes: At the end of the course the student will be able to

CO1.Generate arbitrary wave forms with 8051 Microcontroller.

CO2.Development of assembly language programs with ARM

Processor Microcontroller.

CO3.Interface peripheral devices with 8051 and ARM

Microcontrollers.

CO4. Design and implementation of serial communication by using

8051 and ARM Microcontrollers.

CO5.To implement simple RTOS programs.

8051 experiments:

1. Pulse width modulation

2. Sine wave generation using look-up table

3. Serial communication

4. Interfacing LCD /seven segment display unit

5. Stepper motor control

ARM experiments:

1. Arithmetic operations

2. LEDs

3. Serial communication

4. LCD interface

5. ADC

6. Keyboard interfacing

RTOS programming:

1. Multitasking using RTOS.

2. Implement semaphore for task switching using RTOS.

3. Implement priority scheduling and OS time delay functions by

writing 3 different tasks

4. Transfer data using Ethernet port.

NOTES

Documents

(Department of Electronics and Communication Engineering ...gvpce.ac.in/mtechregsyl18-19/9.VDES_18-19.pdfstudent shall re-register and repeat those courses as and when they are offered