DEPARTMENT OF ELECTRONICS & COMMUNICATION … · 2019-04-12 · 4. Design a 4 – bit Adder / Subtractor. 5. Design and realization of a 4 – bit gray to Binary and Binary to Gray

ANURAG COLLEGE OF ENGINEERING DEPT OF ECE

DIGITAL SYSTEM DESIGN LAB Page 1

DEPARTMENT OF

ELECTRONICS & COMMUNICATION ENGINEERING

LABORATORY MANUAL

FOR

DIGITAL SYSTEM DESIGN LAB

B.Tech. ECE II Year I Sem.

Prepared by

P.Mahender

Assistant Professor

Department of Electronics and Communication Engineering

ANURAG COLLEGE OF ENGINEERING

(Approved by AICTE, New Delhi & Affiliated to JNTU-HYD)

AUSHAPUR (V), GHATKESAR (M), R.R.DIST, T.S.501301







EC307PC: DIGITAL SYSTEM DESIGN LAB L T P C

B.Tech. II Year I Sem. 0 0 2 1

Note: Implement using digital ICs, all experiments to be carried out.

List of Experiments –

1. Realization of Boolean Expressions using Gates.

2. Design and realization logic gates using universal gates.

3. Generation of clock using NAND / NOR gates.

4. Design a 4 – bit Adder / Subtractor.

5. Design and realization of a 4 – bit gray to Binary and Binary to Gray Converter.

6. Design and realization of an 8 bit parallel load and serial out shift register using flip-

flops.

7. Design and realization of a Synchronous counter using flip-flops.

8. Design and realization of Asynchronous counters using flip-flops.

9. Design and realization of 8x1 MUX using 2x1 MUX.

10. Design and realization of 4 bit comparator.

11. Design and Realization of a sequence detector-a finite state machine.

Major Equipments required for Laboratories:

1. 5 V Fixed Regulated Power Supply/ 0-5V or more Regulated Power Supply.

2. 20 MHz Oscilloscope with Dual Channel.

3. Bread board and components/ Trainer Kit.

4. Multimeter.







LIST OF EXPERIMENTS

NAME OF THE EXPERIMENT

1. Realization of Boolean Expressions using Gates.

2. Design and realization logic gates using universal gates.

3. Generation of clock using NAND / NOR gates.

4. Design a 4 – bit Adder / Subtractor.

5. Design and realization of a 4 – bit gray to Binary and Binary to Gray

Converter.

6. Design and realization of an 8 bit parallel load and serial out shift register

using flip-flops.

7. Design and realization of a Synchronous and Asynchronous counter using

flip-flops.

8. Design and realization of Asynchronous counters using flip-flops.

9. Design and realization of 8x1 MUX using 2x1 MUX.

10. Design and realization of 4 bit comparator.

11. Design and Realization of a sequence detector-a finite state machine.



EXPERIMENT-1

Realization of Boolean Expressions using Gates.

Aim:-Implement of the given Boolean function using logic gates in both SOP and POS

forms

Two input SOP - A.B + A’.B’

Two input POS: - (A+B) (B+C) (A+C’)

Apparatus required:-

1. Digital Trainer Kit/Bread board.

2. Single Strand Wires.

3. ICs-7408,7432,7404.

4. Power Supply

5. Connecting Wires.

Theory:-

a) SOP: - It is the Sum of product form in which the terms are taken as 1. It is

denoted in the K-map expression by sigma (Σ)

A.B. + A’B’

Logic Circuit Of this expression:-

Truth Table for this SOP expression:

A B A’ B’ A.B A’.B’ Y=AB’+AB’

0 0 1 1 0 1 1

0 1 1 0 0 0 0

1 0 0 1 0 0 0

1 1 0 0 1 0 1

7408

7408

7432



b) POS: - It is the product of the sums form in which the terms are taken as 0. It is

denoted in the K-Map expression by the Sign pie (π)

(A+B) (B+ C) (A + C’)

Circuit Diagram:

Truth Table for POS expression:

A B C A+B B+C A+C’ Y=(A+B)(B+C)(A+C’)

0 0 0 0 0 1 0

0 0 1 0 1 0 0

0 1 0 1 1 1 1

0 1 1 1 1 0 0

1 0 0 1 0 1 0

1 0 1 1 1 1 1

1 1 0 1 1 1 1

1 1 1 1 1 1 1

Procedure: - For SOP form: - A.B + A’.B’

1. Place the Digital lab kit at one place.

2. Take the one AND gate ICs i.e. IC no.7408, one NOT gate IC i.e. IC no. 7404 and

one OR gate IC i.e. IC no. 7432.

3. Place these 3 ICs in the breadboard one by one.

4. Now, connect the AND gate with the inputs of A and B and other AND gate in the

same

IC is given by the complement input of the A and B i.e. A’ and B’ by using NOT gate

with the help of connecting wires.

7432

7408

7408 7432

7432



5. Give the output voltage Vcc and GROUND to all the ICs separately. When whole

configuration is read, gently on the switch and note there output of different values of A and

B i.e. either 0 or 1.

For POS form :- (A+B)(B+C)(A+C’)

1. Place the Digital lab kit at one place.

2. . Take the 1 OR, 1 AND, 1 NOT gates IC

3. Place these 3 ICs in the breadboard one by one.

4. Now, connect the OR gate of Input A or B, B or C and last one is A or C’ (i.e.

complement of C using NOT gate. Inputs are connected with the help of connecting

wires.

5. When whole circuit is complete, on the switch and note down the output with

different values of A, B and C.

Precautions:-

1. Connecting wires should be rubbed with sand papers so that there is no rust.

2. Make sure that the apparatus is switched off while placing ICs and connecting of

wires.

3. The connections should be tights.

4. ICs are placed in a proper way in the breadboard. There is no short of current in the

in same inputs.

Result:-Hence, given Boolean Expression is implemented by the Logic Gates.

i.e. (i) A.B + A’.B’

(ii) (A+B) (B+C) (A+C’)



EXPERIMENT-2

IMPLEMENT LOGIC GATES USING UNIVERSAL GATES

AIM: -

(A) To construct NOT, AND, OR, Exclusive OR (EX-OR), Exclusive NOR (EX-NOR) logic

gates using only NAND gates.

(B) To construct NOT, AND, OR, Exclusive OR (EX-OR), Exclusive NOR (EX-NOR) logic

gates using only NOR gates.

APPARATUS REQUIRED

SL No.

COMPONENT

SPECIFICATION

1 2 INPUT NAND GATE

IC 7400

2 2 INPUT NOR GATE

IC 7402

3 PATCH CORDS

--

4 CONNECTING WIRES --

5 BREAD BOARD 1

6 RPS(0-30V) 1

(A) NAND as a Universal gate:

THEORY:

NAND gate is actually a combination of two logic gates: AND gate followed by NOT

gate. So its output is complement of the output of an AND gate. This gate can have minimum

two inputs, output is always one. By using only NAND gates, we can realize all logic

functions: AND, OR, NOT, X-OR, X-NOR, NOR. So this gate is also called universal gate.

1. NAND gate as NOT gate:

A NOT produces complement of the input. It can have only one input, tie the inputs of

a NAND gate together. Now it will work as a NOT gate. Its output is

Y = (A.A)’ = (A)’



2. NAND gates as AND gate:

A NAND produces complement of AND gate. So, if the output of a NAND gate is

inverted, overall output will be that of an AND gate.

Y = ((A.B)’)’= (A.B)

3. NAND gates as OR gate:

From Demerger’s theorems: (A.B)’ = A’ + B’. Similarly, (A’.B’)’ = A’’ + B’’ = A + B

So, give the inverted inputs to a NAND gate, obtain OR operation at output.

4. NAND gates as EX-OR gate:

The output of a two input EX-OR gate is given by: Y = A’B + AB’. EX-OR gate can be

implemented using four NAND gates as follows.

Gate No. Inputs Output

1 A, B (AB)’

2 A, (AB)’(A (AB)’)’

3 AB)’, B (B (AB)’)’

4 (A (AB)’)’, (B (AB)’)’ A’B + AB’



Now the output from gate no. 4 is the overall output of the configuration.

Y = ((A (AB)’)’ (B (AB)’)’)’

= (A(AB)’)’’ + (B(AB)’)’’

= (A(AB)’) + (B(AB)’)

= (A(A’ + B)’) + (B(A’ + B’))

= (AA’ + AB’) + (BA’ + BB’)

= ( 0 + AB’ + BA’ + 0 )

= AB’ + BA’

Y = AB’ + A’B

5. NAND gates as EX-NOR gate

EX-NOR gate is actually EX-OR gate followed by NOT gate. So give the output of

EX-OR gate to a NOT gate, overall ouput is that of an EX-NOR gate.

Y = AB+ A’B’

6. NAND gates as NOR gate:

A NOR gate is an OR gate followed by NOT gate. So connect the output of OR gate

to a NOT gate, overall output is that of a NOR gate.

Y = (A + B)’



PROCEDURE:

1. Connect the trainer kit to ac power supply.

2. Connect the NAND gates for any of the logic functions to be realized.

3. Connect the inputs of first stage to logic sources and output of the last gate to logic

indicator.

4. Apply various input combinations and observe output for each one.

5. Verify the truth table for each input/ output combination.

6. Repeat the process for all logic functions.

7. Switch off the ac power supply.

(B) NOR as a Universal gate:-

THEORY:

NOR gate is actually a combination of two logic gates: OR gate followed by NOT

gate. So its output is complement of the output of an OR gate. This gate can have minimum

two inputs, output is always one. By using only NOR gates, we can realize all logic

functions: AND, OR, NOT, X-OR, X-NOR, NAND. So this gate is also called universal gate.

1. NOR gate as NOT gate:

A NOT produces complement of the input. It can have only one input, tie the inputs of

a NOR gate together. Now it will work as a NOT gate. Its output is

Y = (A+A)’ = (A)’



2. NOR gates as OR gate:

A NOR produces complement of OR gate. So, if the output of a NOR gate is inverted,

overall output will be that of an OR gate.

Y = ((A+B)’)’= (A+B)

3. NOR gates as AND gate:

From Demerger’s theorems: (A+B)’ = A’. B’. Similarly, (A’+B’)’ = A’’. B’’ = A .B

So, give the inverted inputs to a NOR gate, obtain AND operation at output.

4. NOR gates as EX-NOR gate:

The output of a two input EX-NOR gate is given by: Y = AB + A’B’. EX-NOR gate

can be implemented using four NOR gates as follows.

Gate No. Inputs Output

1 A, B (A + B)’

2 A, (A + B)’ (A + (A+B)’)’

3 (A + B)’, B (B + (A+B)’)’

4 (A + (A + B)’)’, (B + (A+B)’)’ AB + A’B’

Now the output from gate no. 4 is the overall output of the configuration.

Y = ((A + (A+B)’)’ (B +( A+B)’)’)’

= (A+(A+B)’)’’.(B+(A+B)’)’’

= (A+(A+B)’).(B+(A+B)’)

= (A+A’B’).(B+A’B’)

= (A + A’).(A + B’).(B+A’)(B+B’)

= 1.(A+B’).(B+A’).1



= (A+B’).(B+A’)

= A.(B + A’) +B’.(B+A’)

= AB + AA’ +B’B+B’A’

= AB + 0 + 0 + B’A’

= AB + B’A’

So Y = AB + A’B’

5. NOR gates as EX-OR gate:

EX-OR gate is actually EX-NOR gate followed by NOT gate. So give the output of

EX-NOR gate to a NOT gate, overall output is that of an EX-OR gate.

Y = A’B+ AB’

6. NOR gates as NAND gate:

A NAND gate is an AND gate followed by NOT gate. So connect the output of AND

gate to a NOT gate, overall output is that of a NAND gate.

Y = (AB)’



PROCEDURE:

1. Connect the trainer kit to ac power supply.

2. Connect the NOR gates for any of the logic functions to be realized.

3. Connect the inputs of first stage to logic sources and output of the last gate to logic

indicator.

4. Apply various input combinations and observe output for each one.

5. Verify the truth table for each input/ output combination.

6. Repeat the process for all logic functions.

7. Switch off the ac power supply.

Result:-Hence the verify the truth table of all gates implementation using NAND and NOR

gates.



EXPERIMENT-3

Generation of clock using NAND / NOR gates

AIM: To design a generation of clock using NAND/NOR gates.

EQUIPMENT REQUIRED:

1. CDT KIT.

2. CRO & CRO Probes.

3. IC 7400/IC4093.

4. Connecting wires.

5. Capacitor-0.0001uF.

6. Resistor-3.5kΩ.

7. Power Supply.

THEORY:

The NAND (Not – AND) gate has an output that is normally at logic level “1” and only goes

“LOW” to logic level “0” when all of its inputs are at logic level “1”. The Logic NAND

Gate is the reverse or “Complementary” form of the AND gate.

Logic NAND Gate Equivalence

The logic or Boolean expression given for a logic NAND gate is that for

Logical addition, which is the opposite to the AND gate, and which it performs on

the complements of the inputs. The Boolean expression for a logic NAND gate is denoted by



a single dot or full stop symbol, ( . ) with a line or Over line, ( ‾‾ ) over the expression to

signify the NOT or logical negation of the NAND gate giving us the Boolean expression

of: A.B = Q.

Then we can define t he operation of a 2-input digital logic NAND gate as being:

“If either A or B are NOT true, then Q is true”

Logic NAND Gates are available using digital circuits to produce the desired logical

function and is given a symbol whose shape is that of a standard AND gate with a circle,

sometimes called an “inversion bubble” at its output to represent the NOT gate symbol with

the logical operation of the NAND gate given as.

The Boolean Expression for this 4-input logic NAND gate will therefore be: Q = A.B.C.D

The “Universal” NAND Gate:

The Logic NAND Gate is generally classed as a “Universal” gate because it is one of

the most commonly used logic gate types. NAND gates can also be used to produce any other

type of logic gate function, and in practice the NAND gate forms the basis of most practical

logic circuits.

By connecting them together in various combinations the three basic gate types

of AND, OR and NOT function can be formed using only NAND‘s, for example.

Various Logic Gates: various Logic gates using only NAND GatesAs well as the three

common types above, Ex-Or, Ex-Nor and standard NOR gates can be formed using just

individual NAND gates.

Commonly available digital logic NAND gate IC’s include:

TTL Logic NAND Gates

74LS00 Quad 2-input

74LS10 Triple 3-input

74LS20 Dual 4-input

74LS30 Single 8-input

CMOS Logic NAND Gates

CD4011 Quad 2-input

CD4023 Triple 3-input



CD4012 Dual 4-input

NAND gate: (7400/4093):

BLOCK DIAGRAM:

R

Voutput

C



PROCEDURE:

1. Connect the NAND/NOR gate inputs as for circuit diagram.

2. Connect the Capacitor to input of NAND/NOR gate and with respect to the Ground.

3. Connect the Resistor feedback or parallel to the NAND/NOR gate.

4. Take the output at NAND/NOR gate output and at the ground.

5. Observe the waveform at the CRO and calculate the frequency of clock pulse.

Theoretical Calculations:-

F=450 KHz

F= 1/2πRC

Assume C=0.0001uF

R= 1/2π*450K*0.0001uF

R=3.5KΏ

EXPECTED OUTPUT:

Result: Hence the design of a 450 KHZ clock pulse using NAND/NOR gates has been

verified practically.



EXPERIMENT-4

Design a 4 – bit Adder / Subtractor

AIM:-To study and implement 4 bit adder/subtractor

APPARATUS:-

1) 4-bit adder/ SubtractorTrainerkit.

2) Patchchords.

3) Powersupply.

Theory:-

Adders are important not only in computers but in many types of digital system in which

numerical data are processed. An understanding of the basic adder operation is fundamental

to the study of digital system. In this experiment using the 4 bit add/sub constructing the 16

bit add/sub. The IC number for 4 bit add/sub is 74LS83A. These full adders perform the

addition of two 4-bit binary numbers. The sum (∑) outputs are provided for each bit and the

resultant carry (C4) is obtained from the fourth bit. These adders feature full internal look

ahead across all four bits. This provides the system designer with partial look ahead

performance at the economy and reduced package count of a ripple-carry implementation.

The adder logic, including the carry, is implemented in its true form meaning that the end-

around carry can be accomplished without the need for logic or level inversion. The

cascading of the 4 bit adder we can form the 16 bit adder. The carry should be forwarded to

anotherIC.

PIN CONFIGURATION:-

Figure (1) pin diagram of 74LS83A



CIRCUIT DIAGRAM:-

Figure(2):Cascading of 4 bit adder/subtractor

PROCEDURE:-

ADDITION:-

1) Connect the A0-A3 to the logic switches provided on the trainerkit.

2) Connect the B0-B3 to the logic switches provided on the trainerkit.

3) Connect the outputs to the ledindicators.

4) Connect the mode switch to the logicswitches.

5) Now put the mode switch in logic ‘0’ it is indicated that addition operationperforming.

6) Now give the input data using the A0-A3 and B0-B3logic switches.Ex:-

Input data A0-A3 = 1010

Inputdata B0-B3 =0101

Output 1111



SUBTRACTION:-

1) Connect the A0-A3 to the logic switches provided on the trainerkit.

2) Connect the B0-B3 to the logic switches provided on the trainerkit.

3) Connect the outputs to the ledindicators.

4) Connect the mode switch to the logicswitches.

5) Now put the mode switch in logic ‘1’ it is indicated that Subtraction operation performing.

6) Now give the input data using the A0-A3 and B0-B3logicswitches.

7) To perform the subtraction operation we 1’s compliment the data of the ‘B’input.

8) Now Add two data’s A and B when u get the result add ‘1’ to the resultdata.

Input data A0-A3 = 1010

Inputdata B0-B3 =0101

1’s compliment i/pB data 1010

9)Now add the data input A and 1’s Complimented data B

1 111

Input data A0-A13= 1010

1’s complimenti/p B 1010

Output data1 0100

Carry bit=1

Result: Hence the 4 bit addition and subtraction is verified.



EXPERIMENT-5

DESIGN A 4-BIT GRAY TO BINARY AND

BINARY TO GRAY CODE CONVERTER

AIM:Observe Binary to Gray & Gray to Binary Code Conversion

EQUIPMENT REQUIRED:

1. Gray - binary - gray Trainer kit.

2. Patch Cords.

3. Power Supply.

THEORY:

The logical circuit which converts binary code to equivalent gray code is known

as binary to gray code converter. The gray code is a non weighted code. The successive

gray code differs in one bit position only that means it is a unit distance code. It is also

referred as cyclic code. It is not suitable for arithmetic operations. It is the most popular of

the unit distance codes. It is also a reflective code. An n-bit Gray Code can be obtained by

reflecting an n-1 bit code about an axis after 2n-1 rows, and putting the MSB of 0 above the

axis and the MSB of 1 below the axis.

In gray to binary code converter, input is a multiplies gray code and output is its

equivalent binary code.Let us consider a 4 bit gray to binary code converter. To design a 4 bit

gray to binary code converter, we first have to draw a conversion table.



CIRCUIT DIAGRAM:



TRUTH TABLE: BINARY TO GRAY CODE CONVERTER:

CIRCUIT DIAGRAM:

INPUTS OUTPUTS

BINARY CODE GRAY CODE

A B C D G1 G2 G3 G4

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0



TABLE FOR GRAY TO BINARY CODE CONVERTER:

PR

OCEDURE:

BINARY TO GRAY:

1. Connect Inputs (A, B, C, D) to Input Switches (Red LED).

2. Connect Outputs (G1, G2, G3, G4) to Output Switches (Green LED).

3. Give Binary Inputs at A, B, C, D & Observe Gray Code Outputs as per Truth Table.

GRAY TO BINARY:

1. Connect Inputs (A, B, C, D) to Input Switches (Red LED).

2. Connect Outputs (B1, B2, B3, B4) to Output Switches (Green LED).

3. Give Gray Code Inputs at A, B, C, D & Observe Binary Code Outputs as per Truth

Table.

Result: Hence the Binary to Gray & Gray to Binary Code Conversion has been verified.

INPUTS OUTPUTS

GRAY CODE BINARY CODE

A B C D B4 B3 B2 B1

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1



EXPERIMENT-6

8- BIT PARALLEL LOAD AND SERIAL OUT

USING TWO 4 BIT SHIFT REGISTER

Aim: -To study and implementation of 8 bit parallel load and serial out

using two 4 bit shift Register.

Apparatus Required:-

1. 8 bit shift register Trainerkit.

2. Patchchords.

3. Powersupply.

Theory:-

A register is simply a group of flip flops that can be used to store a binary

number. A shiftregister is a group of flip flops connected such that the binary number can be

entered (shifted) into the register and possibly shifted out. There are two ways to shift the data

(bits in the binary number) from one place to another. The first method involves shifting the

data 1 bit at a time in a serial fashion, beginning with either MSB or LSB. This technique is

referred to as serial shifting. The second method involves shifting all the data bits

simultaneously and is referred to as parallel shifting. There are two ways to shift data into a

register (serial or parallel) and similarly two ways to shift data out of the register. This leads

to the construction of four basic types ofregisters.This bidirectional shift register is designed

to incorporate virtually all of the features a system designer may want in a shift register; they

feature parallel inputs, parallel outputs, right- shift and left-shift serial inputs, operating-

mode-control inputs, and a direct overriding clear line. The register has four distinct modes of

operation, namely: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift

left (in the direction QD toward QA) Inhibit clock Synchronous parallel loading is

accomplished by applying the four bits of data and taking both mode control inputs, S0 and

S1, HIGH. The data is loaded into the associated flip-flops and appear at the outputs after the

positive transition of the clock input. During loading, serial data flow is inhibited. Shift right

is accomplished synchronously with the rising edge of the clock pulse when S0 is HIGH and

S1 is LOW. Serial data for this mode is entered at the shift-right data input. When S0 is LOW

and S1 is HIGH, data shifts left synchronously and new data is entered at the shift-left serial

input.



Pin diagram (74LS194):-

INTERNAL DIAGRAM OF 74194:-



Circuit Diagram:-



Procedure:-

1. Connect the above circuit on the trainerkit.

2. Here the selection lines of the two IC can be shorted then it can be form the S0 andS1.

3. Connect the first pin of the two IC’s then it can be form a clear then it connect to the logic

switch.

4. Short the pin number 11 of the both the IC’s then it forms a common clock line then it is

connected to the 1Hz clock generator or the pulsarswitch.

5. Now connect the parallel data inputs of the first IC and the second IC to the logic switches

6. Connect the QA, QB, QC and QD of the first IC to the led’s shown in thecircuit.

7. Connect the QA, QB, QC and QD of the second IC to the led’s shown in the circuit assume

it as QE, QF, QG andQH.

8. Connect the serial input of the second IC (pin7) to the logic switch put in logic‘0’.

9. Connect the 2pin of the second IC to the 12pin of the first IC.

10. Connect the 7pin of the second IC to the 15pin of the firstIC.

11. Connect the parallel inputs (ABCD) first IC to the logic switches similarly connect the

Parallel inputs (ABCD) of the second IC to the logic switches and assume it asEFGH.

12. Now put the selection lines both are high that is S0=’1’ and S1=’1’ now apply the input

Data. Whatever you given it will be indicated on theled’s.

Ex:

A=1, B=0,C=0,D=0,A=0,B=0,C=0,D=0=1000 0000

1. After applying the parallel data put the S0=’1’ and S1=’0’ then the data

isshifted rightside.

2. The input data serially exited at the QA you will observe that using thepulsar

switch giving a single pulse at atime.

Observe the truth tablebelow.



Truth Table:

Mode

S0

S1

Clear

Clock

PARALLEL

INPU TS

OUTPUTS

SERIA

L

OUTPU

T

A

B

C

D

E

F

G

H

Q

A

QB

QC Q

D

QE

QF Q

G

Q

H

QH

Hold 1 1 H 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

1 0 H 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

1 0 H 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

Shift 1 0 H 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0

right 1 0 H 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0

1 0 H 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0

1 0 H 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0

1 0 H 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Result:- Hence the 8 bit parallel load and serial out using two 4 bit shift Register

constructed and verified.



EXPERIMENT-7

Design and realization of a Asynchronous counter using flip-flops

AIM: To verify the truth table of 4-Bit Asynchronous counter.

EQUIPMENTREQUIRED: 1.ASynchronous counters trainer kit.

2. PATCHCORDS.

3. Power Supply

A 4-Bit Asynchronous counter count from 0 to 15. To implement Binary counter we require

7493 IC.

PINCONFIGURATIONOF74HCT93:

PROCEDURE:

1. Connect the inputs MR1, MR2, to the Logic input Switches and outputs.

2. Qo, Q1, Q2, and Q3 to the Logic outputs.

3.Feed the Logic signals 0 or 1 in the truth table.

4.Monitor the outputs Q0, Q1, Q2, Q3.

5.Verify the truth table.

NOTE:

1. Connect CP1 to Qo



2. Pulse input is connected to Pin 14 (CP0)

3. When the count output is Present count can be observed with every

Pulse. (16Pulses)

TRUTHTABLE:

ResetI/P Outputs

MR1 MR2 Q3 Q2 Q1 Q0

H H L L L L

L H COUNT

H L COUNT

L L COUNT

COUNTTABLE:

COUNT OUTPUTS

Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

CONCLUSION: Hence verified the truth table of 4-Bit binary Asynchronous

Counter.



EXPERIMENT-8

Design and realization of a Synchronous counter using flip-flops

AIM:To verify the truth table of 4-bit Synchronous Counter.

EQUIPMENTREQUIRED: 1.Synchronous counter trainer kit.

2. Patch cords.

3.Power Supply.

THEORY: Synchronous Counters are so called because the clock input of all the individual

flip-flops within the counter are all clocked together at the same time by the same clock

signal with the Synchronous Counter, the external clock signal is connected to the clock

input of EVERY individual flip-flop within the counter so that all of the flip-flops are

clocked together simultaneously (in parallel) at the same time giving a fixed time

relationship.

A counter is a register capable of counting number of clock pulse arriving at its clock

input. Counter represents the number of clock pulses arrived. An up/down counter is one that

is capable of progressing in increasing order or decreasing order through acertain sequence.

An up/down counter is also called bidirectional counter. Usually up/down operation of the

counter is controlled by up/down signal. When this signal is high counter goes through up

sequence and when up/down signal is low counter follows reverse sequence.

CONNECTIONDIAGRAM:



PROCEDURE:

1. Connect the inputs A,B,C,D,G,max/min,load and up/down.

2. Logic inputs witches and outputs Qa Qb, Qc and Qd to the output logic

switches.

3. Keep load input high.

4. When up input(on the board) is fed with logic 0 then the counts “Up “count.

5. When up input(on the board) is fed with logic1 then the count is “down

“count.

6. This Count is achieved with Pulsar switch (instead of the clock, pulsar input

as to be connected and the output changes with every pulse).

FUNCTIONTABLE:

(UPCOUNT)

COUNT OUTPUTS

Qd Qc Qb Qa

0 L L L L

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

10 H L H L

11 H L H H

12 H H L L

13 H H L H

14 H H H L

15 H H H H



(DOWN COUNT)

COUNT OUTPUTS

Qd Qc Qb Qa

0 H H H H

1 H H H L

2 H H L H

3 H H L L

4 H L H H

5 H L H L

6 H L L H

7 H L L L

8 L H H H

9 L H H L

10 L H L H

11 L H L L

12 L L H H

13 L L H L

14 L L L H

15 L L L L

NOTE: All the inputs connected may be high or low. They are just connected to

close the circuit. For every count pulse should be given then only the output

changes.

CONCLUSION:Hence verified the truth table of 4-Bit Synchronous Binary

Counter.



EXPERIMENT-9

Design and realization of 8x1 MUX using 2x1 MUX.

Aim:-To design and implement 8x1 MUX using 2x1MUX.

Apparatus Required:-1.IC74157-3.

2.Bread board/CDTkit-1.

3.Connecting wires.

4.Power supply.

Theory:- 2-to-1 Multiplexer A 2-to 1 multiplexer consists of two inputs D0 and D1, one

select input S and one output Y. Depends on the select signal, the output is connected to

either of the inputs. Since there are two input signals only two ways are possible to connect

the inputs to the outputs, so one select is needed to do these operations. If the select line is

low, then the output will be switched to D0 input, where as if select line is high, then the

output will be switched to D1 input.The figure below shows the block diagram of a 2-to-1

multiplexer which connects two 1-bit inputs to a commend estimation.

2 to1 MUX:-

The truth table of the 2-to-1 multiplexer is shown below. Depending on the selector

switching the inputs are produce dat outputs, i.e., D0, D1and are switched to the output for

S=0 and S=1 respectively. Thus, the Boolean expression for the output becomes D0 when

S=0 and output is D1 when S=1.



From the truth table the Boolean expression of the output is given as exp

2 to 1 MUX truth table:-

From the above output expression, the logic circuit of 2-to-1 multiplexer can be

implemented using logic gates as shown in figure. It consists of two AND gates, on e NOT

gate and one OR gate. When the select line, S=0, the output of the upper AND gate is zero,

but the lower AND gate is D0.

Thus, the output generated by the OR gate is equal to D0. Similarly, when S=1, the output of

the lower AND gate is zero, but the output of upper AND gate is D1. There fore, the output

of the OR gate is D1.Thus, the above given Boolean expression is satisfied by this circuit.

2 to1 mux logic diagram:-

In some cases, two or more multiplexers are fabricated on a single IC because simple logic

gates can implement the multiplexer. Generally four 2 line to 1 line multiplexers are

fabricated in a single IC as shown in figure below. Some of these Ics of 2 to 1 multiplexers

include IC74157 and IC74158. The selection line controls the input lines to the output in all

four multiplexers.



Pindiagramof74157IC:-

ConnectionDiagram:-

Procedure:-

1. Connect the circuit as for circuit diagram.

2.vary the inputs lines (Datalines) and selection lines and observe the output.

3.Verify the truth table for 8x1 mux.



Truth table:-

Result:-Hence the verified the truth table of 8x1 MUX using 2x1 MUX.



EXPERIMENT-10

Design and realization of 4 bit comparator.

AIM:To verify the truth table of 16-bit Comparator.

APPARATUS: 1. 16-bit comparator trainer kit.

2. Patch cords.

3.Power Supply.

THEORY:

Digital comparators actually use Exclusive-NOR gates within their design for

comparing their respective pairs of bits. When we are comparing two binary or BCD values

or variables against each other, we are comparing the “magnitude” of these values, a logic

“0” against a logic “1” which is where the term Magnitude Comparator comes from.

As well as comparing individual bits, we can design larger bit comparators by

cascading together n of these and produce a n-bit comparator just as we did for the n-bit

adder in the previous tutorial. Multi-bit comparators can be constructed to compare whole

binary or BCD words to produce an output if one word is larger, equal to or less than the

other.

A very good example of this is the 4-bit Magnitude Comparator. Here, two 4-bit

words (“nibbles”) are compared to each other to produce the relevant output with one word

connected to inputs A and the other to be compared against connected to input B.

4-bit Magnitude Comparator:



Some commercially available digital comparators such as the TTL 74LS85 or CMOS

4063 4-bit magnitude comparator have additional input terminals that allow more individual

comparators to be “cascaded” together to compare words larger than 4-bits with magnitude

comparators of “n”-bits being produced. These cascading inputs are connected directly to the

corresponding outputs of the previous comparator as shown to compare 8, 16 or even 32-bit

words.

When comparing large binary or BCD numbers like the example above, to save time

the comparator starts by comparing the highest-order bit (MSB) first. If equality exists, A = B

then it compares the next lowest bit and so on until it reaches the lowest-order bit, (LSB). If

equality still exists then the two numbers are defined as being equal.

If inequality is found, either A > B or A < B the relationship between the two

numbers is determined and the comparison between any additional lower order bits stops.

Digital Comparatorare used widely in Analogue-to-Digital converters, (ADC) and Arithmetic

Logic Units, (ALU) to perform a variety of arithmetic operations. Magnitude Comparator is

a logical circuit , which compares two signals A and B and generates three logical

outputs, whether A > B, A = B, or A < B . IC 7485 is a high speed 4-bit Magnitude

comparator , which compares two 4-bit words . The A = B Input must be held high for

proper compare operation.

PIN DIAGRAM :



PROCEDURE: (4-bit Comparator)

1. Connect Inputs ( A0,A1,A2,A3,B0,B1,B2,B3) to Input Switches.

2. Connect Cascade Inputs (A<B,A>B,A=B) to Input Switches.

3. Connect Outputs (A<B,A>B,A=B) to Output Switches.

4. Observe the Truth Table.



TRUTH TABLE FOR 4-BIT COMPARATOR:

COMPARING

INPUTS

CASCADING

INPUTS

OUTPUTS

A3,B3 A2,B2 A1,B1 A0,B0 A>B A<B A=B A>B A<B A=B

A3>B3 X X X X X X H L L

A3<B3 X X X X X X L H L

A3=B3 A2>B2 X X X X X H L L

A3=B3 A2<B2 X X X X X L H L

A3=B3 A2=B2 A1>B1 X X X X H L L

A3=B3 A2=B2 A1<B1 X X X X L H L

A3=B3 A2=B2 A1=B1 A0>B0 X X X H L L

A3=B3 A2=B2 A1=B1 A0<B0 X X X L H L

A3=B3 A2=B2 A1=B1 A0=B0 H L L H L L

A3=B3 A2=B2 A1=B1 A0=B0 L H L L H L

A3=B3 A2=B2 A1=B1 A0=B0 L L H L L H

A3=B3 A2=B2 A1=B1 A0=B0 X X H L L H

Result: Hence the truth table of 16- Comparator has been verified.



EXPERIMENT-11

Design and Realization of a sequence detector-a finite state

machine.

Aim:- To Design and Realization of a Sequence Detector.

Apparatus Required:-

1. ICs 7474,7432,7408,7404,7411,7486.

2. Bread board/ Trainer kit.

3.Power Supply.

4.connecting wires.

Theory:-

A sequence detector is a sequential state machine which takes an input string of bits

and generates an output 1 whenever the target sequence has been detected.In a Mealy

machine, output depends on the present state and the external input (x). Hence in the diagram,

the output is written outside the states, along with inputs. Sequence detector is of two types:

Overlapping & Non-Overlapping

In an overlapping sequence detector the last bit of one sequence becomes the first bit

of next sequence. However, in non-overlapping sequence detector the last bit of one sequence

does not become the first bit of next sequence. In this post, we’ll discuss the design procedure

for non-overlapping 1011 Mealy sequence detector.

FOR 11011 DESIGN



Connection/ Circuit Diagram:-

Procedure:-

1.conncet the circuit as for the circuit diagram.

2. give the input from the X to D flip flop.

3. The out put will be noted across the Z.



Result:- Hence the Design and Realization of a sequence detector-a finite state machine

as been down.

.

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DEPARTMENT OF ELECTRONICS & COMMUNICATION … · 2019-04-12 · 4. Design a 4 – bit Adder / Subtractor. 5. Design and realization of a 4 – bit gray to Binary and Binary to Gray