Design and Characterization of High-Voltage Silicon Carbide Emitter Turn-off Thyristor

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009 1189

Design and Characterization of High-Voltage SiliconCarbide Emitter Turn-off Thyristor

Jun Wang, Student Member, IEEE, and Alex Q. Huang, Fellow, IEEE

Abstract—A novel MOS-controlled silicon carbide (SiC) thyris-tor device, the SiC emitter turn-off thyristor (ETO), as a promis-ing technology for future high-voltage and high-frequency switch-ing applications has been developed. The world’s first 4.5-kV SiCp-type ETO prototype based on a 0.36 cm2 SiC p-type gateturn-off (GTO) shows a forward voltage drop of 4.6 V at a cur-rent density of 25 A/cm2 and a turn-off energy loss of 9.88 mJ. Thelow loss shows that the SiC ETO could operate at a 4-kHz frequencywith a conventional thermal management system. This frequencycapability is about four times higher than the 4.5-kV-class siliconpower devices. The numerical simulations and theoretical analysishave been carried out to show the potentially improved perfor-mance of the high-voltage SiC ETOs. The results show that thehigh-voltage (10-kV) SiC n-type ETO has much better tradeoffperformance than that of the p-type ETO due to a smaller currentgain of the lower bipolar transistor in the SiC n-type GTO. Fur-ther improvement of the 10-kV SiC n-type ETO can be made withthe optimum design of the drift layer carrier lifetime and bufferlayer doping concentration of the 10-kV SiC GTO. The theoreticalanalysis and numerical simulation shows the SiC ETO also has theexcellent reverse bias safe operating area. The experimental andtheoretical studies show that the SiC ETO is a promising candidatefor high-voltage (>5 kV) power conversion applications.

Index Terms—Buffer, emitter turn-off thyristor (ETO), highvoltage, lifetime, loss, reverse bias safe operating area (RBSOA),silicon carbide (SiC).

I. INTRODUCTION

W ITH the increasing demand for smaller, higher powerdensity power systems, the development of novel power

semiconductor devices capable of operating at higher frequen-cies, higher voltages, and higher temperatures are required[1]–[4]. The wide-bandgap silicon carbide (SiC) material is themost promising of the postsilicon alternatives for these appli-cations because of its superior properties (e.g., about ten timeshigher breakdown electric field, higher thermal conductivity,and much lower intrinsic carrier concentration). These prop-erties enable SiC power devices very low loss, fast switchingspeed, and rugged behavior, making them attractive for high-voltage switching applications.

Beginning in the 1990s, continued improvements in the SiCsingle-crystal wafers have resulted in significant progress to-

Manuscript received September 9, 2008; revised November 25, 2008. Cur-rent version published April 17, 2009. This work was supported by a SmallBusiness Technology Transfer (STTR) grant through the U.S. Departmentof Energy’s Energy Storage Program under Contract DE-AC04-94AL85000.Recommended for publication by Associate Editor J. Shen.

The authors are with the Department of Electrical and Computer Engineering,Future Renewable Electric Energy Delivery and Management (FREEDM) Sys-tems Center, North Carolina State University, Raleigh, NC 27695 USA (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2009.2013861

ward the development of low-defect, thick-epitaxial SiC mate-rials and high-voltage SiC devices [5], [6], including the de-velopment of 7-kV gate turn-off (GTO) thyristors [7], 10-kVSiC MOSFETs [8], and 13-kV insulated gate bipolar tran-sistors (IGBTs) [9], [10]. Among these reported high-voltageSiC devices, the on-state resistance of the SiC MOSFET andn-channel IGBT increase significantly as the blocking voltage(>5 kV) and operating junction temperature increase [8], [9].In contrast, the SiC thyristor, with the double-side carrier in-jection and strong conductivity modulation in the drift region,can maintain a low forward voltage drop at high temperatureeven for 10–25 kV level blocking voltage. The high-voltage(10–25 kV) SiC thyristors will have important impact on thefuture’s utility applications because they can greatly reduce thenumber of series connected devices as compared to silicon de-vices, leading to huge reduction of power electronic systems’size, weight, control complexity, cooling cost, and improve-ment of systems’ efficiency and reliability. Therefore, it is clearthat the SiC thyristor is one of the most promising devices forhigh-voltage (>5 kV) switching applications.

In such applications, however, the SiC thyristor has the samedrawbacks as a silicon-based GTO (e.g., current controlledturn-on and turn-off, the need for a turn-on di/dt snubber and,sometimes, a turn-off dv/dt snubber). The emitter turn-offthyristor (ETO) was developed to avoid these drawbacks andto meet the demands of advanced power conversion applica-tions [11]. Theoretical analysis and experimental results on thesilicon-based ETO devices have shown that the ETO technol-ogy can achieve MOS gate control, wide safe operating area(SOA), current saturation capability and faster switching speed[11]–[13]. The innovative ETO concept is also applicable to theSiC thyristor technology. By integrating the high-voltage SiCGTO with the mature silicon power MOSFETs, the SiC ETOis expected not only to simplify the user interface but also toimprove the switching speed and dynamic performance of thedevice.

In this paper, a 4.5-kV SiC p-type ETO prototype is demon-strated with superior performance. Then the simulations andtheoretical analysis are presented to predict the superior trade-off performance of the high-voltage (10 kV) SiC n-type ETOto the p-type ETO and its potentially improved performance bythe design optimization.

II. EXPERIMENT DETAILS AND RESULTS OF SIC ETO

The world’s first SiC p-type ETO, reported here, is a 4.5-kVprototype based on a 0.36 cm2 4.5-kV p-type GTO thyristor. Asshown in Fig. 1, the SiC ETO comprises the power packagedSiC GTO in series with the TO-247 AD packaged silicon power

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1190 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 5, MAY 2009

Fig. 1. 4.5-kV SiC ETO prototype.

MOSFETs. The SiC GTO is a p-type thyristor that uses ann-p-n-p thyristor structure because only the n+ substrates arecommercially available. The emitters of the upper p-n-p andlower n-p-n transistors form the anode and cathode, respec-tively, and the upper base forms the gate contact. Further detailsof the fabrication of the SiC GTO can be referred to the pre-vious work of Ryu et al. [14]. Two 100 V, 75 A Si n-channelMOSFETs (IXTH75N10) in series with the shorting of the gateand drain terminal are used as the gate switch (Qg ) with a turn-onthreshold voltage of more than 3 V between the drain and sourceterminal. A 100-V, 50-A Si p-channel MOSFET (IXTH50P10)is used as the emitter switch (Qe ). The distance between theSiC GTO and silicon power MOSFETs is very small in order toreduce the stray inductance. Similar to the mechanical structureof the Si ETO [12], a copper board with thermally conductiveand electrically insulated dry-to-touch thermal interface pad inits bottom can be attached to the package base plate below thecathode of the SiC GTO so that the generated heat can be dis-sipated through the heat sink, and another copper board can beattached to the drain of the silicon power MOSFETs if theyare surface-mounted together. Because the power losses in thesilicon power MOSFETs are much smaller than that of the SiCGTO, the heat isolation between the SiC GTO and silicon powerMOSFETs can enable the SiC GTO high-temperature operationcapability (>150 C) while keeping silicon power MOSFETs ina lower junction operation temperature (<150 C).

Fig. 2 shows the equivalent circuit and symbol of the SiCETO. The p-type GTO is connected in series with an emitterswitch (Qe ) in its anode and a gate switch (Qg ) in its gate.The resulting SiC ETO is a three-terminal device. The exter-nal resistor (Rg ) of 100 Ω in series with the gate of the Qg

is used to achieve a gate drive current of about 120 mA dur-ing the on-state of the SiC GTO. A small external resistor(Re ) of 3.3 Ω in series with the gate of the Qe is used toachieve a fast switching speed of the emitter switch. During theturn-off transient, the turn-off of the emitter switch cuts off theGTO’s anode current path, and the anode current is commu-tated to the gate path before the cathode voltage starts to rise.In this way, the hard-driven turn-off (or unity-gain turn-off)condition is realized, and the whole turn-off process is like anopen-base n-p-n transistor turn-off. It means that no thyristorlatch-up mechanism exists during the turn-off, which ensures auniform transient process without the strong current filament.Thus, the turn-off current dramatically increases, resulting ina wider SOA. The SiC ETO also improves the turn-off speed

Fig. 2. (a) p-type ETO equivalent circuit. (b) Corresponding ETO symbol.

Fig. 3. Blocking characteristic of the SiC GTO at 25 C.

because of the rapid extraction of the stored charge in the SiCGTO by such a large gate current.

The SiC GTO was tested with gate floating at room tem-perature for blocking voltage measurement. Fig. 3 shows itsreverse current–voltage (I–V ) characteristic at room tempera-ture. A blocking voltage of 4.1 kV at a leakage current densityof 14 µA/cm2 has been achieved. The blocking voltage of theSiC ETO is the sum of the silicon power MOSFET’s (∼100 V)and the SiC GTO’s, achieving 4.5 kV at a current density of50 µA/cm2 .

The forward I–V characteristics of the SiC GTO at elevatedtemperatures are shown in Fig. 4(a). The GTO shows a forwardvoltage drop of 4.2 V at a current density of 25 A/cm2 and agate drive current of 100 mA at room temperature. The deviceshows a negative temperature coefficient due to the increase ofcarrier lifetime and the decrease of the built-in potential of thep-n junction with the increase of temperature. The insignificantreduction of the slope of the I–V curve after the turn-on kneevoltage with the increase of temperature means the increase ofcarrier lifetime with the increased temperature, since the carriermobility reduces with the increase of temperature. The reductionof the turn-on knee voltage means the reduction of the built-inpotential of the p-n junction with the increase of temperature.The forward I–V characteristics of the SiC ETO are shown inFig. 4(b). Comparing to the GTO’s test results, the integrated

WANG AND HUANG: DESIGN AND CHARACTERIZATION OF HIGH-VOLTAGE SILICON CARBIDE EMITTER TURN-OFF THYRISTOR 1191

Fig. 4. (a) SiC GTO I–V characteristics. (b) SiC ETO I–V characteristics.

Fig. 5. Turn-off waveforms of the 4.5-kV SiC ETO.

MOSFET contributes to only a small increase in the forwardvoltage drop, and there is no visible increase of the forwardvoltage drop in the SiC ETO, which indicates that the ETOpreserved the excellent conduction capability of the SiC GTO.

The transient characteristic of the 4.5-kV SiC ETO was testedin a clamped inductive load circuit. An isolated gate driverwas used to drive the SiC ETO. A 10-kV SiC junction barrierSchottky (JBS) diode is used as the freewheeling diode, and anair-core 2.8-mH inductance is used as the load inductor. The testwas conducted at a dc-link voltage of 2.5 kV.

The SiC ETO is in the forward blocking state initially andmost dc-link voltage is applied to the SiC GTO in the clampedinductive load circuit. After applying a turn-on optical pulse, a120-mA gate current is applied to the gate of the SiC GTO and−15 V is applied to the Qe (a p-channel MOSFET) to turn onthe SiC ETO. When the SiC ETO is in the conduction state, theinductor current increases until the applying of a turn-off signal.The turn-off of the SiC ETO starts when the optical pulse isremoved and the Qe turns off. A detailed turn-off waveformof the SiC ETO is shown in Fig. 5 when the SiC ETO turnsoff 9.5 A, where VA (Ch1), VGR (Ch2), VC (Ch3), and IC

(Ch4) represent its anode voltage, gate driver signal, cathodevoltage, and cathode current, individually. There are severalimportant time instances during the snubberless turn-off of the

SiC ETO. The turn-off operation begins from the time = t0when the gate driver signal of the gate switch (Qg ) starts to risefrom −15 V to 0. Thereafter, the Qe is turned off. In the periodt0 − t1 , the voltage on the Qe increases. Because the internalstructure of the SiC GTO gate anode is a p-n junction, whenthe voltage of the Qe rises to 3 V, the Qg will be turned on.During this period, the current in the anode (p+ emitter) willbe commutated to the gate switch Qg until finally the anodecurrent becomes zero at t = t1 . At t1 , the ETO achieves unity-gain turn-off and the device operates like an open-base n-p-ntransistor. Once the unity-gain turn-off is established, the holeinjection at the emitter of the upper p-n-p transistor stops. Theabsence of the hole injection results in a net extraction of excesscarriers from the n-base because the cathode current (IC ) hasto be maintained due to the inductive load characteristic. In thetime period t1–t2 , the minority carriers in the n-base region arepulled out by the current αn-p-n · IC until t2 when the p−/n-base junction is recovered from forward bias to reverse bias.From t2 to t3 , the minority carriers in the p drift region and pbuffer region are swept out by the current (1 − αn-p-n)·IC whilethe cathode voltage increases up to the dc-link voltage due tothe formation and expansion of the depletion region on thep−/n-base junction. In the time period t3–t4 , because the storedcharge in the base of the lower n-p-n transistor is not enough tomaintain the cathode current, the cathode current decreases tozero rapidly and a cathode voltage spike appears due to the strayinductance. Finally after t4 , the SiC ETO is in the off state.

In the turn-off waveforms shown in Fig. 5, the storage timeof the SiC ETO is 504 ns in the time interval t0–t2 . The totalcathode voltage rise time is 980 ns in the time interval t2–t3 .The voltage rise process is separated into two stages. First, thereis a slow rise of the cathode voltage up to −820 V (dVC /dt ≈1 kV/µs) in the time interval t2–t22 . This is followed by afast voltage rise (dVC /dt ≈ 8.8 kV/µs) in the time intervalt22–t3 . When the cathode voltage increases to −820 V, the p−

drift region is fully depleted. The stored minority carriers inthe heavily doped p buffer are recombined at a faster speeddue to their much smaller carrier lifetime, resulting in a fasterdepletion region expansion rate and a faster cathode voltage riserate. After the cathode voltage increases to the dc-link voltagevalue, the clamped diode starts to conduct and the cathodecurrent decreases. The total current fall time is 240 ns and the


Fig. 6. 4.5-kV SiC ETO turn-off characteristics under a high SOA condition.

cathode current decay rate (dIC /dt) is 40 A/µs. The dIC /dt-induced cathode voltage spike reaches −2.8 kV. The totalturn-off time is 1.63 µs and the total turn-off energy loss is 9.88mJ. It shows that the prototype SiC ETO can operate at a 4-kHzfrequency with around 125 C junction temperature when aconventional cooling system is used to dissipate a 100 W/cm2

conduction loss and a 100 W/cm2 turn-off loss. This frequencycapability is about four times higher than the 4.5-kV-classsilicon power devices. Higher operation frequency of the SiCETO (around 8 kHz) can be expected if its high-temperatureoperation capability is utilized because the self-heating inducedby its larger power loss at a higher switching frequency resultsin a higher junction temperature (around 225 C) at the samethermal management.

Another advantage of the SiC ETO is its excellent turn-offruggedness. Fig. 6 shows the switching waveforms of the SiCETO at a high SOA condition. The device was tested with adc-link voltage of 2.5 kV and a current of 39 A (corresponding totwo times the rated current and the current limit of the package).It shows that the SiC ETO is capable of handling at least 100 kW(275 kW/cm2) of power. The handling power density of theSiC ETO exceeds the theoretical dynamic avalanche limitation(∼250 kW/cm2) of Si power devices [15]. With the increase ofthe bonding wire number in the gate of the SiC GTO shown inFig. 1, higher handling power density of the SiC ETO can beexpected.

III. RESULT DISCUSSIONS AND FURTHER IMPROVEMENTS

The demonstrated 4.5-kV SiC p-type ETO prototype showsa low loss and fast switching speed, indicating its attractivepotential in high-voltage (>5 kV) switching applications. Andfurther improvement in the SiC ETO is also possible. Most of theturn-off loss of the tested 4.5-kV SiC ETO arises in the cathodevoltage rise stage. During this stage, the total cathode current isalmost kept constant, and only the hole current, (1 − αn-p-n)·IC ,is useful in extracting the excess carriers in the p− drift layerand p buffer layer of the SiC GTO. In the prototype device,this current is not optimized and not high enough due to a large

αn-p-n , resulting in a slower voltage rise rate and, consequently,a higher turn-off loss. A faster excess carrier extraction ratewould greatly improve the depletion region expansion rate, andthus, the cathode voltage rise rate (dVC /dt). So a smaller lowertransistor current gain or a higher upper transistor current gainwould help to improve the turn-off speed and reduce the turn-off loss. Besides the faster excess carrier extraction rate, thesmaller lower transistor current gain also reduces the voltagerising loss due to an optimum carrier distribution profile in thebipolar devices [16]. In other words, a stronger upper transistordesign is needed. Implementation of such a design would favoran n-type thyristor structure using a p-n-p-n structure, wherethe upper transistor is an n-p-n transistor with a large currentgain. This change would require a p+ type SiC substrate, a chal-lenge to be overcome. The recent successful development of the13-kV SiC n-channel IGBT with the p+ SiC epitaxial layer asthe substrate shows a practical method to overcome the chal-lenge [9]. It makes the fabrication of n-type SiC GTOs possiblewith the same technique. The optimization design of 10-kV SiCETOs is presented with the numerical simulations and theoret-ical analysis to show the potentially improved performance ofhigh-voltage (>5-kV) SiC ETOs.

A. Comparison of n- and p-Type 10-kV SiC ETOs

A conservative design of a 120-µm-thick, 4.8 × 1014 cm−3

doped drift layer is used to block 10 kV in the designed n- andp-type SiC punch through GTO. A small carrier ambipolarlifetime of 600 ns in the drift layer is used in the simulationstudy [17]. A 3-µm-thick, 4 × 1016 cm−3 doped buffer layerwith a carrier lifetime of about 100 ns is used as the filed stopperfor the punch through GTO structures. The n-type SiC GTO usesthe p-n-p-n thyristor structure with a 2-µm-thick, 3 × 1018 cm−3

doped p+ substrate, while the p-type SiC GTO uses the n-p-n-pthyristor structure with a 300-µm-thick, 5 × 1018 cm−3 dopedn+ substrate. The device geometry parameters of the 10-kV SiCGTOs are similar to the Cree’s reported GTO structure [14].The physical models and parameters used in the simulations aresummarized in Table I [18]–[20]. The simulations of the SiCETOs based on 1 cm2 SiC GTOs include the incomplete ioniza-tion model and the dependence of carrier lifetime on the dopingconcentration and temperature. The transient characteristics ofthe 10-kV SiC ETOs are simulated in a clamped inductive loadcircuit with a dc-link voltage of 6 kV, a load inductance of20 mH, a stray inductance of 100 nH in the anode–cathodeloop, and a stray inductance of 10 nH in the gate loop.

Fig. 7 shows the comparison of the simulated forwardI–V characteristics of the 10-kV SiC ETOs at 25 C and200 C based on the designed 10-kV SiC GTOs. The measuredon-state resistance of the 10-kV SiC MOSFET increases rapidlywith the increase of temperature due to the reduction of the bulkmobility in the drift layer and JFET region, and its forward volt-age drop becomes very large at high temperature [8]. However,both SiC ETOs have a negative temperature coefficient in theforward conduction characteristics due to the increase of thecarrier lifetime with the temperature in the drift region of SiCGTOs, thus maintaining a small forward voltage drop at elevated


TABLE IPHYSICAL MODELS AND PARAMETERS USED IN SIMULATIONS

Fig. 7. Simulated on-state characteristics of the 10-kV SiC ETOs at 25 C and200 C.

temperatures. At room temperature, the SiC p-type ETO has aforward voltage drop of 4.43 V at a collector current density of30 A/cm2 with a gate drive current of 100 mA, while the SiCn-type ETO has a forward voltage drop of 4.3 V at a collectorcurrent density of 30 A/cm2 with a gate drive current of 1.8 A.The slightly smaller forward voltage drop of the SiC n-typeETO at a low current density than that of the p-type ETO can beexplained by the larger electron mobility than the hole mobilityin the weakly conductivity-modulated drift layers of the SiCGTOs.

Fig. 8 shows the simulated turn-off waveforms of the 10-kVSiC n- and p-type ETOs in a clamped inductive load circuit. Ata load current of 30 A and a dc-link voltage of 6 kV, the SiCp-type ETO has a turn-off time of 2.9 µs and a turn-off energyloss of 190 mJ, while the SiC n-type ETO has a turn-off time of0.52 µs and a turn-off energy loss of 34 mJ.

The much faster switching speed and smaller turn-off loss ofthe SiC n-type ETO than those of the p-type ETO can be mainlyexplained by the smaller lower transistor current gain of the SiCn-type GTO than that of the p-type GTO. The SiC p-type GTOhas a small upper transistor current gain αp-n-p (∼0.45) due tothe low hole injection efficiency from the upper incompletely

ionized p+ emitter and a high lower transistor current gain αn-p-n(∼0.8–0.95) due to the strong electron injection from the bot-tom n+ substrate. In contrast, the SiC n-type GTO has a highupper transistor gain αn-p-n (∼0.95) and a small lower transis-tor gain αp-n-p (∼0.05–0.2) due to the strong electron injectionfrom the upper n+ emitter and the low hole injection from thebottom p+ substrate. The large difference of the current gain ofthe SiC n-p-n and p-n-p transistors are verified in the reportedSiC p- and n-channel IGBTs by the measurements of the bipolartransistor test chips fabricated with the IGBTs. The results showthat the αp-n-p in the 13-kV SiC n-channel IGBT is less than0.1 and the αn-p-n in the 12-kV SiC p-channel IGBT is morethan 0.5 [10], [21], [22]. And the simulated high current gainof the internal SiC n-p-n bipolar transistor in the SiC p-typeGTO is also verified by the reported high-voltage SiC n-p-ntransistors [23], [24]. The large difference of the lower transis-tor current gain between the 10-kV SiC n- and p-type GTOsresults in several times larger carrier extraction rate in the SiCn-type ETO than that of the p-type ETO, because the current(1 − α) · I is useful in extracting the excess carriers in the driftlayer and buffer layer during the unity-gain turn-off process. Italso explains the much faster switching speed and lower turn-offloss of the reported SiC n-channel IGBT than that of the SiCp-channel IGBT, since the IGBT also turn off like an open-basetransistor after the MOS channel is turned off [21], [22].

B. Effect of Buffer Layer to the Tradeoff Performance of the10-kV SiC ETOs

One of the ideas to improve the GTO tradeoff relationship be-tween the forward voltage drop and turn-off loss is a reductionof the drift layer thickness with the punch-through structure.The bottom buffer layer (field stopper) shown in Fig. 2 is usedin the design of high-voltage SiC GTOs. Numerical 2-D simu-lations were carried out to investigate the effects of the dopingconcentration of the buffer layer at a width of 3 µm in the 10-kV


Fig. 8. (a) Simulated switching waveforms of 10-kV SiC p-type ETO. (b) Simulated switching waveforms of 10-kV SiC n-type ETO in a clamped inductive loadcircuit.

Fig. 9. Theoretical turn-off loss versus forward voltage drop for the 10-kVSiC ETOs with various buffer layer doping concentration.

SiC GTOs on the tradeoff performance of the 10-kV SiC ETOs.Fig. 9 shows the tradeoff curve between the forward voltagedrop at 30 A/cm2 and turn-off energy loss in 10-kV SiC n- andp-type ETOs at room temperature. It shows that the SiC n-typeETO can achieve about a factor of eight lower turn-off loss withthe same forward voltage drop than that of the p-type ETO.Therefore, the high-voltage SiC n-type ETO is preferred due toits superior performance to the p-type ETO. With an ambipolarlifetime of 600 ns in the drift layer and 3-µm-thick buffer layerin the 10-kV SiC n-type GTO, when the buffer layer dopingconcentration increases from 4 × 1016 cm−3 to 4 × 1017 cm−3 ,the forward voltage drop of the 10-kV SiC n-type ETO increasesby 18% to 5.08 V while its turn-off energy loss reduces by 81%to 6.6 mJ. The very low loss of the 10-kV SiC n-type ETOshows that it can operate at a 10-kHz frequency with a conven-tional thermal management system. An appropriate buffer layershould have about 3 µm thick and a doping concentration ofaround 4 × 1017 cm−3 for the 10-kV SiC n-type GTO in theSiC ETO at a switching frequency of 10 kHz and a duty cycleof 0.8.

C. Effect of Drift Layer Carrier Lifetime to the Tradeoff Per-formance of the 10-kV SiC n-Type ETO

The extent of the conductivity modulation in the drift layerand the current gain of the lower transistor of the SiC GTOare governed by the ambipolar lifetime of the carriers in thedrift layer, so another idea to improve the tradeoff relation-

Fig. 10. Theoretical turn-off loss versus forward voltage drop for the 10-kVSiC n-type ETO with various drift layer carrier lifetime and buffer layer dopingconcentration in the SiC GTO.

ship between the forward voltage drop and turn-off loss of theSiC ETO is to adjust the carrier lifetime in the lightly dopeddrift layer of the SiC GTO. Cree’s thick epitaxial growth rou-tinely produces material with carrier lifetime in the 300 ns to2 µs range [17], [25]–[27]. The effect of the carrier lifetime inthe drift region to the tradeoff performance of the 10-kV SiCn-type ETO was investigated with numerical 2-D simulations.The curve A in Fig. 10 shows the theoretical turn-off energyloss versus forward voltage drop for the 10-kV SiC n-type ETOwith various drift layer carrier lifetimes and the same 3-µm-thick 4 × 1017 cm−3 doped buffer layer in the SiC GTO. Thecurve B in Fig. 10 shows the tradeoff curve of the 10-kV SiCn-type ETO with various buffer layer doping concentrations atthe same drift layer carrier ambipolar lifetime of 2 µs in theSiC GTO. The curve C in Fig. 10 shows the zoom in tradeoffcurve of the n-type 10-kV SiC ETO in the Fig. 9 with variousbuffer layer doping concentration at the same drift layer carrierlifetime of 600 ns in the SiC GTO. The curves in Fig. 10 showthat the SiC n-type GTO with a long drift layer carrier lifetimeis superior to those with a short drift layer carrier lifetime for thetradeoff between the forward voltage drop and turn-off loss ofthe SiC ETO. Because the current gain of the lower transistor isdominated by the heavily doped buffer layer for the SiC n-typeGTO with low injection efficiency from the p+ substrate, somerecombination current exits in the buffer layer of the lower life-time device, but the net effect on the device tradeoff performance


is small. The optimum drift region carrier lifetime of the 10-kVSiC GTO in the SiC ETO should be slightly more than 1 µs foroverall power dissipation at a 10-kHz switching frequency anda conduction duty cycle of 0.8.

D. Reverse Bias Safe Operating Area (RBSOA) of 10-kV SiCn-Type ETO

When the unity gain turn-off is established for the SiC n-typeETO, the electron injection at the upper emitter of the SiC n-typeGTO stops and the net extraction of excess carriers from the ndrift layer results in an expansion of the depletion region. Thenthe anode voltage rise at a rapid rate to support the expansionof the depletion region at the p-base/n− drift layer junction. Atthe left hand side of the boundary depletion layer, holes areextracted away from the modulated boundary depletion region.Due to the high electric field prevalent in the depletion region,the holes pass through the depletion region to the p-base atthe saturated drift velocity (vsat,p ). The hole current stronglydetermines the current density controlled effective doping con-centration. Assuming the current distribution in the SiC n-typeGTO cell is uniform during the turn-off transient, the effectivecarrier concentration in the drift region is given by

Neff ≈ ND +|JA |

qvsat,p(1)

where ND is the n− drift layer doping concentration (in inversecubic centimeters), vsat,p is the hole saturated drift velocity (incentimeters per second) and its value is about 8.6 × 106 cm/sfor 4H-SiC [28], and JA is the anode current density (A/cm2).

The electric field distribution in the depletion region is de-termined by the effective carrier concentration (Neff ). Poisson’sequation in the depletion region is expressed as

dE(x)dx

= − q

εsNeff ≈ − q

εs

(ND +

|JA |qvsat,p

). (2)

The presence of the holes in the depletion region increasesthe slope of the electric field profile and the peak electric fieldat the p-base/n− drift layer junction. When the peak electricfield in the depletion region reaches a critical value (EC ), theavalanche breakdown occurs. The dynamic avalanche break-down (or avalanche injection) is the basic failure mechanism ofthe SiC GTO. For the high-voltage Si bipolar devices, the sec-ond term on the right-hand side of (2), the current-controlledcarrier concentration, is much larger than the first term (ND )and the first term can be negligible at a high current density.However, because the critical electric field of 4H-SiC is aboutten times larger than that of Si, for the same breakdown volt-age, the doping concentration in the drift region of the 4H-SiCpower devices is about 200 times larger than that of the Sidevices. Therefore, the effect of the current-controlled carrierconcentration on the electric field distribution in the SiC bipolardevices is much weaker than that of the Si bipolar devices at the

same current density due to the much higher drift layer dopingconcentration in the SiC GTO.

It has been noted that the dynamic avalanche breakdown oc-curs when the peak electric field in the depletion region reachesthe critical electric field EC . To evaluate the onset of the dynamicavalanche breakdown, an empirical relation may be establishedfor the dependence of the critical electric field (in volts percentimeter) on the effective carrier concentration [29],

EC =2.49 × 106

1 − (1/4) log10(Neff /1016). (3)

According to Gauss’s law, the avalanche breakdown of thepunch through SiC GTO occurs with a triangular electric fieldprofile only when the anode current density is higher than thecurrent density (Jth ) given by

|JA | > Jth = qvsat

(εsEC

qWpt− ND

). (4)

For the designed 10-kV SiC n-type GTO, the current densityof Jth = 400 A/cm2 is required to form a triangular electricfield profile in the avalanche breakdown. Ignoring the effect ofthe bipolar transistor current gain to the breakdown voltage ofthe SiC GTO, when the load current is below Jth (|JA | < Jth ),the electric field in the drift layer is a trapezoidal profile and theonset voltage for the dynamic avalanche breakdown of n-typeSiC ETO is simply expressed as

BVdy ≈ EC W −qNeff W 2

pt

2εs

=2.49 × 106

1 − (1/4)log10 ([ND + (JA /qvsat,p)]/1016)

× Wpt − 9.42 × 10−8(

ND +|JA |

qvsat,p

)W 2

pt (5)

where Wpt is the drift layer thickness of the punch throughGTO.

When |JA | > Jth , the onset voltage for the dynamicavalanche of the n-type SiC ETO is expressed as (6), shownat the bottom of this page.

Similarly, the onset voltage for the dynamic avalanche of thehigh-voltage silicon n-type bipolar devices is expressed as

BVdy ≈ 12EC W =

εsEC (Neff)2

2qNeff=

5.34 × 1013

(ND + (JA/qvsat,p))3/4 .

(7)Curves A and B in Fig. 11 show the theoretical onset dynamic

avalanche breakdown voltage of the 10-kV Si ETO and SiC n-type ETO, respectively. It indicates that the power density at theonset dynamic avalanche point of the 10-kV SiC ETO is morethan 7 MW/cm2 , while the power density at the onset dynamicavalanche point of 10-kV Si ETO is less than 300 kW/cm2 . Itindicates the SiC ETO has much better ruggedness than the Si

BVdy ≈ 12EC · W =

εsEC (Neff )2

2qNeff=

εs · (2.49 × 106/(1 − 14 log10([ND + (JA/qvsat,p)]/1016)))2

2q(ND + (|JA |/qvsat,p)). (6)


Fig. 11. Onset of dynamic avalanche breakdown of the 10-kV SiC and SiETOs and the comparison with SiC ETO’s turn-off I–V trajectory in a normaloperation condition.

bipolar power devices. The curve C in Fig. 11 shows the turn-off I–V trajectory of the 10-kV SiC ETO in a normal operationcondition, as shown in Fig. 8. Compared to the turn-off trajec-tory in a normal condition, the large onset dynamic avalanchebreakdown voltage shows the robust turn-off capability of high-voltage SiC ETOs.

IV. CONCLUSION

The SiC ETO is a novel three-terminal MOS-controlled de-vice. It makes use of the high-voltage blocking and excellentcurrent conduction capability of the SiC thyristor and the easydrive interface of the Si power MOSFETs. The 4.5-kV proto-type reported here demonstrates the operation of the SiC ETOand its improved switching performance compared with siliconpower devices, such as a faster switching speed, lower loss, andexcellent turn-off ruggedness.

The optimization design of 10-kV SiC ETO is presented withthe numerical simulation and theoretical analysis to show thepotentially improved performance of high-voltage (>5 kV) SiCETOs. The simulation results predict the high-voltage (10-kV)SiC n-type ETO has a much lower turn-off loss capable ofhigh-frequency (∼10 kHz) applications than the p-type ETObecause of a smaller lower transistor current gain with lowerinjection efficiency from the incompletely ionized p+ substratein the SiC n-type GTO. The effects of the buffer layer dopingconcentration and the drift layer lifetime of the SiC GTOs on thetradeoff performance of the SiC ETOs are investigated for thefurther optimization design of the 10-kV SiC ETOs. A long driftlayer carrier lifetime and an appropriate buffer layer design inthe SiC GTOs can achieve a good tradeoff between the forwardvoltage drop and turn-off loss for the high-voltage SiC ETOs.The theoretical analysis and numerical simulations show thatthe high-voltage (10 kV) SiC n-type ETO has a wide RBSOA,benefiting from the high critical electric field of the SiC material.The advantages of the SiC ETO, low forward voltage drop,fast speed, small switching loss, and wide RBSOA, make itsuitable and attractive for high-voltage (>5 kV) high-frequencyapplications. Further efforts are being made to develop highervoltage (>5 kV) SiC n-type GTOs and ETOs.

ACKNOWLEDGMENT

The authors would like to thank Cree, Inc., for the supply ofthe prototype SiC GTO and diode.

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Jun Wang (S’06) was born in Huanggang, China.He received the B.S. degree in electrical engineeringfrom Huazhong University of Science and Technol-ogy, Wuhan, China, in 2000, the M.S. degree fromthe Institute of Semiconductors, Chinese Academyof Sciences, Beijing, China, in 2003, and the M.E.degree in electrical engineering from the Universityof South Carolina, Columbia, in 2005. He is cur-rently working toward the Ph.D. degree at the Depart-ment of Electrical and Computer Engineering, NorthCarolina State University, Raleigh.

From 2000 to 2005, he focused on III-nitrides UV detectors and LEDs. Hiscurrent research interests include the design, characterization, modeling, andapplications of SiC power devices.

Alex Q. Huang (S’91–M’94–SM’96–F’05) was bornin Zunyi, China. He received the B.Sc. degree fromZheijiang University, Hangzhou, China, in 1983, andthe M.Sc. degree from Chengdu Institute of RadioEngineering, Chengdu, China, in 1986, both in elec-trical engineering, the Ph.D. degree from CambridgeUniversity, Cambridge, U.K., in 1992.

From 1992 to 1994, he was a Research Fellow atMagdalene College, Cambridge. From 1994 to 2004,he was a Professor at the Bradley Department of Elec-trical and Computer Engineering, Virginia Polytech-

nic Institute and State University, Blacksburg. Since 2004, he has been withNorth Carolina State University, Raleigh, where he is currently the ProgressEnergy Distinguished Professor of Electrical and Computer Engineering. Since1983, he has been involved in the development of modern power semiconduc-tor devices and power integrated circuits. He fabricated the first insulated gatebipolar transistor (IGBT) power device in China in 1985. He is the inventor anda key developer of the emitter turn-off thyristor technology. His current researchinterests include utility power electronics, power management microsystems,and power semiconductor devices. He has authored or coauthored more than100 papers published in international conferences and journals, and has 14 U.S.patents.

Prof. Huang is the recipient of the National Science Foundation (NSF)CAREER Award and the prestigious R&D 100 Award.

Documents

Design and Characterization of High-Voltage Silicon Carbide Emitter Turn-off Thyristor