DESIGN AND COMPARISON OF SERIAL AND PARALLEL ADDER /SUBTRACTOR

Description :

1) This project implements the design of 12 bit serial adder/subtractor .2) Eight signed input no’s are taken each of width 12 bits.3) Simulation results of Serial and parallel adder are obtained.4) Project is implemented using verilog coding.5) Comparisons result are verified using synthesis.

PROJECT OBJECTIVES –

Comparison of speed and gate count of serial and parallel adder/subtractor.

GOALS –

Advantage and disadvantages of serial and parallel adder/subtractor and applications of them according to user requirements.

EXPECTED RESULTS :

TYPE OF ADDER SERIAL PARALLEL

NO. OF INPUT CYCLES 8 1NO. OF OUTPUT CYCLES 9 1GATE COUNT LESS GREATERMAX. FREQUENCY OF OPERATION GREATER LESSSPEED SLOW SPEED

DESIGN CONSTRAINTS:

1) All the inputs in serial adder/subtractor must be synchronized with the clock.

2) Use of register and wire should be taken care of while doing verilog coding.