Design and Control for LCL Based Inverters With Both Grid Tie and Standalone Parallel Operations

Design and Control for LCL-Based Inverters with Both Grid-Tie and Standalone Parallel Operations

Chien-Liang Chen, Jih-Sheng Lai, Yu-Bin Wang, Sung-Yeul Park, and Hide Miwa

Virginia Polytechnic Institute and State University Future Energy Electronics Center

415 Whittemore Hall, Blacksburg, VA 24061-0111, USA [email protected], [email protected], [email protected], [email protected], and [email protected]

Abstract—The inductor-capacitor-inductor (LCL) filter allows higher noise attenuation and universal output in which a power conditioning system or an inverter can operate in both grid-tie and standalone modes. In this paper, the LCL filter design considerations including sensor position selection and component selections are discussed for single-phase paralleled inverters operating in both grid-tie and standalone modes. For grid-tie mode operation, each inverter is operating under a single current loop with proportional-resonant controller and admittance path compensation to reduce the steady-state error by providing a high gain at the fundamental frequency. For standalone mode operation, one of the inverters is implemented with a dual-loop controller to regulate the output voltage while the rest inverters operate in single current-loop controller with communication channels in between to ensure the uniformity of current sharing. Both the simulation and experimental results verify that the designed controllers are capable of paralleling inverter operation in grid-tie and standalone modes by adapting to different controller settings while keeping the same hardware setup.

Keywords-LCL filter, grid-tie inverter, dual-loop control, PR controller, parallel inverter, admittance compensation.

I. INTRODUCTION The parallel inverter systems have demonstrated many

advantages compared to a single high-power inverter [1-8]. For example, an inverter can be designed in modular manner which allows the system capacity to be multiplied and the reliability can be greatly improved with redundancy. Parallel inverter operation has been a major topic in uninterruptible power system (UPS) applications where the design is focused on the standalone operation, and the output stage is typically an inductor-capacitor (LC) filter. When connecting the paralleled inverters to utility grids, the capacitor becomes redundant, and thus either a pure inductor (L) or an LCL filter can be used as the inverter output stage. Compared with the L filter, the LCL filter is more attractive [9] because it can not only provide higher high-frequency harmonics attenuation with the same inductance value, but also allow the inverter to operate in both standalone and grid-tie modes, which makes it a universal inverter for distributed generation applications such as fuel cell and photovoltaic power conditioning system (PCS).

Major factors that were used in LCL design considerations include inductor current ripple magnitude and reactive power consumption in capacitor [10], the range of LCL resonant frequency, and the total inductance value of LCL filter [11]. In

this paper, the sensor position selection and the universal application in both grid-tie and standalone modes are added as the LCL design factors.

The compliance of interconnect standards IEEE 1547 and 1547.1 [12,13] and their current harmonic limits can also be used in the LCL design criteria. However, the cause of inverter harmonic distortions were mainly found in nonlinear effects such as nonlinear device voltage drop, dead time, limited PWM resolution and lack of stiffness in dc link [14]. The controller with high gain at the harmonic frequencies such as proportional-resonant (PR) controller [15] and direct-quadrant (DQ) frame current controller [16,17] can be potential candidates to alleviate such harmonic distortions.

In addition to harmonic concerns, the controller design for parallel inverter systems must consider stability and steady-state error issues. In general, parallel inverters are designed in standalone mode for UPS and distributed generation (DG) systems that supply regulated output voltages when grid is not available. Most reported standalone inverter systems use a LC filter and proportional-integral (PI) controller in their control loops [18-20]. In [18,19], multiple feedback loops were proposed to improve the output voltage performance and to damp the poles of LC filter. In [20], feedback, feed-forward, and nonlinear controls were considered for the entire UPS control system. These parallel inverter systems, however, are usually designed with LC filter [1-8] which will have difficulties in grid-tie operations due to the undetermined resonant frequency caused by the change of grid-side source impedance [21]. The design of parallel inverters also needs to consider the current sharing capability [5-6] and the communication [7-8] among paralleled inverters. In [5], some current-sharing schemes for parallel inverter systems including master-salve control, current-limit control, and circular-chain control are examined and compared. In [6], a current-weight-distribution control was proposed to allow inverters in parallel with different output current capability. In [7], the controller area network (CAN) communication interface is utilized in a parallel inverter system to obtain a higher reliability. In [8], a new voltage and frequency droop control for parallel inverter systems is proposed to allow a robust current sharing without communication between inverters.

In this paper, the paralleled inverters adopt the LCL filter as the output stage to allow the inverter to operate in both grid-tie

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and standalone modes. The design procedure of LCL filter in this universal inverter including sensor position and component selection will be discussed. By selecting the filter capacitor voltage and inverter-side inductor current as control feedbacks, the controller of LCL-filter inverter can be easily designed. For grid-tie operation, the current loop employs a PR controller and admittance compensation to achieve high loop gain at the fundamental frequency and to eliminate negative power flow transient during start-up. For standalone operation, one of inverters is selected to incorporate a voltage loop in a dual-loop control system with PR-controller on the voltage loop and a P-controller on the current loop to limit current magnitude under transient, to enhance voltage loop stability, to allow equal current sharing, and to reduce voltage steady-state error. The rest of inverters operate in grid-tie mode with only current loop control to share the load current. Both the simulation and experimental results verify that the designed controllers are capable of paralleling inverter operation in grid-tie and standalone modes by adapting to different controller setting while keeping the same hardware setup.

II. LCL DESIGN CONSIDERATIONS

A. System Configuration of LCL-Based Inverter Fig. 1(a) shows the system configuration of an LCL filter

inverter operating in the grid-tie mode. Depending on the input voltage level, if the input voltage Vin is low and highly unregulated such as fuel cell and PV source, a dc-dc converter is needed before the inverter stage. The inverter output inductor Li, the filter capacitor Cf, and the grid-side inductor Lg constitute the LCL filter of the inverter. In grid-tie applications, the load is normally modeled as a constant voltage source vs in series with a source impedance Ls. Because the grid voltage is known, the way to control the power sending to the grid is to control the inverter output current with current-mode control. Fig. 1(b) represents the LCL inverter used for the standalone operation. On the other hand, most of the standalone loads require the output voltage to be regulated to supply the loads with a desired voltage.

Li Lsiac igLg

vacdc-ac

inverter Grid

vsCf vg

vidc-dc

converterVin Vdc

(a)

Loaddc-acinverter

dc-dcconverter

Vin Vdc

Liiac iLoadLg

vacCf vbusvi

(b)

Fig. 1. (a) LCL based inverter in grid-tie application, and (b) LCL based inverter in standalone application.

B. Sensor Position Selection for the LCL-Based Inverter First of all, the grid-side voltage vg needs to be sensed for

synchronization in grid-tie operations. Next, the capacitor voltage vac needs to be sensed to regulate output voltage in

standalone mode operations. In addition, by selecting the vac and inverter-side-inductor current iac as feedback signals instead of vg or grid-side inductor current ig, the duty-cycle-to-output-current transfer function in grid-tie mode will be a first-order system which will greatly simplify the controller design [9]. Furthermore, compared to the current sensor signal ig, feedback of current iac not only allows the sensor to be easily integrated into the inverter but also reduces the noise in the sensor conditioning circuit because the physical sensor location is closer to the controller board.

C. Selection of Inverter-Side Inductor Li The selection of the inverter-side inductor Li should

compromise the output current performance, system cost, size, and efficiency. For example, with a higher Li value, lower current ripple can be obtained and higher controller gain can be designed to obtain better current performance. Using iac as the feedback current signal, the simplified duty-cycle-to-current transfer function of an LCL inverter Gid(s) can be expressed in (1).

i

dcacid sL

VsdsisG ==)()()( (1)

Here d is the inverter duty cycle, and Vdc is the dc link voltage. However, higher inductance value requires higher cost and occupies larger volume. As for the efficiency, higher inductance allows lower current ripple in the inductor Li, which decreases core losses of the inductor. On the other hand, higher inductance value increases the winding loss for longer wire required. The total inductor losses depend on the core materials, core structures, wires, and winding methods.

D. Selection of the Filter Capacitor If the inverters are implemented only for grid-tie

applications, the selection of Cf can be determined by limiting the reactive power consumed in Cf [10,11]. On the other hand, in the design of universal inverters, the selection of the filter capacitor will be determined by the required voltage ripple damping because the inverter-side inductor Li and the filter capacitor Cf will form a second-order filter that provides a -40dB/dec attenuation after the resonant frequency of this Li-Cf filter.

E. Selection of the Grid-Side Inductor Lg For the grid-tie inverter shown in Fig. 1(a), the transfer

function from duty cycle d to iac can be derived in (2).

( )( )

2

( )( )

( ) 1

ac dc

i g si g s f

i g s

i s Vd s L L L

s L L L s CL L L

=⎧ ⎫⎡ ⎤+⎪ ⎪⎡ ⎤+ + + ⎢ ⎥⎨ ⎬⎣ ⎦ + +⎢ ⎥⎪ ⎪⎣ ⎦⎩ ⎭

(2)

As compared to (1), the denominator of (2) has two more resonant poles that may cause the stability issues. In [21], this resonant frequency was limited in the range neither close to the current cross-over frequency nor close to the switching frequency to avoid resonance issues. After Li and Cf are determined, Lg needs to be selected so that the resonant frequency is in a proper frequency range to ensure the stability.

2


III. PROPORTIONAL-RESONANT CONTROLLER FOR GRID-TIE INVERTER OPERATION

The control object in grid-tie operation is its output current because the output voltage is already determined by the grid. The control system shown in Fig. 2 employs the voltage across the filtering capacitor, vac and the current of the inverter-side inductor, iac as the feedback signals. Such an arrangement allows the first-order control-to-current transfer function Gid(s) shown in (1) to be used for controller design.

vaciref

ifb

vd(t)ierr

_+ FmGi (s)

iacdGid(s) Gvi(s)

Gf (s) HiTi(s)

+–

Giv(s)Gicloop(s)

vaciref

ifb

vd(t)ierr

_+ FmGi (s)

iacdGid(s) Gvi(s)

Gf (s) HiTi(s)

+–

Giv(s)Gicloop(s)

Fig.2. Control block diagram of a current controlled inverter for grid-tie

operation.

As indicated in [9], capacitor voltage vac introduces an undesired current, and its relationship can be expressed in (3). Here Giv(s) can be considered as an intrinsic admittance, which causes a negative current flow and can damage the system by overcharging the dc-link capacitors.

iLiac

aciv sLrsv

sisG+

== 1)()()( (3)

Here the Li and rLi are the inverter-side inductance and its equivalent resistance, respectively. This undesired admittance term Giv(s) can be eliminated by an admittance compensation, and thus allowing the following duty-cycle-to-output-current Gid(s) to be used in the controller design.

iLi

dcacid sLr

VsdsisG

+==

)()()( (4)

Equations (4) and (1) are essentially the same except the (1) neglects the resistive component rLi. For the system under test, Vdc = 420V, rLi = 80mΩ, and Li = 1mH. Negligence of rLi should not impact the controller design. The open current loop gain Gioloop(s) controlled inverter can be obtained in (5).

( ) * ( )* * ( )ioloop m id i lfG s F G s H G s= (5)

Here Glf(s) is the low-pass filter combination in the hardware which includes a second-order low-pass filter at 48 kHz and a first-order anti-aliasing filter at 9.6 kHz. Hi is the current feedback gain with a 34.133 magnitude, and Fm is the DSP modulation gain with a magnitude of 1/1250. The design purpose of the current-controlled inverter is to provide an output current that tracks the external command as close as possible, a PR controller shown in (6) is utilized to provide a high loop gain at the fundamental frequency [15].

2 21

2( )

2c r

i pc

k sG s k

s sωω ω

= ++ +

(6)

Here kp is the proportional gain, kr is the resonant gain, ωc is the equivalent bandwidth, and ω1 is the fundamental angular frequency. With the designed controllers, the compensated loop gain Ti(s) can be represented in (7).

( ) ( )* ( )i i ioloopT s G s G s= (7)

By choosing kp = 0.78, kr = 97.5, ωc = 10 rad/second, and ω1 = 377 rad/second in Gi(s), the Bode plots of Gioloop(s) and Ti(s) can be shown in Fig. 3.

-50

0

50

100

Mag

nitu

de (d

B)

101 102 103 104-180

-90

0

90

Phas

e (d

eg)

Frequency (Hz)

69.2dB

Ti(s)

Gioloop(s)

Ti(s)

Gioloop(s)fc= 1.46kHz

P.M. = 63.2。

-50

0

50

100

Mag

nitu

de (d

B)

101 102 103 104-180

-90

0

90

Phas

e (d

eg)

Frequency (Hz)

-50

0

50

100

Mag

nitu

de (d

B)

101 102 103 104-180

-90

0

90

Phas

e (d

eg)

Frequency (Hz)

69.2dB

Ti(s)

Gioloop(s)

Ti(s)

Gioloop(s)fc= 1.46kHz

P.M. = 63.2。

Fig.3. The Bode plots of compensated current loop gain Ti(s) and current open

loop gain Gioloop(s).

IV. VOLAGE DUAL-LOOP CONTROLLR FOR STANDALONE INVERTER OPERATION

A. Control Block Diagram As shown in Fig. 4, the inverter is controlled in a dual-loop

voltage control [18,19] to ensure system safety and enable current sharing capability among parallel inverters. In this dual-loop controller, a current inner loop damps the LC resonance pole while a voltage outer loop regulates the output voltage.

iref

ifb

vd(t)ierr

_+ FmGi (s)

iacdGid(s) Gvi(s)

vacvref

vfb

verr

_+ Gv(s)

Glf (s) Hi

Glf (s) Hv

Ti(s)

+–

Giv(s)Gicloop(s)iref

ifb

vd(t)ierr

_+ FmGi (s)

iacdGid(s) Gvi(s)

vacvref

vfb

verr

_+ Gv(s)

Glf (s) Hi

Glf (s) Hv

Ti(s)

+–

Giv(s)Gicloop(s)

Fig.4. Control block diagram of a voltage dual-loop controlled inverter for

standalone operation.

B. Inner Current Controller Design Because of the same inverter hardware setup, the current

open loop transfer function Gioloop(s) is the same as that shown in (5). However, the design goal of the current loop in a dual-loop control is to have a high loop bandwidth with enough stability margin rather than to reduce the current steady-state error by providing a high gain at fundamental frequency. With the first-order loop transfer function Gioloop(s), this current controller is only a simple proportional gain with a software low-pass filter shown in (8).

( ) 0.5( )

SWFi

SWF

G ss

ωω

=+

(8)

3


Even though the control system does not contain any resonant poles by carefully selecting the sensor positions, the LCL filter hardware does contain resonant poles that could cause resonance on output voltage and current, as indicated in (2). The LCL parameters are Li = 1 mH, Cf = 6.8 μF, Lg = 0.22 mH which results in a resonant frequency at 4.54 kHz. Thus a 1.5 kHz software first-order low-pass filter is designed to damp possible oscillations at outputs. With the designed current controller, the compensated current loop gain Ti(s) is shown in (9). The Bode plots of Ti(s) and Gioloop(s) can be shown in Fig. 5.

Ti(s) = Gi(s)⋅Gioloop(s) (9)

101 102 103 104-270

-180

-90

0

Phas

e (d

eg)

-40-20

0

20

40

Mag

nitu

de (d

B)

Frequency (Hz)

23.4dB

Ti(s)

Gioloop(s)

Ti(s)

Gioloop(s)

fc= 802HzP.M. = 56.1。

101 102 103 104-270

-180

-90

0

Phas

e (d

eg)

-40-20

0

20

40

Mag

nitu

de (d

B)

Frequency (Hz)

23.4dB

Ti(s)

Gioloop(s)

Ti(s)

Gioloop(s)

fc= 802HzP.M. = 56.1。

Fig.5. The Bode plots of compensated current loop gain Ti(s) and current open

loop gain Gioloop(s).

C. Outer Voltage Controller Design After closing the inner current loop, the outer open voltage

loop gain can be expressed in (10). Gvoloop(s) = Gicloop(s)*Gvi(s)*Hv*Glf(s) (10) Here Hv is the voltage sensor feedback gain, which is 5.12

in the test case. Gicloop(s) and Gvi(s) are the current closed loop gain and output current to output voltage transfer function, respectively. Equation (11) expresses the closed-loop gain of the inner current loop, Gicloop(s).

( )* * ( )

( )1 ( )

i m idicloop

i

G s F G sG s

T s=

+ (11)

Assume that the load is a pure resistive load with a Ro value in Fig. 1(b), the output current to output voltage transfer function Gvi(s) can be represented in (12).

( )( )

2

1

1 2

2

1 1

( )* * ( )

4, , ,2

11, ,

g zvi

g f

oz p p

g

o

g g f

L sG s

L C s p s p

R b b acL a

Ra b c

L L C

ω

ω ω ω

+=

+ +

⎡ ⎤− ± −= = − ⎢ ⎥⎢ ⎥⎣ ⎦

= = =

(12)

The design goal of a dual-loop voltage controller is to obtain a high gain at the fundamental frequency while providing enough bandwidth and stability margin. As shown in (13), a PR controller is adopted here to eliminate the steady-

state error by providing a high gain at the fundamental frequency.

2 21

2( ) ( )

2c r

v pc

k sG s k

s sωω ω

= ++ +

(13)

With 20% load as the design plant, a PR controller is designed to have kp = 0.02, kr = 12, c = 10 rad/s, and 1 = 377 rad/s. The resulting Bode plots of the compensated voltage loop gain Tv(s) = Gv(s)*Gvoloop(s) along with the uncompensated voltage loop gain Gvoloop(s) are shown in Fig. 6.

-100

-50

0

50

Mag

nitu

de (d

B)

101 102 103 104-360

-180

0

180

Phas

e (d

eg)

Frequency (Hz)

38.6dB

Tv(s)

Gvoloop(s)

Tv(s)

Gvoloop(s)

fc= 262HzP.M. = 53.2。

-100

-50

0

50

Mag

nitu

de (d

B)

101 102 103 104-360

-180

0

180

Phas

e (d

eg)

Frequency (Hz)

-100

-50

0

50

Mag

nitu

de (d

B)

101 102 103 104-360

-180

0

180

Phas

e (d

eg)

Frequency (Hz)

38.6dB

Tv(s)

Gvoloop(s)

Tv(s)

Gvoloop(s)

fc= 262HzP.M. = 53.2。

Fig.6. The Bode plots of compensated voltage loop gain Tv(s) and voltage

open loop gain Gioloop(s) in a dual loop controlled inverter at 20% rated power.

V. PARALLEL INVERTERS WITH LCL FILTERS UNDER STANDALONE MODE

A. System Configuration The parallel inverter system under standalone has the same

hardware configuration as that under grid-tie mode configuration except that the load is replaced with a source. Fig. 7 shows the entire system diagram. In this system, one of the inverters needs to be operating in dual loop control and serve as the voltage reference or the grid voltage source. The rest of inverters will be operating in grid-tie mode, and a single current loop will serve the control purpose.

Liiac1 iout1Lg

vac1Cf vbusvi1RLoadiload

inverter1

Liiac2 iout2Lg

vac2Cf vbusvi2inverter

2

Liiacn ioutnLg

vacnCf vbusvininverter

n

dc-dcconverter

Vin-1 Vdc1

dc-dcconverterVin-2 Vdc2

dc-dcconverterVin-n Vdcn

Fig. 7. Hardware configuration of paralleled LCL based inverters.

The selection of the inverter running in dual-loop mode or single-loop mode is determined by the upper level command line, which comes from a CAN bus. Fig. 8 shows the control system diagram with multiple inverters in parallel. Here

4


inverter 1 operates in dual loop and provides the voltage reference. Inverter 2 and the rest will lock the phase to the reference voltage and operate in single current loop.

iref 1

ifb

vd1(t)ierr1

_+ FmGi (s)

iac1d1 Gid(s) Gvi(s)vac1vref 1

vfb1

verr1

_+ Gv(s)

Gf (s) Hi

Gf (s) Hv

Ti(s)

+–

Giv(s)Gicloop(s)

iref2

ifb2

vd2(t)ierr2

_+ FmGi (s)

iac2d2 Gid(s) Gvi(s)vac2

Gf (s) HiTi(s)

+–

Giv(s)Gicloop(s)

Inverter 1- Voltage Control

×

PLL

PC

PLLAPA

cos(ωt)

iref 1,pkCAN T/R

CAN T/R

Inverter 2- Current Control

iref 1,pk

Inverter n- Current Control

CAN BusPC: Peak value calculationAPA: Automatic phase adjustment

iref 1

ifb

vd1(t)ierr1

_+ FmGi (s)

iac1d1 Gid(s) Gvi(s)vac1vref 1

vfb1

verr1

_+ Gv(s)

Gf (s) Hi

Gf (s) Hv

Ti(s)

+–

Giv(s)Gicloop(s)

iref2

ifb2

vd2(t)ierr2

_+ FmGi (s)

iac2d2 Gid(s) Gvi(s)vac2

Gf (s) HiTi(s)

+–

Giv(s)Gicloop(s)

Inverter 1- Voltage Control

×

PLL

PC

PLLAPA

cos(ωt)

iref 1,pkCAN T/R

CAN T/R

Inverter 2- Current Control

iref 1,pk

Inverter n- Current Control

CAN BusPC: Peak value calculationAPA: Automatic phase adjustment

Fig. 8. Control block diagram of a paralleled LCL inverter system.

B. Current Sharing and Synchronization through CAN Bus In order to share the current between inverters, the CAN

bus is utilized to ensure a reliable communication interface [7]. The simplest way to transmit the current reference is to send the current reference directly in ac quantity. However, this method is not practical for the increasing phase delay in ac signal if the transmission length is too long which limits the transmission speed of the CAN interface.

In order to overcome the phase delay in ac signal, the transmission signal is the magnitude of iref1 in dc quantity. The current reference magnitude information shares the current evenly which minimizes the thermal stress of whole system. The phase is synchronized with a phase-locked loop control, similar to the grid-tie control system. The automatic phase adjustment block shown in Fig. 8 is to adjust the phase information of current reference iref2 automatically by monitoring the phase difference of iac2 and vac2.

VI. IMPLEMENTATION RESULTS

A. Experimental Setup The hardware setup consists of two 5-kW power

conditioning systems. Each PCS consists of a dc-dc converter to boost the low-voltage input 48 V to 400 V and a dc-ac inverter that produces 208 V ac output for the grid connection. The source of the dc-dc converter can be a fuel cell or a photovoltaic, but for this testing, a 60-V, 20-kW fuel cell simulator was used to serve as the source. Each PCS is packaged in a standard 19” rack-mount case with power connection on the back panel, and the DSP controller on the front panel. Fig. 9 shows the photograph of the hardware setup with two identical PCS’s sitting side by side.

dc-dc converter dc-ac inverter

DSP controller

rectifier board filter board

PCS-1

PCS-2

Fig. 9. Photograph showing two parallel connected PCS’s packaged in

standard rack-mount cases.

B. Grid-Tie Mode Operation Fig. 10(a) shows the simulation results of the LCL-filter

inverter running in current-mode control with PR controller and admittance compensation. The results show that the output current follows a 32-A peak command current very well because of a high loop gain at the fundamental frequency. Fig. 10(b) shows the experimental results under 32-A peak current command in the grid-tie condition. Waveforms indicate that the output current well follows the command, which suggests the current loop PR controller with admittance compensation provides a high loop gain at the fundamental frequency to eliminate the steady-state output error.

Time

100ms 150ms 200msI(Lg)

-40A

0A

40A

SEL>>

V(Vac)- V(Vb0)-400V

0V

400Vvac

ig

Time

100ms 150ms 200msI(Lg)

-40A

0A

40A

SEL>>

V(Vac)- V(Vb0)-400V

0V

400Vvac

ig

(a)

t:10ms/div

20A

300V

vac

ig

t:10ms/div

20A

300V

vac

ig

(b)

Fig. 10. Current loop implementation results at 4.85kW (a) Pspice simulation result at 32A iref, pk, , and (b) experimental result at 32A iref, pk.

5


C. Standalone Mode Operation Fig. 11(a) and Fig. 11(b) show the simulation and

experimental results of the duel-loop controlled LCL-filter inverter with a PR-controller based outer voltage-loop and a P-controller based inner current-loop operation. The output voltage vac is 215 V rms, and the output current iload is 24.2 A rms. The power output of 5.2-kW goes into a pure resistive load in both simulated and tested cases. The simulation includes all the dynamics of system transfer function and controller blocks shown in Fig. 4. Again, the experimental result agrees with the simulation result very well.

Time

100ms 125ms 150ms 175ms 200msI(RLoad)

-40A

0A

40A

SEL>>

V(Vac1)- V(Vb01)-400V

0V

400V vac

iload

Time

100ms 125ms 150ms 175ms 200msI(RLoad)

-40A

0A

40A

SEL>>

V(Vac1)- V(Vb01)-400V

0V

400V vac

iload

(a)

t:10ms/div

300V

20A

vac

iload

t:10ms/div

300V

20A

vac

iload

(b)

Fig. 11. Voltage dual-loop results at 215V vac, rms, 5.2kW (a) Pspice simulation result, and (b) experimental result.

Fig. 12 shows the simulation and experimental results of

the paralleled inverters supplying to a 7.6 kW load. Load voltage vload and total current iload are the waveforms observed at the load terminal. Current iout1 and iout2 are monitored at the individual inverters. Both simulation and experimental results indicate that output currents are in phase between two inverters, and both parallel inverters share current evenly to supply the load together. With the observation of total current iload being equal to the sum of iout1 and iout2, one can easily conclude that there is no circulating current in between the dual-loop controlled and single-loop controlled inverters. The phase-locked loop and automatic phase adjustment control work effectively.

The even distribution of current between paralleled inverters also indicates that the CAN communication, that transmits the reference current magnitude to different PCS’s

works well, and the proposed design should allow modular inverter design for a high power paralleled inverter system.

Time

100ms 125ms 150ms 175ms 200msI(Lg_i)

-80A

80A

SEL>>

I(Lg_v)-80A

0A

80AI(RLoad)

-80A

0A

80AV(Vload)- V(Vb01)

-400V

0V

400V vload

iload

iout1

iout2

Time

100ms 125ms 150ms 175ms 200msI(Lg_i)

-80A

80A

SEL>>

I(Lg_v)-80A

0A

80AI(RLoad)

-80A

0A

80AV(Vload)- V(Vb01)

-400V

0V

400V vload

iload

iout1

iout2

(a)

vload

iload

iout1

t:10ms/div

40A iout2

40A

40A

300V

(b)

Fig.12. Parallel inverters operation at 215V vload, rms, 7.6kW (a) Pspice simulation result, and (b) experimental result.

VII. CONCLUSION Complete design and implementation results of a paralleled

power conditioning system operating in both grid-tie and standalone modes were presented in this paper. Key design features of the proposed inverter system are summarized as follows.

1. Design of LCL filter This paper suggested design considerations on current ripple, stability, output performance, sensor location, noise, and ease of controller design.

2. Design of dual- and single-loop controllers For grid-tie operation, a single current loop controller design with PR controller and admittance compensation is proposed to reduce the steady-state error while maintaining system stability. For standalone operation, a dual-loop control system with PR-controller for outer

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voltage loop and a P-controlled for inner current loop is proposed to limit peak current magnitude under transient, enhance voltage loop stability, and reduce voltage steady-state error.

3. Design of synchronization and equal current sharing The synchronization is implemented with PLL and an automatic phase adjustment to synchronize the output currents among different inverters. The CAN bus is adapted as upper level commander to specify one unit to operate in dual loop control and to transmit current reference command magnitude to individual inverters.

Simulation and experimental results show that the designed

inverters are capable of parallel operation in both grid-tie and standalone modes by adapting to different controller sets with the same hardware setup. The LCL filter based inverter controlled with the proposed single- and dual-loop controllers for different operating modes shows stable output waveforms. The output current is equally shared among different inverters without noticeable circulating current by the use of the proposed synchronization and upper level control methods. The successful parallel operation results suggest that the proposed design with LCL filter based inverter, mix of dual- and single-loop voltage and current controllers, PLL synchronization and CAN bus communication architecture can be extended to microgrid or smartgrid applications where both the grid-tie and standalone operations are needed.

ACKNOWLEDGMENT The authors would like to thank Mr. M. H. Lin and his

group of Tatung System Technologies, Taipei, Taiwan for both financial and technical supports of the project.

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Documents

Design and Control for LCL Based Inverters With Both Grid Tie and Standalone Parallel Operations