DESIGN AND IMPLEMENTATION OF A LOW POWER DIGITAL UP · growth in the digital electronics make possible many processes which used to be only theoretically possible. Di erent radio

DESIGN AND IMPLEMENTATIONOF A LOW POWER DIGITAL UP

CONVERTER USING PULSESHAPING FIR FILTER

Dylan Royce Fernandes1 , Vigneshwaran T2,School of Electronics and Communication (SENSE)

VIT UniversityChennai- India

[email protected]

June 25, 2018

Abstract

An efficient reconfigurable root raised cosine filter usingconstant multiplier architecture based on vertical-horizontal binary common sub- expression elimination isdesigned for multistandard digital up converter to reducethe delay and power consumption. According to theproposed VHBCSE algorithm, 2- bit binary common sub-expression elimination is being applied. The proposedtechnique reduces the number of multiplications per inputsample. And can be reconfigured for one of the threeinterpolation factors 4, 6 and 8 for tap filters 25, 37 and49- tap respectively. This method was successful inreducing the delay and power usage and improved theoperating frequency over the earlier reported methods.

Keywords: Brent- Kung Adder, Root- Raised Cosine(RRC) filter, Binary Common Sub- expression Elimination(BCSE), Vertical- Horizontal Binary Common Sub-expression Elimination (VHBCSE), Software DefinedRadio (SDR).

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International Journal of Pure and Applied MathematicsVolume 120 No. 6 2018, 1181-1196ISSN: 1314-3395 (on-line version)url: http://www.acadpubl.eu/hub/Special Issue http://www.acadpubl.eu/hub/

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1 INTRODUCTION

SDR is a radio communication system where components thathave been traditionally been implemented in hardware are insteadimplemented in software [1]. SDR is not a new concept, the rapidgrowth in the digital electronics make possible many processeswhich used to be only theoretically possible. Different radioprotocols can be realized on a single chip by providingprogrammable channel select filter at baseband level in a SDRsystem. Signal to noise ratio, bandwidths, sampling rates,blocking and interference profiles are different for differentchannels [1]. However, to meet all the requirements of multiplechannels one reconfigurable sample rate converter is needed [5].Interpolators using up samplers is used to increase the sample ratewhile decimators using down samplers is mostly used to decreasesample rate. However, using interpolators and decimators leads toaliasing and interference effect. Hence to reduce the undesiredeffect due to sample rate converter a pulse shaping filter isrequired to shape this baseband signal. The pulse in a datatransmission system must have a basic shape in such a way thatat optimal sampling point they do not interfere with one another.The pulse (rectangular) is not suitable for modern communicationsystem since it has unbounded frequency response and has largebandwidth. The root raised cosine and raised cosine are veryappropriate for band limited data transmission where it limits thebandwidth, decay rapidly and supports zero crossing during pulseshaping. A very valuable spectral processing technique in wirelesstransmission is pulse shaping which makes the signals to fit in itsfrequency band. Pulse shaping filters removes both inter- symbolinterference and adjacent channel interference. Root raised cosinefilter is broadly used filter in reconfigurable filter because of itshigh inter- symbol interference elimination ration and highbandwidth limitation. Due to its ability to decrease BER wirelessstandards such as WCDMA, UMTS and DVB use RRC filter aschannel filter. However, in RRC filter different radio protocolsneed different oversampling rates and roll- off factor. Areconfigurable RRC filter is needed to support all standards.Wireless transmission requires minimum number of adders for lowpower and high-speed FIR filter. A technique to reduce the

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number of adders in multipliers of FIR filter is by using CSEtechnique which is best in hardware reduction. The digital signalprocessing uses variable sample rates can boost the flexibility ofSDR. It decreases the requirement of costly anti- aliasing analogfilters and processes different signals with different sampling rates.It enables partitioning of high speed processing into low speedprocessing.

Figure 1: Architecture of RRC filter

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2 LITERATURE SURVEY

A. Data Generator Block

Depending on the selection of interpolation factor data generatorblock samples the input signal. Commonly used wirelessstandards have 25, 37, and 49 taps- filters with interpolationfactor 4, 6 and 8 respectively. The tap- filters mentioned abovecan be implemented using branch filter having seven taps.

[25/4] = [37/6] = [49/8] = 7.....................(1)

It is used as a serial to parallel converter. It consists of amultiplexer and a shift register. Input given to the shift register istransferred depending on the output of the multiplexer. Clockhaving different clock rates are given as input to the multiplexer.Depending on the selected interpolation factor the output clockrate is selected [1] [4].

Figure 2: Architecture of data generator block

B. Coefficient Generator Block

This block performs multiplication of input with the filtercoefficients. It consists of control generator, sign conversion block,

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partial product generator, multiplexed coefficients, multiplexerunit and accumulation unit. Multiplexer is used to structure eachblock in the coefficient generator. The algorithm as shown infigure 3 is VHBCSE algorithm [2]. A sign conversion block isneeded which supports the signed decimal format datarepresentation for the input and for the filter coefficients. Themultiplexed coefficient will be inverted for a negative value and itwill not change for a positive value.

Figure 3: Flow diagram of coefficient generator

a. Partial Product Generator

The shift and add technique is used to generate partial productsfor the multiplication process. In BCSE technique, use of shiftand add technique while realizing CSE eliminates the commonterm present. A 2- bit BCS ranging from 00 to 11 is used in

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implementation of partial product generator. Among the fourBCS only 11 requires an adder. This reduces the hardware forimplementation and improvement in speed for performing themultiplication. The partial product generator block is shown infigure 4.

Figure 4: Partial product generator block

b. Multiplexer Unit

Multiplexer unit is needed to select appropriate data from thepartial product generator. Eight 4:1 multiplexers are needed toselect the partial products according to 2- bit BCSE algorithm.The inputs to each multiplexer is of different bits. Multiplexer(M8) has a 17- bit input and multiplexer (M1) consist of 3- bitinput bit.

c. Control Logic Generator

Multiplexer coefficients are given as input to the control logicgenerator which groups them into two groups one of 4- bits (H[15:12], H [11:8], H [7:4], H [3:0]) each and another 8- bits (H[15:8], H [7:0]). The control logic block will produce seven controlsignals.

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Figure 5: Control logic generator block

d. Controlled Addition at Layer 2

For the final multiplication, the partial products are added up. Asstated in BCS algorithm, layer 2 requires four addition (A1- A4)operations to sum the eight partial products. This addition iscontrolled by six control signal (C1- C6). The multiplexers areused to reduce the power dissipation and propagation delay of thisaddition layer. The outputs of this layer are AS1, AS2, AS3 andAS4. The architecture of the controlled addition layer is shown infigure 6.

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Figure 6: Controlled addition layer 2

e. Control addition at layer 3

The output of controlled addition at layer 2 (AS1- AS4) is givento the input of controlled addition layer 3. It consist of two addersas shown in figure. Control signal C7 is used to control thisaddition layer.

Figure 7: Controlled addition layer 3

Output AS and AS6 is done using a parallel prefix adder. Aparallel prefix adder consist of three stages the pre- computation,

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the prefix network and the post computation. The pre-computation is used to produce the Propagate and Generate bits.The prefix network consist of black cells and gray cells. Thisnetwork is used to compute the final carry and the post-computation is used to compute the final sum. The prefix adder isused for final addition as it reduces the delay, lowers powerdissipation and area consumption is small compared to serialadders.

In figure 8, a constant multiplier architecture is shown. Partialgenerator generates eight outputs (M1- M8) [6]. The constantmultiplier consist of eight 4:1 multiplexers, two controlled additionlayer, a control logic and multiplexed coefficient. The output is aproduct of filter coefficients and input signal

Figure 8: Coefficient generator block

C. Coefficient Selector Block

The coefficient selector block takes different values from data

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generator and coefficient generator. Depending on FLT SELparameter a single sub filter is selected from the seven sub filters.As the branch filter is made of seven taps, seven coefficientselectors are needed. The three block MUXREG4, MUXREG6and MUXREG8 consist of adders and multiplexers these blocksare used to process data depending on the interpolation factor

Figure 9: Coefficient selector block

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D. Final Data Accumulation Block

Figure 10: Final data accumulation block

The data accumulation block consists of six adders and six registersconnected in a chain. FA block is fully pipelined to get maximumfrequency

3 PROPOSED WORK

BCSE’s are of two types vertical and horizontal BCSE which areused for eliminating BCSs present in adjacent coefficients.However, in the proposed work a combination of vertical andhorizontal BCSE is used in design of RRC filter. In this proposedalgorithm the number of multiplexers are less [2].

Data generator block consist of multiplexer and a shift register.Clock gating technique is applied to the shift register to achievelow power. The proposed design also helps to reduce the areaconsumption.

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Figure 11: Proposed data generator block

In the final addition block (parallel prefix adder) the use of Brent-Kung adder for addition achieves a low power and low delayconstant multiplier. Brent- Kung adder uses logarithmic concept.This concept is considered as among the fastest structures. Thelogarithmic concept is used to combine its operands in a tree likestructure. The delay of this structure is equal to (log2N) t, where’N’ is number of input bits to the adder and ’t’ is the propagationdelay. Coefficient selector block proposed here uses seven subfilters since 25, 37 and 49 tap- filter with interpolation factor 4, 6and 8 to implement these three filters in a single design a 7- bitbranch filter is needed so since we use a 7- bit branch filter weneed seven sub filters (coefficient selector). Depending on theinterpolation factor the tap filter is selected. Final dataaccumulation unit consist of six adders and six registers.

4 RESULT

Figure 12: Output waveform of data generator block

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Figure shows output waveform of data generator block whereRRCin is the input given to the shift register, INT SEL is theinterpolation factor selection parameter.

Figure 13: Output waveform of Brent- Kung adder

Brent- Kung adder output is shown in figure 13. This adder is alow power adder and uses minimum circuitry to obtain the result.Two 16- bit inputs are given to the adder at ’a’ and ’b’ and outputis taken at ’out’.

Figure 14: Output waveform of coefficient selector

Figure 14 shows output waveform of coefficient selector. Thecoefficient block is used to steer correct data to the finalaccumulation block depending on the interpolation factor. Inputto coefficient selector is from data generator as well as fromcoefficient selector blocks.

Figure 15: Output waveform of final data accumulation unit

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5 CONCLUSION

A low power high speed architecture for implementing multi-tapRRC filter has been proposed. Multiplexer based design reduces thepower dissipation. BCSE algorithm is used to achieve an efficientFIR filter. By using this, algorithm there will be increase in theefficiency of the filter.

References

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[2] N. Anusha, B. V. Naik, ”Design and Implementationof Reconfigurable FIR Filter using VHBCSE Algorithm,”IJRAET, vol. 5, Oct. 2016.

[3] S.-J. Lee, J.-W. Choi, S. W. Kim, and J. Park, ”Areconfigurable FIR filter architecture to trade off filterperformance for dynamic power consumption,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 12, pp.22212228, Dec. 2011.

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[7] Y. J. Yu and Y. C. Lim, ”Optimization of linear phaseFIR filters in dynamically expanding subexpressions space,”Circuits, Syst., SignalProcess., vol. 29. no. 1, pp. 6580, 2010.

[8] S. F. Lin, S. C. Huang, F. S. Yang, C. W. Ku, and L. G.Chen,”Power-efficient FIR filter architecture design for wirelessembeddedsystem,” IEEE Trans. Circuits Syst. II, Exp. Briefs,vol. 51, no. 1,pp. 2125, Jan. 2004.

[9] F. Sheikh, M. Miller, B. Richards, D. Markovic,and B. Nikolic,”A 1190 MSample/s 864 tap energy-efficient reconfigurable FIR filterfor multi-mode wirelesscommunication,” in Proc. IEEE Symp. VLSICircuits, Jun.2010, pp. 207208.

[10] S.-F. Hsiao, J.-H. Zhang Jian, and M.-C. Chen, ”Low-costFIR filter designs based on faithfully rounded truncatedmultipleconstant multiplication/accumulation,” IEEE Trans.Circuits Syst. II,Exp. Briefs, vol. 60, no. 5, pp. 287291, May2013.

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DESIGN AND IMPLEMENTATION OF A LOW POWER DIGITAL UP · growth in the digital electronics make possible many processes which used to be only theoretically possible. Di erent radio