DESIGN AND VERIFICATION OF AREA EFFICIENT PSK …

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DESIGN AND VERIFICATION OF AREA EFFICIENT PSK MODULATOR

FOR LONG DISTANCE COMMUNICATION

Santosh kumar Sahu*1

, Prof. Abhishek Singh*2

*1,2GGITS, Jabalpur, MP, India.

ABSTRACT

Channel coding and modulation schemes are important when digital communication required. Phase-shift

keying (PSK) is a digital modulation scheme that conveys data by changing, or modulating, the phase of a

reference signal (the carrier wave). Any digital modulation scheme uses a finite number of distinct signals to

represent digital data. PSK uses a finite number of phases; each assigned a unique pattern of binary digits.

Usually, each phase encodes an equal number of bits. But problems are that the user has to load large bit files

even for small changes in the waveforms. Proposed work is present an architecture for a 16-PSK which is

prototyped to handle real world signals up to 6dB QPSK and up to 6dB for 8-PSK using only 2 samples per

symbol. This design supports symbol rates between 32kS/s and 10MS/s. This infrastructure is scalable to any

kind of real time software radio development and aids rapid development on FPGA.

KEYWORDS: FPGA, QPSK, AM, PM, FDM,VHDL.

I. INTRODUCTION

In electronics and telecommunications, modulation is the process of varying one or more properties of a

periodic waveform, called the carrier signal, with a modulating signal which typically contains information to

be transmitted. Baseband signals generated by various information sources are not always suitable for direct

transmission over a given channel. These signals are generally further modified to facilitate transmission. This

conversion process is called modulation. In modulation process, the baseband signal is used to modify some

parameters of a high frequency carrier signal.

The aim of digital modulation is to transfer a digital bit stream over an analog band pass channel, digital

modulation technique is to be thought over by the designer which has an ability of exploiting the available

transmitted power and the bandwidth to its full extent [18, 19]. In order to achieve a discrete signal it is essential

to have the modulating signal of the form of a NRZ rectangular pulse thus yielding the modulated parameter as a

discrete signal switching or keying between two discrete values . However, ASK, FSK, and PSK with Nyquiste

pulse shaping at the base band form the basic technique of digital modulation, but other methods are also

possible with hybridization of two or more basic digital modulation schemes with or without pulse shaping.

Table1: Base papers concluded survey

Author Title Purpose Findings and Suggestion

Arun

Kumar

K A

A Low Power

Implementation of

PSK Modems in

FPGA with

Reconfigurable

Filter and Digital

NCO using PR for

SDR and CR

Applications

The objective of this work

is to make the modulation

and demodulation (PSK)

Schemes partially

reconfigurable. This work

involves the Design and

implementation of BPSK,

QPSK , 8-PSK and 16-

PSK modulation and

demodulation schemes in

FPGA.

The entire modem is implemented in this

device using the highly efficient DSP48

slices, Block RAMS and other dedicated

devices. The final implemented system is a

multi-rate waveform working at 92.16 MHz

and 46.08 MHz. Here power reduction is

mainly achieved by using pipeline technique

and implementing the design using block

RAMs which will not use any

programmable routing inside the core. Here

we can see the static and dynamic part of the

modulator and demodulator along with the

http://en.wikipedia.org/wiki/Electronics

http://en.wikipedia.org/wiki/Telecommunications

http://en.wikipedia.org/wiki/Waveform

http://en.wikipedia.org/wiki/Carrier_wave

http://en.wikipedia.org/wiki/Digital_data

http://en.wikipedia.org/wiki/Bandpass

http://en.wikipedia.org/wiki/Channel_(communications)




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chip scope pro for on chip debugging.

Satish

Sharma,

Sunil,

Vijay

kumar

Pujari,

FPGA

Implementation of

M-PSK modulators

for Satellite

Communication

This paper presents the

digital implementation

QPSK & 8-PSK

modulators for satellite

communication.

The modulators are realized using the

concept of Direct Digital Frequency

Synthesis (DDFS).The real time testing is

done on the Xilinx platform and the

performances of the systems are found well

within limits.

Vinay

Kumar

Velkuru

and

Abhay

Samant

A design for

software defined M-

PSK radio on FPGA

for low SNRs and

symbol rates up to

10MS/s

In this they evaluate its

effectiveness and

feasibility through

implementation with field

programmable gate array

(FPGA) and test bed

experiments with a sample

RF power amplifier (PA).

Trellis shaping has been examined from the

viewpoint of circuit complexity and a

shaping system with the moment method

which can be implemented with relatively

small circuit scale, has been implemented on

a FPGA board. The peak power reduction

capability of the proposed trellis shaping

and its effectiveness has been demonstrated

by observing RF waveforms and power

spectra through the linear power amplifier.

II. METHODOLOGY

Requirement of PSK is already been explained in chapter-1. Specification for proposed work is that designed is

a M-PSK modulator and demodulator where M can be 4, 8, or Max 16. Each sample is of 8 bit in length. So

total possible detectable phase change of design are (0, 22.5, 45, 67.5, 90, 112.5, 135, 157.5, 180, 202.5,

225,247.5, 270, 292.5, 315, 337.5, 360/0). In the process of literature survey (chapter-2) we come up with the

conclusion that all existing design are of digital Demodulator uses FIFO or memory element for receiving

varying speed data. As we come up with a new handshaking signals at the receiving end design Demodulator of

M-PSK with help Mealy type FSM. That reduced the area requirement of Demodulator part of M-PSK design.

We did not made any change in modulation section. Figure shown below is the signal are used for design entity

of each tr, rc, and top

Fig-1: Overall module of M-PSK design

In figur 2 below Module „clkcounter‟ is there for generating control signals and these control signals provides

proper synchronisation between other modules.

Module „tr‟ receives four bit input of digital signal which can be any one quantized level of digital input signal,

because a complete cycle of any signal can have 16 time intervals so it receives total 64 input bit and ones it

receives 64 bit it consider it as one cycle and pass these 64 bits to next module and starts receiving next inputs.

Single wire

Binary signal

The overall module of M-PSK design

Transmitter

Modulator

Receiver/

Demodulator 4 wire

digital

signal

4 wire

digital

signal




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Module „trm‟ gets 64 bit input which is a complete cycle of input it observe the patterns and recognise the phase

difference from the last received cycle as per that observation it generates a 8 bit encoded output signal which is

actually a patterns of phase difference in 8 bit parallel form of PSK.

Module „generator‟ gets 8 bit encoded input and it simply convert that 8 bit parallel form of PSK into serial

single line PSK output.

Fig-2: Transmitter Modulator design

We modified the receiver module and use FSM mealy type rather than FIFO or memory designed new

handshaking signals and test our design for 16 PSK.

Fig-3: Receiver Module bock representation

Fig-4: Proposed FSM

Idle

Dlow

Dhigh

Din=1

Din=0

Din=1

Din=0

rst=1

rst=1

Din=0

Din=1

Rst=1

tr

Clk-counter

trm

Generator 4 bit 64 bit

8 bit 1 bit PSK

output

FSM

Datagen

Signalgen

Clkctr

1 wire

input

4 wire

digital

output

4 wire

encode

wire

64 wires

of full

signal




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FSM: here FSM is been proposed and used for receiving one bit input data line, FSM encode the signals and

generates 4 bit data and it generates total 16 samples for each phase change one can say FSM output generation

rate is 16 time greater then input arriving of signal. The FSM is been used as a replacement of FIFO/Memory

element in receiver part of PSK demodulation it reduce the overall Area requirement of design.

Datagen is been used as a 4x64 encoded signals signalen is been used to produce final output from the 64 bit

encoded signal and clkctr is been used to provide various control signals for the each design module.

III. RESULTS

Fig 5:- Input Signal In Analog :MATLAB plots of input signal in 16 different phase in Analog form

Fig 6 :- Input Signal in Digital form: MATLAB plots of input signal in 16 different phase in Digital form:

Simulation on MATLAB is done because as we know FPGA is a digital device and it can have digital inputs

only which requires an ADC conversion, so we did the same with MATLAB tool.




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Table-2: Sampled digital Signal

00

/3600 22.50 450 67.50 900 112.50 1350 157.50 1800 202.50 2250 247.50 2700 292.50 315 0 337.50

0010 0001 0000 1111 1110 1101 1100 1101 1110 1111 0000 0001 0010 0011 0100 0011

0011 0010 0001 0000 1111 1110 1101 1100 1101 1110 1111 0000 0001 0010 0011 0100

0100 0011 0010 0001 0000 1111 1110 1101 1100 1101 1110 1111 0000 0001 0010 0011

0011 0100 0011 0010 0001 0000 1111 1110 1101 1100 1101 1110 1111 0000 0001 0010

0010 0011 0100 0011 0010 0001 0000 1111 1110 1101 1100 1101 1110 1111 0000 0001

0001 0010 0011 0100 0011 0010 0001 0000 1111 1110 1101 1100 1101 1110 1111 0000

0000 0001 0010 0011 0100 0011 0010 0001 0000 1111 1110 1101 1100 1101 1110 1111

1111 0000 0001 0010 0011 0100 0011 0010 0001 0000 1111 1110 1101 1100 1101 1110

1110 1111 0000 0001 0010 0011 0100 0011 0010 0001 0000 1111 1110 1101 1100 1101

1101 1110 1111 0000 0001 0010 0011 0100 0011 0010 0001 0000 1111 1110 1101 1100

1100 1101 1110 1111 0000 0001 0010 0011 0100 0011 0010 0001 0000 1111 1110 1101

1101 1100 1101 1110 1111 0000 0001 0010 0011 0100 0011 0010 0001 0000 0000 1110

1110 1101 1100 1101 1110 1111 0000 0001 0010 0011 0100 0011 0010 0001 0000 0000

1111 1110 1101 1100 1101 1110 1111 0000 0001 0010 0011 0100 0011 0010 0001 0000

0000 1111 1110 1101 1100 1101 1110 1111 0000 0001 0010 0011 0100 0011 0010 0001

0001 0000 1111 1110 1101 1100 1101 1110 1111 0000 0001 0010 0011 0100 0011 0010

Fig-7: Design summary of complete module




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Fig 8 : RTL Schematic of Complete Module

Fig 9 : Technological Schematic of Complete Module




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Fig-10: Simulation Results of Complete module




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Table-3: Simulation Results obtained

Logic Simulation Used Available Utilization

Number of Slices 274 4656 5%

Number of Slices Flip Flops 223 9312 2%

Number of 4 inputs LUTs 466 9312 5%

Number of Bonded IOBs 10 158 6%

Number of GCLKs 1 24 4%

Trans Delay - 4.927 ns

Table-4: Comparative Analysis of Demodulator

Base [1] Base[2] Proposed Receiver

module

Number of Slices 143 151 101

Number of Slices Flip Flops 438 - 82

Number of 4 inputs LUTs 76 - 175

Number of Bonded IOBs - - 7

Number of GCLKs 1 - 1

Logical Delay - - 4.927 ns

Max Frequency - 204 MHz 202.96 MHz

From table 4 it may be observe that proposed work is best among others works in terms of area utilization.

IV. CONCLUSION

Thesis work can be used for M-PSK and all results of proposed work is been compared with existing 16-PSK

modules. FSM based Demodulator is been proposed and a better results (area, frequency etc.) are been

observed. An efficient exploitation of the satellite capacity and reliable communication has always been key

factors in development of the satellite market. With the advancement in digital and signal processing

technology, now advance modulation based systems can be realized in better and fast manner. This work

presents the design and development of 16-PSK modulators. This concept is an advanced and extended part of

8-PSK modulators i.e. for high order modulation. The modulators are realized with different methods to get the

advantage in term of hardware and frequency of operation. Digital Implementation definitely has advantage over

analog in terms of performance. The developed modulators can cater the present and future requirement, as they

can support high bit rate also. The designs are well optimized at system level and finally coded in VHDL. The

real time testing is done on the Xilinx platform and the performance of the systems is found well within limits.

V. REFERENCES

[1] Kumar, Arun; “A Low Power Implementation of PSK Modems in FPGA with Reconfigurable Filter and

Digital NCO using PR for SDR and CR Applications”; 978-1-4673-2636-0/12/$31.00 ©2012 IEEE.




[807]

[2] Sharma, Satish; Pujari, Vijaykumar and Lakshminarsimhan, P., “FPGA Implementation of M-PSK

Modulators for Satellite Communication”, 978-0-7695-4201-0/10 © 2010 IEEE DOI

10.1109/ARTCom.2010.71.

[3] Velkuru, Vinay Kumar; Samant, Abhay, “A Design for Software Defined M-PSK Radio on FPGA for

Low SNRs and Symbol Rates upto 10MS/s”. 978-1-4577-0242-6/11. IEEE ICSIPA, 2011

[4] Kitagawa, Hiroyuki; Tanahashi, Makoto and Ochiai, Hideki, “FPGA Implementation of Trellis Shaping

to Control Peak Power for PSK Signals”, 978-1-4244-3435-0/09. 2009 IEEE ICC Proceedings.

[5] M. Mohamed Ismail, M.J.S Rangachar, Ch. D. V. Paradesi Rao, “An Area Efficient Mixed-Radix 4-2

Butterfly with Bit Reversal for OFDM Applications”, European Journal of Scientific Research, ISSN

1450-216X Vol.40 No.4 (2010), pp.515-521, © Euro Journals Publishing, Inc. 2010.

[6] G. Shafirulla, M. Subbareddy, “ Design of high speed FFT processor based on FPGA”, Vol.2, Issue 3,

May- June 2012, pp 657-660, International Journal of Modern Engineering Research (IJMER) , ISSN:

2249-6645.

[7] FPGA Implementation of BASK-BFSK- BPSK Digital Modulators C. Erdoğan, I. Myderrizi and S.

Minaei ECE Department, Dogus University Zeamet Sokak 21, Acıbadem – Kadıköy, 34722 Istanbul,

Turkey.

[8] S. O. Popescu, G. Budura, and A. S. Gontean, “Review of PSK and QAM – Digital Modulation

Techniques on FPGA,” Proceedings of the IEEE International Conference on Computational

Cybernetics and Technical Informatics (ICCCCONTI10), May 27-29, 2010, pp. 327-332.

[9] Proakis, J., Digital Communications, 2nd ed., New York: McGraw-Hill, 1989.

[10] Feher, K., Digital Communications: Satellite/Earth Station Engineering, Englewood Cliffs, New Jersey:

Prentice Hall, 1983.

[11] Pasupathy, S., „„Minimum shift keying: a spectrally efficient modulation,‟‟ IEEE Communications

Magazine, July 1979.

[12] Liu, C. L., and K. Feher, „„π/4-QPSKModems for Satellite Sound/Data Broadcast Systems,‟‟IEEE

Trans. Broadcasting, March 1991.

[13] Roden, M. Analog and Digital Communication, 3rd

ed , Englewood Cliffs, New Jersey , Prentice Hall

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[14] Haykin,S., Communication Systems, 3rd

ed., NewYork: John Wiley,1994.

[15] Haykin.S., Digital Communication , New York: John Wiley, 1988.

[16] Liu, C. L., and K. Feher, „„Bit error performance of π/4-DQPSK in a frequency-selective fast Rayleigh

fading channel,‟‟ IEEE Trans. Vehicular Technology, vol. 40, no. 3, August 1991.

[17] Sklar, B., Digital Communications: Fundamentals and Applications, Englewood Cliffs, New Jersey:

Prentice Hall, 1988.

[18] Smith, D. R., Digital Transmission Systems, 2nd ed., New York: Van Nostrand Reinhold, 1993.

[19] Ziemer, R. E., and R. L. Peterson, Introduction to Digital Communication, New York: Macmillan, 1992.

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DESIGN AND VERIFICATION OF AREA EFFICIENT PSK …