Isaac Zafrany

Custom Design Products Group

April 30, 2019

Design Data Management in Custom Compiler

using ClioSoft SOS

© 2019 Synopsys, Inc. 2

CONFIDENTIAL INFORMATIONThe information contained in this presentation is the confidential and proprietary

information of Synopsys. You are not permitted to disseminate or use any of

the information provided to you in this presentation outside of Synopsys

without prior written authorization.

IMPORTANT NOTICEIn the event information in this presentation reflects Synopsys’ future plans, such plans

are as of the date of this presentation and are subject to change. Synopsys is not

obligated to update this presentation or develop the products with the features and

functionality discussed in this presentation. Additionally, Synopsys’ services and products

may only be offered and purchased pursuant to an authorized quote and purchase order

or a mutually agreed upon written contract with Synopsys.

Synopsys Confidential Information

© 2019 Synopsys, Inc. 3Synopsys Confidential Information

Synopsys Custom Design Platform

Foundry Auto DRAMFLASHCPU GPU

Over 8 billion units shipped

Custom Compiler Environment

StarRC, IC Validator

Custom

Compiler

HSPICE

FineSim

CustomSim

DR

C F

usio

n

Extraction

Fusion

Designed using Synopsys custom design platform

Circuit simulation leadership

© 2019 Synopsys, Inc. 4Synopsys Confidential Information

Synopsys Custom Design Platform

Custom Compiler Environment

StarRC, IC Validator

Custom

Compiler

HSPICE

FineSim

CustomSim

DR

C F

usio

n

Extraction

Fusion

dd

28nm

53

22

16nm 10nm 7nm

45nm

Custom Digital Custom Analog

52

11

46

17

36

22

Synopsys IP completed in last 4Q using

Custom Platform

© 2019 Synopsys, Inc. 5Synopsys Confidential Information

DAC 2018 Custom Platform Luncheon

Recent Customer Experiences

Custom Compiler

sim. environment

2X faster analog

verification

FineSim

3D Flash memory

2X faster

simulation

HSPICE

ML applications

100X faster

finding reliability

issues

Custom Platform

PLL design

Productivity gain

across the flow

Custom Platform

MRAM memory

Silicon success

out of the box

flow

Custom Platform

ML processor

2X faster

7nm layout

© 2019 Synopsys, Inc. 6

Why a New Custom Solution?Impact of advanced nodes on custom design: 3X more effort

Variability and Reliability

Variability, EM/IR,

aging effects

Analog Design ClosureLayout Complexity

Increased design rule

complexity

Process Variability

0X

1X

2X

3X

4X

5X

40 28 14/16 10 7nm

Rules

Need to accelerate robust custom design

Design

Layout

More iterations due to

parasitics and reliability

© 2019 Synopsys, Inc. 7Synopsys Confidential Information

Synopsys Custom Design Platform

Layout productivity

Flexible, open environment

Visually

Assisted

Layout

Tighter design/layout collaboration

Faster custom design closure

Fusion

Architecture

Custom Compiler Environment

StarRC, IC Validator

Custom

Compiler

HSPICE

FineSim

CustomSim

DR

C F

usio

n

Extraction

Fusion

Monte Carlo and reliability analysis

Simulation, analytics, reporting

Reliability

Aware

Verification

© 2019 Synopsys, Inc. 10Synopsys Confidential Information

Custom Compiler Core Technologies

Layout productivity

Flexible, open environment

Visually

Assisted

Layout

Monte Carlo and reliability analysis

Simulation, analytics, reporting

Reliability

Aware

Verification

Tighter design/layout collaboration

Faster custom design closure

Fusion

Architecture

Schematics and HDL editing

Simulation setup and management

Multi-testbench, corners

Design Entry, Simulation and Analysis

Monte Carlo, reliability analysis

Charting, plotting and reporting

Synopsys and 3rd party simulation

© 2019 Synopsys, Inc. 11Synopsys Confidential Information

Custom Compiler Core Technologies

Layout productivity

Flexible, open environment

Visually

Assisted

Layout

Monte Carlo and reliability analysis

Simulation, analytics, reporting

Reliability

Aware

Verification

Tighter design/layout collaboration

Faster custom design closure

Fusion

Architecture

2X shorter

verification time

© 2019 Synopsys, Inc. 12

Comprehensive Variability and Reliability Analyses

Robust Design

Monte Carlo

EM / IR

Mixed-signal

Corners

Safe Operating

Area

Aging

Custom Compiler HSPICEHigh-Sigma Analysis

FineSimSmart Corner Simulation

CustomSimHigh Cap. Monte Carlo

Synopsys Confidential Information

© 2019 Synopsys, Inc. 13Synopsys Confidential Information

Custom Compiler Core Technologies

Layout productivity

Flexible, open environment

Visually

Assisted

Layout

Monte Carlo and reliability analysis

Simulation, analytics, reporting

Reliability

Aware

Verification

Tighter design/layout collaboration

Faster custom design closure

Fusion

Architecture

Create Template Use Template

© 2019 Synopsys, Inc. 14Synopsys Confidential Information

Custom Compiler Core Technologies

Layout productivity

Flexible, open environment

Visually

Assisted

Layout

Monte Carlo and reliability analysis

Simulation, analytics, reporting

Reliability

Aware

Verification

Tighter design/layout collaboration

Faster custom design closure

Fusion

Architecture

3X shorter

layout time

© 2019 Synopsys, Inc. 15Synopsys Confidential Information

Layout productivity

Flexible, open environment

Visually

Assisted

Layout

Monte Carlo and reliability analysis

Simulation, analytics, reporting

Reliability

Aware

Verification

Tighter design/layout collaboration

Faster custom design closure

Fusion

Architecture

Real-time

signoff-quality

feedback

Avoid

late-cycle

iterations

IC Validator

Custom

Compiler

shapes errors

Seamless

mixed-signal

implementation

Extraction

FusionDRC

FusionCustom Compiler – ICC II

Co-design

Custom Compiler Core Technologies

© 2019 Synopsys, Inc. 19Synopsys Confidential Information

• Unified and comprehensive design review system

for both schematic and layout

• Add comments, annotations and snapshots in design

• Enables effective collaboration between design

and layout teams

• Embedded tracking and approval flow

• Reviews Assistant are OA views stored in separate in

the in Library manager and works seamlessly with

design revision control systems

Design Review Assistant

© 2019 Synopsys, Inc. 20Synopsys Confidential Information

• Design Manager menu gives access to all

DM operations

• Manage hierarchy allows operations on a

hierarchical design

• Easy access cellview icons for Check-In,

Check-Out, Discard and Update

• Integration of common operations in the

right-mouse-button context menu

Interaction with ClioSoft ® SOS7™ platform

Tightly Integrated Data Management using ClioSoft ® SOS7™

© 2019 Synopsys, Inc. 21Synopsys Confidential Information

• All DM operations available in design editors

• Ability to update workarea

– Recreate a specific release configuration using

tags, snapshots and branches

– Reflect project-state at a specified time

• Version info

– Check current and older versions with the

description and the applied tags

– Controls for using a different revision

or revert back to a working version

Direct access from design editors and library manager

Tightly Integrated Data Management using ClioSoft ® SOS7™

© 2019 Synopsys, Inc. 22Synopsys Confidential Information

Accelerating Robust Custom Design

FinFET layout productivity from proven flows

Template-based design

Visually

Assisted

Layout

High speed circuit simulation

Monte Carlo and reliability analysis

Reliability

Aware

Verification

Tighter design/layout collaboration

Faster custom design closure

Fusion

Architecture

Custom Compiler Environment

StarRC, IC Validator

Custom

Compiler

HSPICE

FineSim

CustomSim

DR

C F

usio

n

Extraction

Fusion

Thank You