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Petrify: Method and Tool for Synthesis of Asynchronous Controllers and
Interfaces
Jordi Cortadella (UPC, Barcelona, Spain), MikeKishinevsky (Intel Strategic CAD Labs, Oregon), Alex Kondratyev (Berkeley CadenceResearch Labs, CA), Luciano Lavagno (Politecnico di Torino, Italy ),Alex Yakovlev (University of Newcastle, UK)
ASYNC2003 - Tutorial on Petrify Method and Tool 2
Outline
• Part 1: The Petrify Method– Overview of thePetrify synthesis flow
– Specification: Signal Tranistion Graphs
– Stategraph and next-state functions
– Stateencoding
– Implementation conditions
– Speed-independent circuits• Complex gates
• C-element architecture
ASYNC2003 - Tutorial on Petrify Method and Tool 3
Specification(STG)
State Graph
SG withCSC
Next-statefunctions
Decomposedfunctions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
Design flow
ASYNC2003 - Tutorial on Petrify Method and Tool 4
x
y
z
x+
x-
y+
y-
z+
z-
Signal Transition Graph (STG)
xy
z
Specification
ASYNC2003 - Tutorial on Petrify Method and Tool 5
x
y
z
x+
x-
y+
y-
z+
z-
Token flow
ASYNC2003 - Tutorial on Petrify Method and Tool 6
x+
x-
y+
y-
z+
z-
xyz000
x+
100y+z+
z+y+
101 110
111
x-
x-
001
011y+
z-
010
y-
State graph
ASYNC2003 - Tutorial on Petrify Method and Tool 7
x z x y= ⋅ +( )
y z x= +
z x y z= + ⋅
Next-state functionsxyz000
x+
100y+z+
z+y+
101 110
111
x-
x-
001
011y+
z-
010
y-
ASYNC2003 - Tutorial on Petrify Method and Tool 8
x
z
y
Gate netlist
x z x y= ⋅ +( )
y z x= +
z x y z= + ⋅
ASYNC2003 - Tutorial on Petrify Method and Tool 9
Specification(STG)
State Graph
SG withCSC
Next-statefunctions
Decomposedfunctions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
Design flow
ASYNC2003 - Tutorial on Petrify Method and Tool 10
VME bus
DeviceLDS
LDTACK
D
DSr
DSw
DTACK
VME BusController
DataTransceiver
BusDSr
LDS
LDTACK
D
DTACK
Read Cycle
ASYNC2003 - Tutorial on Petrify Method and Tool 11
STG for theREAD cycle
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
LDS
LDTACK
D
DSr
DTACK
VME BusController
ASYNC2003 - Tutorial on Petrify Method and Tool 12
Choice: Read and Writecycles
DSr+
LDS+
LDTACK+
D+
DTACK+
DSr-
D-
LDS-
LDTACK- DTACK-
DSw+
D+
LDS+
LDTACK+
D-
DTACK+
DSw-
LDS-
LDTACK-DTACK-
ASYNC2003 - Tutorial on Petrify Method and Tool 13
Choice: Read and Writecycles
DTACK-
DSr+
LDS+
LDTACK+
D+
DTACK+
DSr-
D-
LDS-
LDTACK-
DSw+
D+
LDS+
LDTACK+
D-
DTACK+
DSw-
LDS-
LDTACK-DTACK-
ASYNC2003 - Tutorial on Petrify Method and Tool 14
Choice: Read and Writecycles
DTACK-
DSr+
LDS+
LDTACK+
D+
DTACK+
DSr-
D-
LDS-
LDTACK-
DSw+
D+
LDS+
LDTACK+
D-
DTACK+
DSw-
LDS-
LDTACK-DTACK-
ASYNC2003 - Tutorial on Petrify Method and Tool 15
Circuit synthesis
• Goal:– Derive a hazard-free circuit
under a given delay model andmode of operation
ASYNC2003 - Tutorial on Petrify Method and Tool 16
Speed independence
• Delay model– Unbounded gate / environment delays
– Certain wire delays shorter than certain paths in the circuit
• Conditions for implementability:– Consistency
– Complete State Coding
– Persistency
ASYNC2003 - Tutorial on Petrify Method and Tool 17
Specification(STG)
State Graph
SG withCSC
Next-statefunctions
Decomposedfunctions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
Design flow
ASYNC2003 - Tutorial on Petrify Method and Tool 18
STG for theREAD cycle
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
LDS
LDTACK
D
DSr
DTACK
VME BusController
ASYNC2003 - Tutorial on Petrify Method and Tool 19
Binary encoding of signals
DSr+
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDS-LDS-LDS-
LDTACK- LDTACK- LDTACK-
D-
DSr-DTACK+
D+
LDTACK+
LDS+
ASYNC2003 - Tutorial on Petrify Method and Tool 20
Binary encoding of signals
DSr+
DSr+
DSr+
DTACK-
DTACK-
DTACK-
LDS-LDS-LDS-
LDTACK- LDTACK- LDTACK-
D-
DSr-DTACK+
D+
LDTACK+
LDS+
10000
10010
10110 01110
01100
0011010110
(DSr , DTACK , LDTACK , LDS , D)
ASYNC2003 - Tutorial on Petrify Method and Tool 21
QR (LDS+)
QR (LDS-)
Excitation / Quiescent Regions
ER (LDS+)
ER (LDS-)
LDS-LDS-
LDS+
LDS-
ASYNC2003 - Tutorial on Petrify Method and Tool 22
Next-state function
0 →→→→ 1
LDS-LDS-
LDS+
LDS-
1 →→→→ 0
0 →→→→ 0
1 →→→→ 1
1011010110
ASYNC2003 - Tutorial on Petrify Method and Tool 23
Karnaugh map for LDS
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
DTACKDSrD
LDTACK 00 01 11 10
00
01
11
10
LDS = 0 LDS = 1
0 1-0
0 0 0 0 0 0/1?
1
111
-
-
-
---
- - - -
-
- ---
- - -
ASYNC2003 - Tutorial on Petrify Method and Tool 24
Specification(STG)
State Graph
SG withCSC
Next-statefunctions
Decomposedfunctions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
Design flow
ASYNC2003 - Tutorial on Petrify Method and Tool 25
Concurrency reduction
LDS-LDS-
LDS+
LDS-
1011010110
DSr+
DSr+
DSr+
ASYNC2003 - Tutorial on Petrify Method and Tool 26
Concurrency reduction
LDS+ LDTACK+ D+ DTACK+ DSr- D-
DTACK-
LDS-LDTACK-
DSr+
ASYNC2003 - Tutorial on Petrify Method and Tool 27
Stateencoding conflicts
LDS-
LDTACK-
LDTACK+
LDS+
10110
10110
ASYNC2003 - Tutorial on Petrify Method and Tool 28
Signal Insertion
LDS-
LDTACK-
D-
DSr-
LDTACK+
LDS+
CSC-
CSC+
101101
101100
ASYNC2003 - Tutorial on Petrify Method and Tool 29
Specification(STG)
State Graph
SG withCSC
Next-statefunctions
Decomposedfunctions
Gate netlist
Reachability analysis
State encoding
Boolean minimization
Logic decomposition
Technology mapping
Design flow
ASYNC2003 - Tutorial on Petrify Method and Tool 30
Complex-gate implementation
)(csccsc
csc
csc
LDTACKDSr
LDTACKD
DDTACK
DLDS
+⋅=
⋅=
=
+=
ASYNC2003 - Tutorial on Petrify Method and Tool 31
Implementation conditions
• Consistency– Rising and falling transitions of each signal
alternate in any trace
• Complete statecoding (CSC)– Next-state functionscorrectly defined
• Persistency– No event can be disabled by another event
(unless they are both inputs)
ASYNC2003 - Tutorial on Petrify Method and Tool 32
Implementation conditions
• Consistency + CSC + persistency
• Thereexists a speed-independent circuitthat implements thebehavior of theSTG
(under theassumption that ay Boolean functioncan be implemented with onecomplex gate)
ASYNC2003 - Tutorial on Petrify Method and Tool 33
Persistency
100 000 001a- c+
b+ b+
a
cb
a
c
b
is thisa pulse ?
Speed independence� glitch-free output behavior under any delay
a+
b+
c+
d+
a-
b-
d-
a+
c-a-
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
abcd 00 01 11 10
00
01
11
10 1
1 1 11
10
0 000
ER(d+)
ER(d-)
abcd 00 01 11 10
00
01
11
10 1
1 1 11
10
0 000
caadd +=
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
Complex gate
ASYNC2003 - Tutorial on Petrify Method and Tool 37
Implementation with C elements
CR
S z
• • • → S+ → z+ → S- → R+ → z- → R- → • • •
• S(set) and R (reset) must be mutually exclusive
• Smust cover ER(z+) and must not intersect ER(z-) ∪ QR(z-)
• Rmust cover ER(z-) and must not intersect ER(z+) ∪ QR(z+)
abcd 00 01 11 10
00
01
11
10 1
1 1 11
10
0 000
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
CS
Rdc
ca
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
CS
Rdc
ca
but ...
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
CS
Rdc
ca
Assume that R=ac has an unbounded delay
Starting from state0000 (R=1 and S=0):
a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ;
R+ disabled (potential glitch)
abcd 00 01 11 10
00
01
11
10 1
1 1 11
10
0 000
0000
1000
1100
0100
0110
0111
1111
1011
0011 1001
0001
a+
b+
c+
a-
b-
c-
a+
c-
a-
a-
d-d+
CS
Rdc
cba
Monotonic covers ASYNC2003 - Tutorial on Petrify Method and Tool 42
C-based implementations
CS
Rdc
cbaC
d
ab
c
a
b
cd
weak
a
cd
generalized C elements (gC)
weak
ASYNC2003 - Tutorial on Petrify Method and Tool 43
Speed-independent implementations
• Implementation conditions– Consistency
– Complete statecoding
– Persistency
• Circuit architectures– Complex (hazard-free) gates
– C elements with monotonic covers
– ...
ASYNC2003 - Tutorial on Petrify Method and Tool 44
Synthesis exercise
y-
z- w-
y+ x+
z+
x-
w+
1011
0111
0011
1001
1000
1010
0001
0000 0101
0010 0100
0110
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
Derive circuits for signals x and z (complex gates and monotonic covers)
ASYNC2003 - Tutorial on Petrify Method and Tool 45
Synthesis exercise
1011
0111
0011
1001
1000
1010
0001
0000 0101
0010 0100
0110
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
wxyz 00 01 11 10
00
01
11
10
-
-
-
-
Signal x
1
0
1
1
1
1
1
0 0
0
0
0
ASYNC2003 - Tutorial on Petrify Method and Tool 46
Synthesis exercise
1011
0111
0011
1001
1000
1010
0001
0000 0101
0010 0100
0110
y-
y+
x-
x+w+
w-
z+
z-
w-
w-
z-
z-y+
y+
x+
x+
wxyz 00 01 11 10
00
01
11
10
-
-
-
-
Signal z
1
0 0
0
0
11 1
0
0 0
0
ASYNC2003 - Tutorial on Petrify Method and Tool 47
A simple filter: specification
y := 0;loop
x := READ (IN);WRITE (OUT, (x+y)/2);y := x;
end loop
RinAin
Aout Rout
IN
OUT
filter
ASYNC2003 - Tutorial on Petrify Method and Tool 48
A simple filter: block diagram
x y+
controlRinAin
RoutAout
Rx Ax Ry Ay Ra Aa
INOUT
• x and y are level-sensitive latches (transparent when R=1)• + is a bundled-data adder (matched delay between Ra and Aa)• Rin indicates the validity of IN• After Ain+ the environment is allowed to change IN• (Rout,Aout) control a level-sensitive latch at the output
ASYNC2003 - Tutorial on Petrify Method and Tool 49
A simple filter: control spec.
x y+
controlRinAin
RoutAout
Rx Ax Ry Ay Ra Aa
INOUT
Rin+
Ain+
Rin-
Ain-
Rx+
Ax+
Rx-
Ax-
Ry+
Ay+
Ry-
Ay-
Ra+
Aa+Ra-
Aa-
Rout+
Aout+
Rout-
Aout-
ASYNC2003 - Tutorial on Petrify Method and Tool 50
A simple filter: control impl.
Rin+
Ain+
Rin-
Ain-
Rx+
Ax+
Rx-
Ax-
Ry+
Ay+
Ry-
Ay-
Ra+
Aa+
Ra-
Aa-
Rout+
Aout+
Rout-
Aout-
C
Rin
Ain
Rx Ax RyAy AaRa
Aout
Rout
ASYNC2003 - Tutorial on Petrify Method and Tool 51
Control: observable behavior
Rx+
Rin+
Ax+ Ra+ Aa+ Rout+ Aout+ z+ Rout- Aout- Ry+
Ry- Ay+Rx-Ax-Ay-
Ain-
Ain+
Ra-
Rin-
Aa-z-
C
Rin
Ain
Rx Ax RyAy AaRa
Aout
Rout
z
ASYNC2003 - Tutorial on Petrify Method and Tool 52
Following slides borrowed from Ran Ginosar, Technion (VLSI Architectures course) with thanks
ASYNC2003 - Tutorial on Petrify Method and Tool 53
Generalized C Element
ab C
+
-cz set(z) = ab
reset(z) = b'c'
z
reset
setb
a
c
b
z
a
b
c
z
reset
setb
a
c
b
a
b
cset
reset
DYNAMIC (Pseudostatic) STATIC
z
b c
b a
From Ran Ginosar’s course
ASYNC2003 - Tutorial on Petrify Method and Tool 54
STG Rules
• Any STG:– Input free-choice—Only inputs may control the choice)– Bounded—Maximum k (given bound) token per place– Liveness—every signal transition can be activated
• STG for Speed Independent circuits:– Consistent state assignment—Signals strictly alternate
between + and –– Persistency—Excited non-input signals must fire,
namely they cannot be disabled by another transition
• Synthesizable STG:– Complete state coding—Different markings must
represent different states
ASYNC2003 - Tutorial on Petrify Method and Tool 55
• We use the following circuit to explain STG rules:
req
ack
REQ
ACK
ASYNC2003 - Tutorial on Petrify Method and Tool 56
1-Bounded (Safety)
• STG is safe if no place or arc can ever contain more than one token
• Often caused by one-sided dependency
STG is not safe: If left cycle goes fast and right cycle lags, then arc ack+ → REQ+ accumulates tokens. (REQ+ depends on both ack+ and ACK- )
Possible solution: stop left cycle by right cycle
REQ+ ACK+
REQ-ACK-
req+ ack+
req-ack-
ASYNC2003 - Tutorial on Petrify Method and Tool 57
Liveness
• STG is live if from every reachable marking, every transition can eventually be fired
• The STG is not live: • Transitions reset, reset_ok cannot be repeated.
• But non-liveness is useful for initialization
reset_ok-reset- req+ ack+
req-ack-
ASYNC2003 - Tutorial on Petrify Method and Tool 58
Consistent state assignment
• The following subgraph of STG makes no sense:
a+ a+
a- a-
ASYNC2003 - Tutorial on Petrify Method and Tool 59
Persistency
• STG is persistent if for all non-input transitions once enabled the transition cannot be disabled by another transitions. Non-persistency may be caused by arbitration or dynamic conflict relations – STG must have places
STG is not persistent: there is a place between req+ and ack+ in which a token is needed in order to fire REQ+ . So there is some sort ofnondeterminism – either REQ+ manages to fire before ack+ or not
Possible solution: introduce proper dependence of the left cylceon the right one (e.g., an arc from req+ to REQ+, and from REQ+ to ack+)
REQ+ ACK+
REQ-ACK-
req+
ack+req-
ack-
60
Complete State Coding
• STG has a complete state coding if no two different markings have identical values for all signals.
REQ+ ACK+
REQ-ACK-
ack- req+
ack+req-
1000 1010req,ack,REQ,ACK:
1011
100110001100
0100
0000
00
01
00 01 11 10cd\ab
11
10
Disaster!
ASYNC2003 - Tutorial on Petrify Method and Tool 61
Complete State Coding
• Possible solution: Add an internal state variable
x- x+
req,ack,REQ,ACK,x:
REQ+ ACK+
REQ-ACK-
ack- req+
ack+req-
10000 10100
1000111001
ASYNC2003 - Tutorial on Petrify Method and Tool 62
A faster STG?
• Does it need an extra variable?
ack-
req+
ack+
req-
ACK-
REQ+
ACK+
REQ-
ASYNC2003 - Tutorial on Petrify Method and Tool 63
STG specification in .astg format. model si mpl e_buf f er. i nput s r A. out put s a R. gr aph# l ef t handshake ( r , a)r + a+a+ r -r - a-a- r +# r i ght handshake ( R, A)R+ A+A+ R-R- A-A- R+# i nt er act i on bet ween handshakesr + R+A+ a-. mar ki ng{ <a- , r +><A- , R+>}. end
ASYNC2003 - Tutorial on Petrify Method and Tool 64
Drawn by draw_astg
65
The SGreq,ack,REQ,ACK:
0000
r+1000a+ R+
1100 1010r-
0100
R+
1110a+ A+
1011A+
1111a+r-
0110
R+a-
a- A+
0111r-
0011a-
R-
1001R-
1101a+
R-
0101r-
0001a-R-
A-
1000A-
1100a+
A-
0100r-
a-A-1011
r+
1001r+R-
A-1111
a+
R-
1101a+
A-0111
r-
R-
0101r-
A-
a-
a-
66
The SGreq,ack,REQ,ACK:
0000
r+1000a+ R+
1100 1010r-
0100
R+
1110a+ A+
1011A+
1111a+r-
0110
R+a-
a- A+
0111r-
0011a-
R-
1001R-
1101a+
R-
0101r-
0001a-R-
A-
1000A-
1100a+
A-
0100r-
a-A-1011
r+
1001r+R-
A-1111
a+
R-
1101a+
A-0111
r-
R-
0101r-
A-
a-
a-
R+
R+
R+
CSC-conflict states are highlighted
ASYNC2003 - Tutorial on Petrify Method and Tool 67
Drawn by write_sg & draw_astg
ASYNC2003 - Tutorial on Petrify Method and Tool 68
Extra states inserted by petrify
ASYNC2003 - Tutorial on Petrify Method and Tool 69
Rearranged STG
ack-
req+
ack+
req-
c1-
c1+
c0-
ACK-
REQ+
ACK+
REQ-
c2-
c2+
c0+
Initial Internal State: c0=c1=c2=1ASYNC2003 - Tutorial on Petrify Method and Tool 70
The new State Graph…
ASYNC2003 - Tutorial on Petrify Method and Tool 71
The Synthesized Complex Gates Circuit
I NORDER = r A a R csc0 csc1 csc2;
OUTORDER = [ a] [ R] [ csc0] [ csc1] [ csc2] ;
[ a] = a ( csc2 + csc0) + csc1' ;
[ R] = csc2 ( csc0 ( a + r ) + R) ;
[ csc0] = csc0 ( csc1' + a' ) + R' csc2;
[ csc1] = r ' ( csc0 + csc1) ;
[ csc2] = A' ( csc0' ( csc1' + a' ) + csc2) ;
ASYNC2003 - Tutorial on Petrify Method and Tool 72
Technology MappingI NORDER = r A a R csc0 csc1 csc2;OUTORDER = [ a] [ R] [ csc0] [ csc1] [ csc2] ;
[ 0] = R' ; # gat e i nv: combi nat i onal[ 1] = [ 0] ' A' + csc2' ; # gat e oai 12: combi nat i onal[ a] = a csc0' + [ 1] ; # gat e sr _nor : asynch
[ 3] = csc1' ; # gat e i nv: combi nat i onal[ 4] = csc0' csc2' [ 3] ' ; # gat e nor 3: combi nat i onal[ 5] = [ 4] ' ( csc1' + R' ) ; # gat e aoi 12: combi nat i onal
[ R] = [ 5] ' ; # gat e i nv: combi nat i onal[ 7] = ( csc2' + a' ) ( csc0' + A' ) ; # gat e aoi 22: combi nat i onal[ 8] = csc0' ; # gat e i nv: combi nat i onal[ csc0] = [ 8] ' csc1' + [ 7] ' ; # gat e oai 12: combi nat i onal[ csc1] = A' ( csc0 + csc1) ; # gat e r s_nor : asynch
[ 11] = R' ; # gat e i nv: combi nat i onal
[ 12] = csc0' ( [ 11] ' + csc1' ) ; # gat e aoi 12: combi nat i onal[ csc2] = [ 12] ( r ' + csc2) + r ' csc2; # gat e c_el ement 1: asynch
ASYNC2003 - Tutorial on Petrify Method and Tool 73
The Synthesized Gen-C CircuitI NORDER = r A a R csc0 csc1 csc2;
OUTORDER = [ a] [ R] [ csc0] [ csc1] [ csc2] ;
[ 0] = csc0' csc1 ( R' + A) ;
[ 1] = csc0 csc2 ( a + r ) ;
[ 2] = csc2' A;
[ R] = R [ 2] ' + [ 1] ; # mappabl e ont o gC
[ 4] = a csc1 csc2' ;
[ csc0] = csc0 [ 4] ' + csc2; # mappabl e ont o gC
[ 6] = r ' csc0;
[ csc1] = csc1 r ' + [ 6] ; # mappabl e ont o gC
[ 8] = A' csc0' ( csc1' + a' ) ;
[ csc2] = csc2 R' + [ 8] ; # mappabl e ont o gC
[ a] = a [ 0] ' + csc1' ; # mappabl e ont o gC
ASYNC2003 - Tutorial on Petrify Method and Tool 74
Petrify Environment
STG
EQNdraw_astg
ps
write_sg
SG
libpetrify
ASYNC2003 - Tutorial on Petrify Method and Tool 75
Petrify
• Unix (Linux) command line tool• pet r i f y –h for help (flags etc.)• pet r i f y –cg for complex gates• pet r i f y –gc for generalized C-elements• pet r i f y –t m for tech mapping• dr aw_ast g to draw• wr i t e_sg to create state graphs• Documented on line, including tutorial
ASYNC2003 - Tutorial on Petrify Method and Tool 76
References
• See the attached Practical Exercise manual for various design examples using Petrify commands
• Additional references:– Petrify and all documentation can be downloaded from:
http://www.lsi.upc.es/~jordic/petrify/petrify.html
– J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces, Springer, Berlin, 2002, ISBN3-540-43152-7