Upload
anjugadu
View
13
Download
0
Tags:
Embed Size (px)
DESCRIPTION
Design for Test
Citation preview
5/26/2018 Design for Test
1/84
Mani Srivastava
UCLA - EE Department
Room: 6731-H Boelter Hall
Email: [email protected]
Tel: 310-267-2098
WWW: http://www.ee.ucla.edu/~mbs
Copyright 2004 Mani Srivastava
Design for TestEE116B (Winter 2004): Lecture # 5
5/26/2018 Design for Test
2/84
2Copyright 2004 Mani Srivastava
VLSI Realization Process
Determine requirementsWrite specificationsDesign synthesis and Verification
FabricationManufacturing test
Chips to customer
ustomers need
Test development
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
5/26/2018 Design for Test
3/84
3Copyright 2004 Mani Srivastava
Definitions
Design synthesis: Given an I/O function, developa procedure to manufacture a device using
known materials and processes. Verification: Predictive analysis to ensure that
the synthesized design, when manufactured, willperform the given I/O function.
Test: A manufacturing step that ensures that thephysical device, manufactured from thesynthesized design, has no manufacturingdefect.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
5/26/2018 Design for Test
4/84
4Copyright 2004 Mani Srivastava
Validation and Test of
Manufactured Circuits Goals of Design-for-Test (DFT)
make testing of manufactured part swift &comprehensive
DFT mantra
provide controllability and observability
Components of DFT strategy provide circuitry to enable test
provide test patterns that guarantee reasonablecoverage
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
5/26/2018 Design for Test
5/84
5Copyright 2004 Mani Srivastava
Test Classification
Diagnostic test
used in chip/board debugging
defect localization
Go/no-go or production test
used to determine whether a chip is functional
simpler than diagnostic test; must be simple & swift
Parametric test (static/dc and dynamic/ac tests)
x e[v,i] versus x e[0,1]
check parameters such as NM, Vt, tp, T[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
5/26/2018 Design for Test
6/84
6Copyright 2004 Mani Srivastava
Verification vs. Test
Verifies correctness of design.
Performed by simulation,
hardware emulation, or formalmethods.
Performed once prior tomanufacturing.
Responsible for quality of
design.
Verifies correctness ofmanufactured hardware.
Two-part process:
1. Test generation:software process executedonce during design
2. Test application:electrical tests applied to
hardware Test application performed on
every manufactured device.
Responsible for quality ofdevices.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
5/26/2018 Design for Test
7/84
7Copyright 2004 Mani Srivastava
Why such a big deal?
High speed testers are astronomically costly!
Reducing test time can help increase throughputof tester
impacts testing cost
Testing must be considered from early phases
of the design process
5/26/2018 Design for Test
8/84
8Copyright 2004 Mani Srivastava
Costs of Testing
Design for testability (DFT)
Chip area overhead and yield reduction
Performance overhead
Software processes of test
Test generation and fault simulation
Test programming and debugging Manufacturing test
Automatic test equipment (ATE) capital cost
Test center operational cost[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
5/26/2018 Design for Test
9/84
9Copyright 2004 Mani Srivastava
Design for Testability (DFT)DFT refers to hardware design styles or addedhardware that reduces test generation complexityMotivation: Test generation complexity increasesexponentially with the size of the circuit.
Logicblock A Logicblock BI PO
Testinput
Testoutput
Int.bus
Example: Test hardware applies tests to blocks Aand B and to internal bus; avoids test generationfor combined A and B blocks.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
5/26/2018 Design for Test
10/84
10Copyright 2004 Mani Srivastava
Present and Future
Transistors/sq. cm 4 - 10M 18 - 39MPin count 100 - 900 160 - 1475Clock rate (MHz) 200 - 730 530 - 1100Power (Watts) 1.2 - 61 2 - 96
Feature size (micron) 0.25 - 0.15 0.13 - 0.101997 -2001 2003 - 2006
* SIA Roadmap, IEEE Spectrum, July 1999[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
5/26/2018 Design for Test
11/84
11Copyright 2004 Mani Srivastava
Cost of Manufacturing Testing in
2000AD 0.5-1.0GHz, analog instruments,1,024 digital pins: ATE
purchase price
= $1.2M + 1,024 x $3,000 = $4.272M
Running cost (five-year linear depreciation)
= Depreciation + Maintenance + Operation
= $0.854M + $0.085M + $0.5M
= $1.439M/year
Test cost (24 hour ATE operation)
= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
5/26/2018 Design for Test
12/84
12Copyright 2004 Mani Srivastava
Roles of Testing
Detection: Determination whether or not the deviceunder test (DUT) has some fault.
Diagnosis: Identification of a specific fault that is presenton DUT.
Device characterization: Determination and correction oferrors in design and/or test procedure.
Failure mode analysis (FMA): Determination ofmanufacturing process errors that may have causeddefects on the DUT.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
C i ht 2004 M i S i t
5/26/2018 Design for Test
13/84
13Copyright 2004 Mani Srivastava
Design for Testability
Mstate regs
inputs Koutputs
KoutputsNinputs
Combinational
Logic
Module
Combinational
Logic
Module
(a) Combinational function (b) Sequential engine
2Npatterns 2N+Mpatterns
Exhaustive test is impossible or unpractical
(consider a processor with N=64, M=50 at 1 sec/pattern)[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
C i ht 2004 M i S i t
5/26/2018 Design for Test
14/84
14Copyright 2004 Mani Srivastava
Testing Approach
Exhaustive testing has redundancy same fault covered by many input patterns
only one needed, other are superfluous
Cost of detecting all patterns may not be worth it typical test procedures attempt 95-99% coverage
C i ht 2004 M i S i t
5/26/2018 Design for Test
15/84
15Copyright 2004 Mani Srivastava
Ideal vs. Real Tests
Ideal tests detect all defectsproduced in the manufacturing
process. Ideal tests pass all functionally
good devices.
Very large numbers andvarieties of possible defects
need to be tested. Difficult to generate tests for
some real defects. Defect-oriented testing is an open
problem.
Based on analyzable faultmodels, which may not map onreal defects.
Incomplete coverage ofmodeled faults due to highcomplexity.
Some good chips are rejected.The fraction (or percentage) of
such chips is called the yieldloss.
Some bad chips pass tests.The fraction (or percentage) ofbad chips among all passingchips is called the defect level.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
16/84
16Copyright 2004 Mani Srivastava
Testing as Filter Process
Fabricatedchips
Good chips
Defective chips
Prob good) = y
Prob bad) = 1- y
Prob pass test) = high
Prob fail test) = high
Mostlygoodchips
Mostlybadchips
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
17/84
17Copyright 2004 Mani Srivastava
A Modern VLSI Device
System-on-a-chip (SOC)
DSPcore RAMROMInter-facelogic
Mixed-signalCodec
DataterminalTransmissionmedium
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
18/84
18Copyright 2004 Mani Srivastava
Testing Principle
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
19/84
19Copyright 2004 Mani Srivastava
Problem: Controllability &
Observability Combinational circuits
controllable and observable
relatively easy to determine test patterns
Sequential circuits: have state!
turn into combination circuits
or, use self-test Memory: requires complex patterns
use self-test
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
20Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
20/84
20Copyright 2004 Mani Srivastava
Test Approaches
Three approaches
Ad-hoc testing
Scan-based testing
Self-test
Problem is getting harder
increasing complexity and heterogeneouscombination of modules in systems-on-a-chip
advanced packaging and assembly techniquesextend problem to the board level
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
21Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
21/84
21Copyright 2004 Mani Srivastava
Generating and Validating
Test-Vectors Automatic test-pattern generation (ATPG)
for given fault, determine excitation vector (called testvector) that will propagate error to primary(observable) output
majority of available tools: combinational n/w only
sequential ATPG available from academic research
Fault simulation determines test coverageof proposed test-vector set
simulates correct network in parallel with faulty networks
Both require adequate models of faults in CMOS[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
22Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
22/84
22Copyright 2004 Mani Srivastava
Fault Modeling
Why model faults?
Some real defects in VLSI and PCB
Common fault models
Stuck-at faults Single stuck-at faults
Fault equivalence Fault dominance and checkpoint theorem
Classes of stuck-at faults and multiple faults
Transistor faults
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
23Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
23/84
23py g
Why Model Faults?
I/O function tests inadequate for
manufacturing (functionality versus
component and interconnect testing)
Real defects (often mechanical) too
numerous and often not analyzable
A fault model identifies targets for testing A fault model makes analysis possible
Effectiveness measurable by experiments
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
24Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
24/84
24py g
Some Real Defects in Chips Processing defects
Missing contact windows Parasitic transistors Oxide breakdown . . .
Material defects
Bulk defects (cracks, crystal imperfections) surface impurities (ion migration) . . .
Time-dependent failures Dielectric breakdown Electromigration
. . . Packaging failures
Contact degradation Seal leaks . . .
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation -
Semiconductor Devices and Circuits,Wiley, 1981.[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
25Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
25/84
25py g
Observed PCB DefectsDefect classes
Shorts
Opens
Missing componentsWrong components
Reversed components
Bent leads
Analog specifications
Digital logic
Performance (timing)
Occurrence frequency (%)
51
1
613
6
8
5
5
5
Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
26Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
26/84
26
Common Fault Models
Single stuck-at faults
Transistor open and short faults Memory faults
PLA faults (stuck-at, cross-point, bridging)
Functional faults (processors)
Delay faults (transition, path)
Analog faults
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
27Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
27/84
27
Fault Models
0
1
sa0
sa1
(output)
(input)
Most Popular - Stuck - at model
x1
x2 x3
Z
, : x1 sa1: x1 sa0 or
x2 sa0
: Z sa1
Covers almost all (other)occurring faults, such asopens and shorts.
[Adapted from
http://infopad.eecs.berkeley.edu/~icdes
ign/. Copyright 1996 UCB]
28Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
28/84
28
Single Stuck-at Fault
Three properties define a single stuck-at fault Only one line is faulty
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate
Example: XOR circuit has 12 fault sites ( ) and 24 singlestuck-at faults
a
b
c
d
e
f
1
0
g h
i1
s-a-0
j
k
z
0(1)1(0)
1
Test vector for h s-a-0 fault
Good circuit value
Faulty circuit value
[Adapted from VLSI Testing Course byBushnell/Agrawal at Rutgers]
29Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
29/84
29
Fault Equivalence
Number of fault sites in a Boolean gate circuit = #PI +#gates + #(fanout branches).
Fault equivalence: Two faults f1 and f2 are equivalent ifall tests that detect f1 also detect f2.
If faults f1 and f2 are equivalent then the correspondingfaulty functions are identical.
Fault collapsing: All single faults of a logic circuits can bedivided into disjoint equivalence subsets, where all faultsin a subset are mutually equivalent. A collapsed fault setcontains one fault from each equivalence subset.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
30Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
30/84
30
Equivalence Rules
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0
sa1
sa0sa1
sa0
sa0sa1
sa1
sa0
sa0
sa0sa1
sa1
sa1
AND
NAND
OR
NOR
WIRE
NOT
FANOUT[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
31Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
31/84
31
Equivalence Example
sa0 sa1
sa0sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0sa1
sa0sa1
sa0 sa1
sa0 sa1
sa0sa1
sa0 sa1
sa0sa1
sa0 sa1
sa0 sa1
Faults in red
removed by
equivalence
collapsing
20Collapse ratio = ----- = 0.625
32[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
32Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
32/84
3
Fault Dominance
If all tests of some fault F1 detect another fault F2, thenF2 is said to dominate F1.
Dominance fault collapsing: If fault F2 dominates F1,then F2 is removed from the fault list.
When dominance fault collapsing is used, it is sufficientto consider only the input faults of Boolean gates. Seethe next example.
In a tree circuit (without fanouts) PI faults form adominance collapsed fault set.
If two faults dominate each other then they areequivalent.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
33Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
33/84
Dominance Example
s-a-1F1
s-a-1F2 001
110 010
000101
100
011
All tests of F2
Only test of F1s-a-1
s-a-1
s-a-1
s-a-0
A dominance collapsed fault set
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
34Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
34/84
Checkpoints
Primary inputs and fanout branches of a combinationalcircuit are called checkpoints.
Checkpoint theorem: A test set that detects all single
(multiple) stuck-at faults on all checkpoints of acombinational circuit, also detects all single (multiple)stuck-at faults in that circuit.
Total fault sites = 16
Checkpoints ( ) = 10
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
35Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
35/84
Classes of Stuck-at Faults
Following classes of single stuck-at faults are identifiedby fault simulators:
Potentially-detectable fault -- Test produces an unknown (X)state at PO; detection is probabilistic, usually with 50%probability.
Initialization fault -- Fault prevents initialization of the faultycircuit; can be detected as a potentially-detectable fault.
Hyperactive fault -- Fault induces much internal signal activitywithout reaching PO.
Redundant fault -- No test exists for the fault.
Untestable fault -- Test generator is unable to find a test.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
36Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
36/84
Multiple Stuck-at Faults
A multiple stuck-at fault means that any set oflines is stuck-at some combination of (0,1)
values. The total number of single and multiple stuck-at
faults in a circuit with k single fault sites is 3k-1.
A single fault test can fail to detect the targetfault if another fault is also present, however,such masking of one fault by another is rare.
Statistically, single fault tests cover a very largenumber of multiple faults.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
37Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
37/84
Transistor (Switch) Faults
MOS transistor is considered an ideal switchand two types of faults are modeled:
Stuck-open -- a single transistor is permanentlystuck in the open state.
Stuck-short -- a single transistor is permanentlyshorted irrespective of its gate voltage.
Detection of a stuck-open fault requires twovectors.
Detection of a stuck-short fault requires themeasurement of quiescent current (IDDQ).
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
38Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
38/84
Problem with stuck-at model:
CMOS open faultx1 x2
x1
x2
Z
Sequential effect
Needs two vectors to ensure detection!
Other options: use stuck-open or stuck-short modelsThis requires fault-simulation and analysis at the switch ortransistor level - Very expensive!
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
39Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
39/84
Another Stuck-Open Examples
Two-vector s-op test
can be constructed byordering two s-at testsA
B
VDD
C
pMOS
FETs
nMOS
FETs
Stuck-
open
1
0
0
0
0 1(Z)
Good circuit states
Faulty circuit states
Vector 1: test for As-a-0(Initialization vector)
Vector 2 (test for As-a-1)
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
40Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
40/84
Problem with stuck-at model:
CMOS short fault0
0
0
1
C
A B
D
A
B
C
D
Causes short circuit between
Vdd and GND for A=C=0, B=1
Possible approach:Supply Current Measurement (IDDQ)but: not applicable for gigascale
integration
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
41Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
41/84
Another Stuck-Short Example
A
B
VDD
C
pMOS
FETs
nMOS
FETs
Stuck-
short1
0
0 (X)
Good circuit state
Faulty circuit state
Test vector for As-a-0
IDDQpath in
faulty circuit
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
42Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
42/84
Summary of Fault Models
Fault models are analyzable approximations of defectsand are essential for a test methodology.
For digital logic single stuck-at fault model offers bestadvantage of tools and experience.
Many other faults (bridging, stuck-open and multiplestuck-at) are largely covered by stuck-at fault tests.
Stuck-short and delay faults and technology-dependentfaults require special tests.
Memory and analog circuits need other specialized faultmodels and tests.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
43Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
43/84
Automatic Test Pattern
Generation Determine a minimum set of excitation vectors that cover
a significant portion of the fault set as defined by theadopted fault model
An approach: start form random set of patterns use fault simulation to determine how many potential faults
are detected
iteratively add or remove extra vectors
Fault simulation determines fault coverage correct circuit simulated in parallel with a number of faulty
ones, each with a single fault results compared
44Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
44/84
Exhaustive Test Pattern
Generation For n-input circuit, generate all 2ninput patterns
Infeasible, unless circuit is partitioned into conesof logic, with 15inputs
Perform exhaustive ATPG for each cone
Misses faults that require specific activation
patterns for multiple cones to be tested
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
45Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
45/84
Random-Pattern Generation
Flow chart formethod
Use to get tests for60-80% of faults,then switch to D-
algorithm or otherATPG for rest
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
46 Copyright 2004Mani Srivastava
5/26/2018 Design for Test
46/84
Fault Simulation
Fault simulation Problem: Given A circuit
A sequence of test vectors A fault model
Determine Fault coverage - fraction (or percentage) of modeled faults
detected by test vectors
Set of undetected faults Motivation
Determine test quality and in turn product quality
Find undetected fault targets to improve tests
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
47 Copyright 2004Mani Srivastava
5/26/2018 Design for Test
47/84
Fault Simulator in a VLSI DesignProcess
Verified design
netlist
Verification
input stimuli
Fault simulator Test vectors
Modeled
fault list
Test
generator
Test
compactor
Faultcoverage
?
Remove
tested faultsDelete
vectors
Add vectors
Low
Adequate
Stop[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
48 Copyright 2004Mani Srivastava
5/26/2018 Design for Test
48/84
Fault Simulation Algorithms
Serial
Parallel
Concurrent
Deductive
Differential
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
49 Copyright 2004Mani Srivastava
5/26/2018 Design for Test
49/84
Serial Algorithm
Algorithm: Simulate fault-free circuit and saveresponses. Repeat following steps for each fault in the
fault list: Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing
responses with saved responses
If response differs, report fault detection and suspendsimulation of remaining vectors
Advantages: Easy to implement; needs only a true-value simulator, less
memory
Most faults, including analog faults, can be simulated
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
50 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
50/84
Serial Algorithm (Cont.)
Disadvantage: Much repeated computation;CPU time prohibitive for VLSI circuits
Alternative: Simulate many faults together
Test vectors Fault-free circuit
Circuit with fault f1
Circuit with fault f2
Circuit with fault fn
Comparator f1 detected?
Comparator f2 detected?
Comparator fn detected?[Adapted from VLSI
Testing Course by
Bushnell/Agrawal atRutgers]
51 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
51/84
Parallel Fault Simulation
Best with two-states (0,1)
Exploits inherent bit-parallelism of logic operations on
computer words Storage: one word per line for two-state simulation
Multi-pass simulation: Each pass simulates w-1 newfaults, where w is the machine word length
Speed up over serial method ~ w-1
Not suitable for circuits with timing-critical and non-Boolean logic
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
52 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
52/84
Parallel Fault Sim. Example
ab c
d
e
f
g
1 1 1
1 1 1 1 0 11 0 1
0 0 0
1 0 1
s-a-1
s-a-0
0 0 1
c s-a-0 detected
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
55 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
53/84
Concurrent Fault Simulation
Event-driven simulation of fault-free circuit and onlythose parts of the faulty circuit that differ in signal states
from the fault-free circuit. A list per gate containing copies of the gate from all
faulty circuits in which this gate differs. List elementcontains fault ID, gate input and output values andinternal states, if any.
All events of fault-free and all faulty circuits are implicitlysimulated.
Faults can be simulated in any modeling style or detailsupported in true-value simulation (offers most flexibility.)
Faster than other methods, but uses most memory.56 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
54/84
Conc. Fault Sim. Example
ab c
d
e
f
g
1
1
1
0
1
1
11
1
01
1 0
0
10
1
00
1
00
1
10
1
00
1
11
1
11
0
00
0
11
0
00
0
00
a0 b0 c0 e0
a0 b0
b0
c0 e0
d0d0 g0 f1
f1
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
57 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
55/84
Fault Sampling
A randomly selected subset (sample) of faults issimulated.
Measured coverage in the sample is used toestimate fault coverage in the entire circuit.
Advantage: Saving in computing resources
(CPU time and memory.) Disadvantage: Limited data on undetected
faults.
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
58 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
56/84
Motivation for Sampling
Complexity of fault simulation depends on:
Number of gates
Number of faults
Number of vectors
Complexity of fault simulation with fault sampling
depends on: Number of gates
Number of vectors
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
59 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
57/84
Functional vs. Structural ATPG
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
60 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
58/84
Carry Circuit
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
61 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
59/84
Functional vs. Structural(Continued)
Functional ATPGgenerate complete set of tests for circuit input-output combinations
129inputs, 65outputs:
2129= 680,564,733,841,876,926,926,749,
214,863,536,422,912patterns
Using 1 GHz ATE, would take 2.15 x 1022 years
Structural test:
No redundant adder hardware, 64bit slices
Each with 27faults (using fault equivalence)
At most 64 x 27 = 1728faults (tests)
Takes 0.000001728 s on 1 GHz ATE
Designer gives small set of functional testsaugment with structuraltests to boost coverage to 98+%
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
62 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
60/84
Automatic Test PatternGeneration: Path Sensitization
Out
Techniques Used: D-algorithm, Podem
Goals: Determine input pattern that makes a faultcontrollable (triggers the fault, and makes its impactvisible at the output nodes)
sa011
0
11
10
1
Fault propagation
Fault enabling
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
63 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
61/84
Path Sensitization MethodCircuit Example
1 Fault Sensitization2 Fault Propagation
3 Line Justification
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
64 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
62/84
Using 5-Valued Logic
Symbol
D
D
01
X
Meaning
0/1
1/0
0/01/1
X/X
Failing
Machine
1
0
01
X
Good
Machine
0
1
01
X
Represent two machines, which are simulated
simultaneously:
Good circuit machine (1stvalue)
Bad circuit machine (2ndvalue)
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
65 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
63/84
Path Sensitization MethodCircuit Example
Try path f h k L blocked atj, sincethere is no way to justify the 1 oni
1
0
D
D1
1
1D
DD
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
66 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
64/84
Path Sensitization MethodCircuit Example
Try simultaneous paths f h k Land
g i j k Lblocked at kbecause D-
frontier(chain of Dor D) disappears
1
DD D
D
D
1
1
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
67 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
65/84
Path Sensitization MethodCircuit Example
Final try: path g i j k Ltest found!
0
DD D
1 DD
1
0
1
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
68 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
66/84
Irredundant Hardware and TestPatterns
Combinational ATPG can find redundant (unnecessary)
hardware
Fault Test
asa1, bsa0 A= 1
asa0, bsa1 A= 0
Therefore, these faults are not redundant[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
69 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
67/84
Redundant Hardware andSimplification
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
70 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
68/84
Redundant Fault qsa1
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
71 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
69/84
Multiple Fault Masking
fsa0 tested when fault qsa1 not there
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
72 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
70/84
Multiple Fault Masking
fsa0 masked when fault qsa1 also present
[Adapted from VLSI Testing Course by Bushnell/Agrawal at Rutgers]
73 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
71/84
Ad-hoc Test
Inserting multiplexer improves testability
I/O bus
Memory
Processor
da
ta
add
ress
I/O bus
Memory
Processor
da
ta
add
ress
selecttest
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
74 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
72/84
Design-for-Testability
Extra hardware
no functionality other than to improve testability
take penalty in area and performance ifobservability and controllability improved
Extra I/O pins
e.g. Test port
multiplex test andn ormal signals on same pins
75 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
73/84
Scan-based Test
Logic
Combinational
Logic
Combinational
Register
Register
OutIn
ScanOutScanIn
A B
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
76 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
74/84
Scan-based Test: Operation
Test
ScanIn
Test
Latch
In0
Out0
Test Test
Latch
In1
Out1
Test Test
Latch
In2
Out2
Test Test
Latch
In3
Out3
ScanOut
Test
1
2
Ncycles 1 cycleevaluationscan-in
Ncyclesscan-out
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
77 Copyright 2004 Mani Srivastava
P l i H ld SRL
5/26/2018 Design for Test
75/84
Polarity-Hold SRL(Shift-Register Latch)
Level sensitive Scan Design (LSSD)Introduced at IBM and set as company policy
System Data
System Clock
Scan Data
Shift A Clock
D
C
SI
A
L1
L2Shift B Clock B
Q
Q
SO
SO
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
78 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
76/84
Scan-Path Register
SCANIN
IN
LOAD
SCAN PHI2 PHI1
KEEP
OUT
SCANOUT
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
79 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
77/84
Scan-Path Testing
Partial-Scan can be more effective for pipelined datapaths
REG[5]
REG[4]
REG[3]REG[2]
REG[0]REG[1]
+
COMP
OUT
SCANIN
COMPIN
SCANOUT
A B
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
80 Copyright 2004 Mani Srivastava
B d S
5/26/2018 Design for Test
78/84
Boundary Scan(JTAG or IEEE1149)Printed-circuit board
Logic
scan path
normalinterconnect
Packaged IC
Bonding Pad
Scan-in
Scan-out
si so
Board testing becomes as problematic as chip testing
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
81 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
79/84
Built-in Self-test (BIST)
(Sub)-Circuit
Under
Test
Stimulus Generator Response Analyzer
Test Controller
Rapidly becoming more important with increasingchip-complexity and larger modules
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
82 Copyright 2004 Mani Srivastava
Li F db k Shift R i t
5/26/2018 Design for Test
80/84
Linear-Feedback Shift Register(LFSR)
S0 S1 S2
R R R
1 0 00 1 01 0 11 1 01 1 1
0 1 10 0 11 0 0
Pseudo-Random Pattern Generator: 2N-1 states
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
83 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
81/84
Signature Analysis
R
Counter
In
Counts transitions on single-bit streamCompression in time
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
84 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
82/84
BILBO
S0
R R R
S1 S2
ScanOutScanIn mux
D2D1D0B0
B1
Operation modeB0
Normal
Scan
Signature analysis
1 1
0 0
1 0 Pattern generation or
0 1 Reset
B1
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
85 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
83/84
BILBO Application
Logic
Combinational
Logic
Combinational
BILBO
-B
BILBO
-A OutIn
ScanIn ScanOut
[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]
86 Copyright 2004 Mani Srivastava
5/26/2018 Design for Test
84/84
Memory Self-test
FSMMemory Signature
AnalysisUnder Test
data
address &
R/Wcontrol
-in
data-out
Patterns: Writing/Reading 0s, 1s,Walking 0s, 1sGalloping 0s, 1s