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Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
DesignMethodologies
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
The Design Problem
Source: sematech97
A growing gap between design complexity and design productivity
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Design Methodology
• Design process traverses iteratively between three abstractions: behavior, structure, and geometry• More and more automation for each of these steps
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Design Analysis and Verification
l Accounts for largest fraction of design timel More efficient when done at higher levels of
abstraction - selection of correct analysislevel can account for multiple orders ofmagnitude in verification time
l Two major approaches:» Simulation» Verification
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Digital Data treated as Analog Signal
V out
(V)
5.0
3.0
1.0
–1.0
t (nsec)
21.510.50
Vin Vout
tpHL
Gn,p
In Out
VDD
Bp
Bn
Dn,p
Sn
Sp
Circuit Simulation
Both Time and Data treated as Analog QuantitiesAlso complicated by presence of non-linear elements(relaxed in timing simulation)
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Representing Data as Discrete Entity
V
t
VM
t1 t2
0 1 0 VDD
Rn
Rp
CL
Discretizing the data usingswitching threshold
The linear switch modelof the inverter
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Circuit versus Switch-Level Simulation
0 5 10 15 20time (nsec)
–1.0
1.0
3.0
5.0
CIN
OUT[3]
OUT[2]
Circ
uit
Sw
itch
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Structural Description of Accumulatorentity accumulator is
port ( -- definition of input and output terminalsDI: in bit_vector(15 downto 0) -- a vector of 16 bit wideDO: inout bit_vector(15 downto 0);CLK: in bit
);end accumulator;
architecture structure of accumulator iscomponent reg -- definition of register ports
port (DI : in bit_vector(15 downto 0);DO : out bit_vector(15 downto 0);CLK : in bit
);end component;component add -- definition of adder ports
port (IN0 : in bit_vector(15 downto 0);IN1 : in bit_vector(15 downto 0);OUT0 : out bit_vector(15 downto 0)
);end component;
-- definition of accumulator structuresi gnal X : bit_vector(15 downto 0);begin
add1 : addport map (DI, DO, X); -- defines port connectivity
reg1 : regport map (X, DO, CLK);
end structure;
Design defined as composition ofregister and full-adder cells (“netlist”)
Data represented as {0,1,Z}
Time discretized and progresses withunit steps
Description language: VHDLOther options: schematics, Verilog
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Behavioral Description of Accumulator
entity accumulator isport (
DI : in integer;DO : inout integer := 0;CLK : in bit
);end accumulator;
architecture behavior of accumulator isbegin
process(CLK)variable X : integer := 0; -- intermediate variablebegin
if CLK = '1' thenX <= DO + D1;DO <= X;
end if;end process;
end behavior;
Design described as set of input-outputrelations, regardless of chosen implementation
Data described at higher abstractionlevel (“integer”)
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Behavioral simulation of accumulator
Integer data
Discrete time
(Synopsys Waves display tool)
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Timing Verification
(Synopsys-Epic Pathmill)
Critical path
Enumerates and rankorders critical timing paths
No simulation needed!
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Issues in Timing Verification
bypass
4-bit adder
MU
X
Out
In
False Timing Paths
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Implementation Methodologies
Digital Circuit Implementation Approaches
Custom Semi-custom
Cell-Based Array-Based
Standard Cells Macro Cells Pre-diffused Pre-wired(FPGA)Compiled Cells (Gate Arrays)
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Custom Design – Layout Editor
Magic Layout Editor(UC Berkeley)
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Symbolic Layout
1
3
In Out
VDD
GND
Stick diagram of inverter
• Dimensionless layout entities• Only topology is important• Final layout generated by “compaction” program
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Cell-based Design (or standard cells)
FunctionalModule(RAM,multiplier, … )
Row
s of C
ells
Logic Cell
RoutingChannel
Feedthrough Cell
Routing channelrequirements arereduced by presenceof more interconnectlayers
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Standard Cell — Example
[Brodersen92]
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Standard Cell - Example
3-input NAND cell(from Mississippi State Library)characterized for fanout of 4 andfor three different technologies
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Automatic Cell Generation
Random-logic layoutgenerated by CLEOcell compiler (Digital)
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Module Generators —Compiled Datapath
adde
r
buff
er
reg0
reg1
mux
bus0
bus2
bus1
bit-slicerouting area feed-through
Advantages: One-dimensional placement/routing problem
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Macrocell Design Methodology
Macrocell
Interconnect Bus
Routing Channel
Floorplan:Defines overalltopology of design,relative placement ofmodules, and global routes of busses,supplies, and clocks
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Macrocell-Based DesignExample
Video-encoder chip[Brodersen92]
SRAM
SRAM
Rou
ting
Cha
nnel
Data paths
Standard cells
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Gate Array — Sea-of-gates
rows of
cells
routing channel
uncommitted
VDD
GND
polysilicon
metal
possiblecontact
In1 In2 In3 In4
Out
UncommitedCell
CommittedCell(4-input NOR)
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Sea-of-gate Primitive Cells
NMOS
PMOS
Oxide-isolation
PMOS
NMOS
NMOS
Using oxide-isolation Using gate-isolation
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Sea-of-gates
Random Logic
MemorySubsystem
LSI Logic LEA300K(0.6 µm CMOS)
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Prewired Arrays
Categories of prewired arrays (or field-programmable devices):
l Fuse-based (program-once)l Non-volatile EPROM basedl RAM based
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Programmable Logic Devices
PLA PROM PAL
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
EPLD Block Diagram
Macrocell
Courtesy Altera Corp.
Primary inputs
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Field-Programmable Gate ArraysFuse-based
I/O Buffers
Program/Test/Diagnostics
I/O Buffers
I/O B
uffe
rs
I/O B
uffe
rs
Vertical routes
Rows of logic modulesRouting channels
Standard-cell likefloorplan
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Interconnect
Cell
Horizontaltracks
Vertical tracks
Input/output pin
Antifuse
Programmed interconnection
Programming interconnect using anti-fuses
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Field-Programmable Gate ArraysRAM-based
CLB CLB
CLBCLB
swi tching matrixHorizontalroutingchannel
Vertical routing channel
Interconnect point
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
RAM-based FPGABasic Cell (CLB)
RQ1D
CE
RQ2D
CE
F
G
F
G
F
G
RD in
Clock
CE
F
G
AB/Q1/Q2C/Q1/Q2
D
AB/Q1/Q2C/Q1/Q2
D
E
Combinational logic Storage elements
Any function of up to 4 variables
Any function of up to 4 variables
Courtesy of Xilinx
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
RAM-based FPGA
Xilinx XC4025
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Taxonomy of Synthesis TasksArchitectural Level Logic Level Circuit Level
Beh
avi
ora
l V
iew
Str
uc
tura
l V
iew
ArchitectureSynthesis
LogicSynthesis
CircuitSynthesis
0
13
2
state(i: 1..16) ::sum = sum*z–1 +coeff[i]*In*z–1
ab
c x
a
bc1
2
2
4
tp
ab
cx
D
mem
*
fsm
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Designfor Test
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Validation and Test ofManufactured Circuits
Components of DFT strategy
• Provide circuitry to enable test• Provide test patterns that guarantee reasonable
coverage
Goals of Design-for-Test (DFT)Make testing of manufactured part swift andcomprehensive
DFT MantraProvide controllability and observability
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Test Classification
l Diagnostic test» used in chip/board debugging» defect localization
l “go/no go” or production test» Used in chip production
l Parametric test» x ε [v,i] versus x ε [0,1]» check parameters such as NM, Vt, tp, T
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Design for Testability
M state regs
N inputs K outputs
K outputsN inputsCombinational
Logic
Module
Combinational
Logic
Module
(a) Combinational function (b) Sequential engine
2N patterns 2N+M patterns
Exhaustive test is impossible or unpractical
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Problem:Controllability/Observability
l Combinational Circuits:controllable and observable - relatively easy to
determine test patterns
l Sequential Circuits: State!Turn into combinational circuits or use self-test
l Memory: requires complex patternsUse self-test
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Test Approaches
l Ad-hoc testingl Scan-based Testl Self-TestProblem is getting harder
» increasing complexity and heterogeneouscombination of modules in system-on-a-chip.
» Advanced packaging and assembly techniquesextend problem to the board level
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Generating and ValidatingTest-Vectors
l Automatic test-pattern generation (ATPG)» for given fault, determine excitation vector (called test vector)
that will propagate error to primary (observable) output» majority of available tools: combinational networks only» sequential ATPG available from academic research
l Fault simulation» determines test coverage of proposed test-vector set» simulates correct network in parallel with faulty networks
l Both require adequate models of faults inCMOS integrated circuits
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Fault Models
0
1
sa0
sa1
(output)
(input)
Most Popular - “Stuck - at” model
x1
x2x3
Z
α
β
γ
α, γ : x1 sa1β : x1 sa0 or x2 sa0γ : Z sa1
Covers almost all (other) occurring faults, such asopens and shorts.
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Problem with stuck-at model:CMOS open fault
x1 x2
x1
x2
Z
Sequential effectNeeds two vectors to ensure detection!
Other options: use stuck-open or stuck-short modelsThis requires fault-simulation and analysis at the switch ortransistor level - Very expensive!
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Problem with stuck-at model:CMOS short fault
‘0’
‘0’
‘0’
‘1’
C
A B
D
A
B
C
D
Causes short circuit betweenVdd and GND for A=C=0, B=1
Possible approach:Supply Current Measurement (IDDQ)but: not applicable for gigascale integration
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Path Sensitization
Out
Techniques Used: D-algorithm, Podem
Goals: Determine input pattern that makes a faultcontrollable (triggers the fault, and makes its impactvisible at the output nodes)
sa011
0
11 1
0
1
Fault propagation
Fault enabling
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Ad-hoc Test
Inserting multiplexer improves testability I/O bus
Memory
Processor
data
addr
ess
I/O bus
Memory
Processor
data
addr
ess
selecttest
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Scan-based Test
Logic
Combinational
Logic
Combinational
Reg
iste
r
Reg
iste
r
OutIn
ScanOutScanIn
A B
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Polarity-Hold SRL(Shift-Register Latch)
Introduced at IBM and set as company policy
System DataSystem ClockScan DataShift A Clock
DCSIA
L1
L2Shift B Clock B
Q
Q
SO
SO
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Scan-Path Register
SCANIN
IN
LOAD
SCAN PHI2 PHI1
KEEP
OUT
SCANOUT
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Scan-based Test — Operation
TestScanIn
Test
Latch
In0
Out0
Test Test
Latch
In1
Out1
Test Test
Latch
In2
Out2
Test Test
Latch
In3
Out3
ScanOut
Test
φ1
φ2
N cycles 1 cycleevaluationscan-in
N cyclesscan-out
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Scan-Path Testing
Partial-Scan can be more effective for pipelined datapaths
REG[5]
REG[4]
REG[3]REG[2]
REG[0]REG[1]
+
COMP
OUT
SCANIN
COMPIN
SCANOUT
A B
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Boundary Scan (JTAG)Printed-circuit board
Logic
scan path
normal interconnect
Packaged IC
Bonding Pad
Scan-in
Scan-out
si so
Board testing becomes as problematic as chip testing
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Self-test
(Sub)-Circuit
Under
Test
Stimulus Generator Response Analyzer
Test Controller
Rapidly becoming more important with increasingchip-complexity and larger modules
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Linear-Feedback Shift Register (LFSR)
S0 S1 S2
R R R
1 0 00 1 01 0 11 1 01 1 10 1 10 0 11 0 0
Pseudo-Random Pattern Generator
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Signature Analysis
R
Counter
In
Counts transitions on single-bit stream ≡ Compression in time
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
BILBO
S0
R R R
S1 S2
ScanOutScanIn mux
D2D1D0B0
B1
Operation modeB0
NormalScan
Signature analysis
1 10 0
1 0 Pattern generation or
0 1 Reset
B1
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
BILBO Application
Logic
Combinational
Logic
Combinational
BIL
BO
-B
BIL
BO
-A OutIn
ScanIn ScanOut
Digital Integrated Circuits © Prentice Hall 1995Design Methodologies
Memory Self-Test
FSMMemory Signature
AnalysisUnder Test
data
address &
R/W control
-in
data-out
Patterns: Writing/Reading 0s, 1s, Walking 0s, 1s Galloping 0s, 1s