TUTORIAL ON USING XILINX ISE DESIGN SUITE 10.1:Mixing VHDL and Schematics “Design of an AdderSubtractor” for Spartan-II E (Digilent D2E Board)

Shawki Areibi

September 28, 2009

1 Introduction

The objective of this tutorial is to show you how VHDL can be incorporated into a schematic designusing the ISE tools. At this point, the student should have read and understood the followingdocuments:

1. TUTORIAL ON USING XILINX ISE DESIGN SUITE 10.1: Design Entry ofFull Adder Using Schematic Capture

2. TUTORIAL ON USING XILINX ISE DESIGN SUITE 10.1: Design Entry UsingVHDL (Full Adder)

Students should also be familiar with the Schematic Editor and the Test Bencher in the ProjectNavigator software.

The tutorial will first attempt to design a 4-bit adder using VHDL. The next step is to transformthis VHDL code into schematic symbol which will be again used at the schematic capture level todesign an adder/subtractor circuit.

2 Starting a new project

Since we wish to combine VHDL with schematic capture, we will create a new project with schematicas the Top-Level Module Type.

1. Load the Project Navigator from the → All Programs → Development → XilinxISE Design Suite 10.1 → ISE → Project Navigator.

2. The Project Navigator window will appear. Select File → New Project

3. The New Project Wizard dialog box will appear. Specify the directory in which you want tostore the project in and give the project a name. In the Top-Level Source Type sectionselect Schematic and click Next.

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4. Another New Project Wizard dialog box will appear prompting you for device, synthesis andsimulation settings for the project.

In this dialog box verify the following settings:

• Device Family → Spartan2E.

• Device → xc2s200e.

• Package → pq208.

• Speed Grade → -6.

• Synthesis Tool → XST (VHDL/Verilog).

• Simulator → ISE Simulator (VHDL/Verilog).

• Generated Simulation Language → VHDL.

If the information is correct click Next.

5. The next dialog box will ask if you wish to add a new source file to the project. Click NewSource.... A new dialog box will appear prompting you for the file type, name and location.Select VHDL module from the list of file types and name the file ”MyAdder” (Project

Navigator will append the appropriate file extension). The default location should be theproject directory and ensure the Add to project box is checked.

6. In the Define VHDL Source dialog box that appears, add ports A, B and CI as inputs andCO and S as outputs. Click Next when this is done.

7. The next dialog box will allow you to confirm the previous choices. Click if they arecorrect.

8. You will now return to the New Project dialog box and the ”MyAdder.vhd” source templatethat you have created will now be listed. Click Next. The next dialog box is used to addexisting source files to the project. Since we are only using new source files in this project,click Next. Finally, a confirmation dialog box will appear. Click Finish if the information iscorrect.

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3 Using the HDL Editor for VHDL

We are now ready to start working with the HDL Editor.

1. At the completion of the last section the VHDL editor window should now have the templatecode with the variables that you entered. Modify the code to match the following:

– 1 bit Full Adder

library IEEE;

use IEEE.std logic 1164.all;

entity fulladd is

port (

A, B, Ci: in STD LOGIC;

Co, S: out STD LOGIC

);

end fulladd;

architecture fulladd arch of fulladd is

begin

S ⇐ ((A xor B) xor Ci);

Co ⇐ ((A and B) or (Ci and (A xor B)));

end fulladd arch;

– 4 bit Adder

library IEEE;

use IEEE.std logic 1164.all;

entity adder4 is

port (

A0,A1,A2,A3: in STD LOGIC;

B0,B1,B2,B3: in STD LOGIC;

Ci: in STD LOGIC;

Co: out STD LOGIC;

S0,S1,S2,S3: out STD LOGIC

);

end adder4;

architecture adder4 arch of adder4 is

COMPONENT fulladd

port (

A, B, Ci: in STD LOGIC;

Co, S: out STD LOGIC

);

END COMPONENT;

signal tmp: STD LOGIC VECTOR (2 downto 0);

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begin

U0: fulladd port map(Ci⇒Ci, A⇒A0,B⇒B0,S⇒S0,Co⇒tmp(0));

U1: fulladd port map(Ci⇒tmp(0),A⇒A1,B⇒B1,S⇒S1,Co⇒tmp(1));

U2: fulladd port map(Ci⇒tmp(1),A⇒A2,B⇒B2,S⇒S2,Co⇒tmp(2));

U3: fulladd port map(Ci⇒tmp(2),A⇒A3,B⇒B3,S⇒S3,Co⇒Co);

end adder4 arch;

2. We must now check that the syntax of the VHDL code is correct. In the Project Navigator

window highlight the VHDL source in the Sources in Project pane. Expand ifit is not already and double click A process will be spawned to verify the VHDLcode for syntax errors.

• If there are none, a green check mark will appear next to the Check Syntax process.

• If errors where found, A red cross will appear next to the Check Syntax process. Theerrors will be listed in the Errors tab of the Transcript window located at the bottomof the Project Navigator window. In it you will see a listing of the errors and the lineson which they occur. If you double click on an error message a red dot will appear inthe VHDL editor pane next to (or close to) the line where the error was found.

3. Once you have eliminated all of the errors, save your work.

4. We will now create a module that can be used in the Schematic Editor. Expand theif it is not already and double click . If the process is successful a green checkwill appear next to the process name. Output from the process is shown in the Transcriptwindow at the bottom of the Project Navigator window. We are now ready to use the symbolin a schematic.

4 Using the macro

Now return to the Project Navigator and add a schematic source to the project.In the Symbols tab of the Options toolbar, the project directory will be listed in the Catagories

pane. Highlight this entry and the adder4 symbol that you have created will be listed in the Sym-bols pane. You can use it in the same way you use the other components.

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5 Adder/Subtractor Circuit

The addition of two signed binary numbers with negative numbers represented in signed-2’s com-plement form is obtained from the addition of the two numbers, including their sign bits. A carryout of the sign bit position is discarded.

The subtraction of two signed binary numbers when negative numbers are in 2’s complementform is very simple and can be stated as follows: “Take the 2’s complement of the subtrahend(including the sign bit) and add it to the minuend (including the sign bit). A carry out of the signbit position is discarded.

5.1 Adder-Subtractor Circuit

FAFAFA FA

AAAA BBBB

SSS SC

CCCC

0

00

0

11

12

2233

3 2 1

3

4

Figure 1: 4-Bit Adder

The circuit for subtracting A - B consists of a parallel adder as shown in Figure 1 with invertersplaced between each B terminal and the corresponding full-adder input. The input carry C0 must beequal to 1. The operation that is performed becomes A plus the 1’s complement of B plus 1. This isequal to A plus the 2’s complement of B. The addition and subtraction operations can be combinedinto one circuit with one common binary adder. This is done by including an exclusive-OR gatewith each full adder. A 4-bit adder-subtractor circuit is shown in Figure 2. Input S controls theoperation.

1. When S = 0 the circuit is an adder.

2. When S = 1 the circuit becomes a subtractor.

Each exclusive-OR gate receives input S and one of the inputs of B, Bi. When S = 0, we haveBi ⊕ 0 = Bi. If the full adders receive the value of B, and the input carry is 0, the circuit performsA plus B. When S = 1, we have Bi ⊕ 1 = Bi and C0 = 1. The circuit performs the operation Aplus the 2’s complement of B.

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A

SSS SC

CCCC

0

0

0

1

12

23

3 2 1

3

4

B3 B2 B1 B0

S

FAFAFA FA

AAA

Figure 2: 4-Bit Adder/Subtractor

6 Appendix A - User Constrained File (UCF)

A User Constraint File (UCF) is used to assign I/O pins in a design to the actual pins on theFPGA.

The UCF file has the following format:

NET <pin name in VHDL design> LOC=P<pin number on FPGA>

6.1 LEDs

The Digilent DIO1 Board provides a series of eight LEDs (LD1–LD8) and four multiplexed 7-segment displays (DSP1) for use by a Digilent 2E FPGA Board. All of these LEDs are Largeactive high meaning that an LED segment will glow when a logic-high is applied to it. Thefollowing tables show the connection from the Digilent 2E Board to the LEDs on the DIO1 Boardexpressed as UCF constraints.

—Description —LocationNET SEGA LOC=P127NET SEGB LOC=P132NET SEGC LOC=P134NET SEGD LOC=P136NET SEGE LOC=P139NET SEGF LOC=P141NET SEGG LOC=P146NET SEGDP LOC=P148

Table 1: Connections between DIO1 7-Segment display and Digilent 2E

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—Description —LocationNET LD < 1 > LOC=P154NET LD < 2 > LOC=P161NET LD < 3 > LOC=P163NET LD < 4 > LOC=P165NET LD < 5 > LOC=P167NET LD < 6 > LOC=P169NET LD < 7 > LOC=P174NET LD < 8 > LOC=P176

Table 2: Connections between the DIO1 LEDs and Digilent 2E

—Description —LocationNET SW < 1 > LOC=P126NET SW < 2 > LOC=P129NET SW < 3 > LOC=P133NET SW < 4 > LOC=P135NET SW < 5 > LOC=P138NET SW < 6 > LOC=P140NET SW < 7 > LOC=P145NET SW < 8 > LOC=P147

Table 3: Connections between the DIO1 slide switches and Digilent 2E

6.2 Switches

The DIO1 has bank of eight slide switches and five pushbuttons (labeled BTN1 through BTN5)that are accessible from an Digilent 2E Board.

When closed or ON, each DIP switch pulls the connected pin of the D2E Board to ground.When the DIP switch is open or OFF, the pin is pulled high through a 10KΩ resistor.

When pressed, each pushbutton pulls the connected pin of the D2E Board to ground. Otherwise,the pin is pulled high through a 10KΩ resistor. The table below show the connections from theDigilent D2E Board to the switches on the Digilent IO1 Board expressed as UCF constraints.

—Description —LocationNET BTN < 1 > LOC=P149NET BTN < 2 > LOC=P150NET BTN < 3 > LOC=P151NET BTN < 4 > LOC=P152NET BTN < 5 > LOC=P178

Table 4: Connections between the DIO1 pushbuttons and Digilent 2E

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