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Design of Sequential Elements for Low Power

Clocking System

AIM:

The main aim of the project is to design “Design of Sequential Elements for Low

Power Clocking System”.

(ABS!AC"

Power consumption is a major bottleneck of system performance and is listed as

one of the top three challenges in International Technology Roadmap for

Semiconductor !!". In practice# a large portion of the on chip power is consumed

 by the clock system which is made of the clock distribution network and flop$

flops. In this paper# %arious design techni&ues for a low power clocking system are

sur%eyed. 'mong them is an effecti%e way to reduce capacity of the clock load by

minimi(ing number of clocked transistors. To approach this# we propose a no%el

clocked pair shared flip$flop which reduces the number of local clocked transistors

 by appro)imately *!+. ' *+ reduction of clock dri%ing power is achie%ed. In

addition# low swing and double edge clocking# can be easily incorporated into the

new flip$flop to build clocking systems

Pro#ose$ Met%o$:

In this architecture the proposed ,PS-- consume less power than ,/--. -urtherwe can apply low power techni&ues to reduce static power. In these low power

techni&ues the e)tra circuit added to e)isting circuit e%en the power is reduced.

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A$&antage:

The proposed multiband fle)ible di%ider also uses an impro%ed loadable bit$cell for 

Swallow$counter and consumes a power of !.01 and . m2 in

.*$ and 3$45( bands# respecti%ely# and pro%ides a solution to the low

 power P66 synthesi(ers for 7luetooth# 8igbee# I999 "!.:3.*# and

I999 "!.::a;b;g 26'< applications with %ariable channel spacing.  BL'C

DIA)!AM:

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''LS= hspice>%'$!!".!?# t$spice

!E*E!E+CE: 

@:A 5. Bawaguchi and T. Sakurai# “' reduced clock$swing flip$flop CR,S--D for

1?+ power reduction#” I999 E. Solid$State ,ircuits# %ol. ??# no. 3# pp. "!FG"::#

/ay :00".

@A '. ,handrakasan# 2. 7owhill# and -. -o)# esign of 5igh$Performance

/icroprocessor ,ircuits# :st ed. Piscataway# <E= I999 Press#!!:.

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@?A 4. 4erosa# “' . 2# "! /5( superscalar RIS, microprocessor#”I999

E. Solid$State ,ircuits# %ol. 0# no. :# pp. :**!G:*3*# ec. :00*.

@*A 7. <ikolic# H. 4. klob(ija# H. Stojano%ic# 2. Eia# E. B. ,hiu# and /./.

6eung# “Impro%ed sense$amplifier$based flip$flop= esign and measurements#”

I999 E. Solid$State ,ircuits# %ol. ?3# no. 1# pp. "F1G""?# Eun. !!!.

@3A S. . <aff(iger# 4. ,olon$7onet# T. -ischer# R. Riedlinger# T. E.Sulli%an# and

T. 4rutkowski# “The implementation of the Itanium microprocessor#” I999 E.Solid$State ,ircuits# %ol. ?F# no. ::# pp.:**"G:*1!# <o%. !!

V.Mallikarjuna (Project manager) Mobile No: +91-8297578555.

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