Design Problem Design Space Explorationese570/spring2016/handouts/lec18_6up.pdfSequential Circuit (or State Machine) Construct 10 Kenneth R. Laker, University of Pennsylvania, updated

1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 18: March 24, 2016 Sequential MOS Logic and Timing Hazards

Penn ESE 570 Spring 2016 – Khanna

Lecture Outline

!  Finish: Design Space Exploration "  Design Problem Example: Match Circuit

!  Sequential MOS Logic !  Timing Hazards

2 Penn ESE 570 Spring 2016 – Khanna

Design Space Exploration


Design Problem

!  Function: Identify equivalence of two 32bit inputs !  Optimize: Minimize total energy !  Assumptions: Match case uncommon

"  Ie. Most of the time, the inputs won’t be matched

!  Deliberately focus on Energy to complement project "  …but will still talk about delay


Design Space Dimensions

!  Vdd !  Topology

"  Gate choice, logical optimization "  Fanin, fanout, Serial vs. parallel

!  Gate style / logic family "  CMOS, Ratioed (N load, P load)

!  Transistor Sizing !  Vth

!  The choices you make impact area, speed (delay), power


Ideas

!  Three components of power "  Ptot = Pstatic + Pdyn+ Psc

!  We know many things we can do to our circuits !  Design space is large !  Systematically identify dimensions !  Identify continuum (trends) tuning when possible !  Watch tradeoffs

"  …don’t over-tune


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Sequential MOS Logic


Classes of Logic Circuits

8

Kenneth R. Laker,

University of Pennsylvania,

updated 25Mar15

two stable op. pts. Latch – level triggered.

Flip-Flop – edge triggered.

one stable op. pt. One-shot – single

pulse output

no stable op. pt. Ring Oscillator

Combinational Circuits: a. Current Output(s) depend ONLY on Current Inputs. b. Suited to problems that can be solved using truth tables.

Sequential Circuits or State Machines: a. Current Output(s) depend on Current Inputs and Past Inputs via State(s). b. Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner.


Functions Using Sequential Operations


Sequential Circuit (or State Machine) Construct

10

Kenneth R. Laker, University of Pennsylvania,

updated 25Mar15

-> Register is used to Store Past Values of State(s) and Output(s) -> Synchronous Sequential Circuit – clock, outputs change with clock event -> Asynchronous Sequential Circuit – no clock, outputs change after inputs change

Vo1 Vo2

.

.

.

.

.

.

.

.

Vo3

Present State

Next State

Inputs Outputs

Clock

REGISTER


Static Bistable Sequential Circuits

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updated 25Mar15

Basic Cross-coupled Inverter

pair

Q

Q


12


updated 25Mar15


pair

Q

Q



3

13


pair


Q

Q


14


updated 25Mar15

Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s) to change the circuit's State.


pair Q

Q

VOH = VDD

VOL = 0

maintain stable state. STATIC: VDD and GND are required to maintain a stable state.



Basic Sequential Circuits (Cells)

!  Latches !  Registers


Latch

16

Q =CLK ⋅Q+CLK ⋅ In

!  Level-sensitive device !  Positive Latch

"  Output follows input if CLK high

!  Negative Latch "  Output follows input if

CLK low


Register

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!  Edge-triggered storage element

!  Positive edge-triggered "  Input sampled on

rising CLK edge

!  Negative edge-triggered "  Input sampled on

falling CLK edge


Shift Register

!  How do you make a shift register out of latches?


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Two Phase Non-Overlapping Clocks

!  Build master-slave register from pair of latches !  Control with non-overlapping clocks









!  What could go wrong if the overlap?


Clocking Discipline

!  Follow discipline of combinational logic broken by registers

!  Compute "  From state elements "  Through combinational logic "  To new values for state elements

!  As long as clock cycle long enough, "  Will get correct behavior

23 Penn ESE 570 Spring 2016 – Khanna 24

CMOS SR Latch – NOR2

* *


5


25

basic cross-coupled inverter

pair



26


pair



27


pair

SET OP: S = 1, R = 0


28


pair

RESET OP: R = 1, S = 0



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pair

HOLD OP: S = 0, R = 0



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pair

HOLD OP: S = 0, R = 0


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31


* *

“ACTIVE HIGH”


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updated 25Mar15

CMOS SR Latch – NAND2

basic cross-coupled inverter pair


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CMOS SR Latch – NAND2

* *

“ACTIVE LOW” * *


Synchronous Latches

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NAND SR Latch NOTE: S and R are asynchronous.

CK

S’/R'

NAND SR LATCH

S/R


Synchronous Latches

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NAND SR Latch NOTE: S and R are asynchronous.

CK

S’/R'

NAND SR LATCH

S/R

SET STATE: CK = 1, S = 1, R = 0 => S' = 0, R' = 1 => Qn+1 = 1, Qn+1 = 0 RESET STATE: CK = 1, S = 0, R = 1 => S' = 1, R' = 0 => Qn+1 = 0, Qn+1 = 1 NOT ALLOWED: CK = 1, S = 1, R = 1 => S' = 0, R' = 0

IS CK = 1, S = 0, R = 0 a HOLD STATE? Penn ESE 570 Spring 2016 – Khanna

36

R

Q error due to glitch on S

T glitch

HOLD STATE: CK = 1, S = 0, R = 0

Synchronous Latches


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Latch

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Q =CLK ⋅Q+CLK ⋅ In

!  Level-sensitive device !  Positive Latch

"  Output follows input if CLK high

!  Negative Latch "  Output follows input if

CLK low


Static CMOS D-Latch

38


updated 25Mar15

S

R

LATCH

If CK = 1

If CK = 0, HOLD


Static CMOS D-Latch

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updated 25Mar15

CK D S' R' Qn+1 Qn+1 1 1 0 1 1 0 SR-Set 1 0 1 0 0 1 SR-Reset 0 x 0 0 Qn Qn SR-Hold

+ NO TOGGLE + NO NOT-ALLOWED INPUTS

S

R

LATCH

18 Transistors

If CK = 1

If CK = 0, HOLD


Static CMOS TG D-LATCH – 8 Transistors

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updated 25Mar15

**Transistor level implementation using transmission gates requires fewer transistors

8 Transistors


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updated 25Mar15

QQ

D

CKCK

CK

CK

Static CMOS TG D-LATCH


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updated 25Mar15

Static CMOS TG D-LATCH

When CK = 1 output Q = D, and tracks D until CK = 0, the D-Latch is referred to positive level triggered.

When CK → 1 to 0, the Q = D is captured, held (or stored) in the Latch.


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D-LATCH Timing Requirements


Ideas

!  Synchronize circuits "  to external events (eg. Clk) "  disciplined reuse of circuitry

!  Leads to clocked circuit discipline "  Uses state holding element (eg. Latches and registers) "  Prevents

"  Timing assumptions "  (More) complex reasoning about all possible timings

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Admin

!  HW 7 due 3/31 "  Design 8 bit adder "  Extra Credit: Modify design for optimized delay (Submit

online before 4/8) "  Get up to 10 points added to your Midterm grade

!  NO LAYOUT


Documents

Design Problem Design Space Explorationese570/spring2016/handouts/lec18_6up.pdfSequential Circuit (or State Machine) Construct 10 Kenneth R. Laker, University of Pennsylvania, updated