Design, Simulation, and Layout of a Serial Digital-to-Analog Converter (DAC) Array

7710 Mandan Road #102 Greenbelt, MD 20770 May 10, 2007 Prof. Timothy Horiuchi Department of Electrical and Computer Engineering A.V. Williams 2215 University of Maryland College Park, MD 20742 Dear Prof. Horiuchi: This package contains a report on the design, simulation, and physical layout of a low power, mixed-signal, Digital-to-Analog Converter (DAC) array. As you might already know, pin limitations are always a problem in the design of many analog VLSI circuits. Providing constant transistor bias voltages limits the availability of pins that can be used to control and monitor on-chip time-varying signals. The DAC array proposed in the attached report will eliminate the overwhelming number of DIP pins used to supply constant transistor bias voltages. The DAC array requires only six control pins and allows, theoretically, an unlimited number of transistors biases without requiring any additional control pins. Thus, the DAC array will maximize the number of pins that could be dedicated to monitoring and controlling on-chip time-varying signals. In addition to reporting the design of the DAC array, other aspects of the DAC array are discussed as well. The design specifications of the DAC array are reported, along with the actual design used to fulfill the required specifications. The importance of monotonicity in the DAC array, small circuit area, modularity of the design, and speed requirements are discussed in the report. The operation of each component of the DAC array including its computer simulation result is also presented. Finally, a suggested implementation of the DAC array’s physical layout has also been provided so that the DAC array circuit design can be sent to MOSIS immediately for fabrication. The report, therefore, is an all-inclusive guide to the design, operation, computer simulation, and physical layout of the DAC array in its entirety. The DAC array was designed to address the pin limitations issue encountered by the researchers at the Computational Sensorimotor and Systems Laboratory (CSSL). However, in order to broaden the audience, publishing the report on your research group website might benefit other circuit design research laboratories currently facing pin limitation issues. Inside the CSSL, printed copies of the report could be provided to your post-doctoral research associates, graduate students, and undergraduate research assistants. Of course, the exact means by which the report will be distributed is left to your discretion. Please feel free to contact me if you have any questions or concerns. I can be reached at 240-562-5622. Sincerely, Imran Shamim

Design, Simulation, and Layout of a

Serial Digital-to-Analog Converter (DAC) Array

for On-Chip, Analog Parameter Control

(July 22, 2007)

Imran Shamim

Computational Sensorimotor Systems Laboratory (CSSL)

Institute for Systems Research (ISR)

Department of Electrical and Computer Engineering (ECE)

University of Maryland, College Park

Abstract

This report presents the design, simulation, and physical layout of a low power, mixed-signal,

Digital-to-Analog Converter (DAC) array for non-volatile, on-chip, bias generation. The primary

purpose of the DAC array presented in this report is to reduce the number of chip pins used for

analog transistor biases so that more pins can be dedicated to controlling and monitoring time-

varying signals. The DAC array operates by storing a digital binary sequence into a non-volatile

memory, and then converting the digital sequence into an analog output signal for transistor

biases. Although many different DAC designs exist in the literature, the DAC used for this project

is monotonic and has a very small circuit size. To achieve monotonicity, a pMOS Ladder Network

analogous to a resistive ladder network is used. An analysis is presented for choosing the

appropriate transistor sizes and correct termination to emulate an infinite ladder network.

Computer simulation results show that a desired current scaling ratio of r = 0.5 can be achieved

with the pMOS Ladder Network such that the average ratio r of consecutive currents is 0.506 with

a standard deviation of 0.011. This report also includes the computer simulations of the entire

DAC array circuit, including its control circuitry. The DAC array requires only 6 control pins to

operate, leaving the remaining 34 pins to be dedicated to time-varying signals. Finally, this report

includes a possible implementation of the physical layout of the DAC array (given in Appendix

A), so that the circuit can be sent to a silicon foundry, such as MOSIS [1], with a minimum

amount of work.

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Table of Contents I. INTRODUCTION ...................................................................................................................... 1 II. DESIGN SPECIFICATIONS FOR DAC ARRAY ................................................................ 2

A. DIGITAL-TO-ANALOG CONVERTER (DAC).............................................................................. 2 B. MONOTONICITY ....................................................................................................................... 4 C. CIRCUIT SIZE ........................................................................................................................... 4 D. PIN REDUCTION ....................................................................................................................... 5 E. MODULARITY........................................................................................................................... 5 F. SPEED....................................................................................................................................... 5

III. IMPLEMENTATION OF DIGITAL-TO-ANALOG CONVERTER ................................ 6 A. PMOS LADDER NETWORK ...................................................................................................... 7 B. PSPICE SIMULATION OF PMOS LADDER NETWORK ............................................................... 8

IV. DAC ARRAY SYSTEM COMPONENTS........................................................................... 10 A. SHIFT REGISTERS................................................................................................................... 12 B. DIGITAL AND GATE.............................................................................................................. 14 C. PMOS LADDER NETWORK..................................................................................................... 15 D. DAC LATCHES ...................................................................................................................... 18 E. DAC ARRAY SYSTEM OPERATION SUMMARY ....................................................................... 21

V. TESTING: PSPICE SIMULATION RESULTS OF DAC ARRAY ................................... 23 TEST A: ALTERNATING BITS INPUT TO SHIFT REGISTER ............................................................ 23 TEST B: SRAM CELL DATA UPDATE ......................................................................................... 24 TEST C: SINGLE DAC SELECT ROW ACTIVATION ...................................................................... 24 TEST D: MONOTONICITY AND CURRENT LINEARITY.................................................................. 25

VI. PHYSICAL LAYOUT OF DAC ARRAY ........................................................................... 29 VII. SUMMARY AND CONCLUSION ..................................................................................... 30 VIII. REFERENCES ................................................................................................................... 31 APPENDIX A: PHYSICAL LAYOUT OF DAC ARRAY COMPONENTS.......................... 32

A. DAC LATCH .......................................................................................................................... 32 B. SHIFT REGISTER..................................................................................................................... 33 C. PMOS LADDER LEG .............................................................................................................. 34 E. DAC ARRAY (WITH 14-BIT PRECISION AND 4 ROWS) ............................................................. 35

APPENDIX B: RESISTIVE LADDER NETWORK THEORY.............................................. 36

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I. Introduction Imran Shamim

I. Introduction

In the design of many analog VLSI circuits, pin limitations are always a problem. For

example, the custom VLSI circuits designed in the Computational Sensorimotor Systems

Laboratory (CSSL – University of Maryland) use a Dual In-line Package (DIP) consisting of two

rows of twenty pins (total of forty pins) protruding from either side of the DIP. These pins are

used to provide input signals, control the circuit, monitor on-chip parameters, and read output

signals. A major issue with these chips is that almost half of the forty pins are used to supply

constant transistor bias voltages. These bias voltages are usually determined at the beginning of an

experiment and are seldom changed while the chip is being tested or used. The large number of

these bias signals limits the availability of pins that can be used to provide input, control, and

output signals. Thus, the design of the circuit under study is constrained by the number of pins

used for constant transistor bias signals.

To resolve the above-mentioned issue, I propose the design and use of a log-domain

pMOS Ladder Network that can provide digital-to-analog conversion similar to a resistive R-2R

ladder network. The pMOS Ladder Network is incorporated in a low power, mixed-signal,

Digital-to-Analog Converter (DAC) array whose primary purpose is to store a digital binary

sequence in a digital memory and convert the digital sequence into an on-chip, analog, output

signal for transistor biasing.

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II. Design Specifications for DAC Array Imran Shamim

II. Design Specifications for DAC Array

In order for the DAC array presented in this report to be useful to the researchers at

CSSL, the design of the DAC array must adhere to some specific requirements. In this section, I

discuss the requirements and specifications of the DAC array, along with the constraints and

possible tradeoffs that require consideration. The specifications discussed below were obtained

after discussions with Prof. Timothy Horiuchi, an Associate Professor at the University of

Maryland and the principal investigator of the Computational Sensorimotor Systems Laboratory

(CSSL).

A. Digital-to-Analog Converter (DAC)

To provide an array of analog bias values, the design must use a low power Digital-to-

Analog Converter (DAC) with on-chip memory. A DAC converts a binary number, i.e. a

sequence of binary digits, into an analog signal. Current scaling, voltage scaling, or charge scaling

techniques are all commonly used to carry out the digital-to-analog conversion. A current scaling

method will be used for this project since the DAC array is expected to produce currents in a range

suitable for low-power Neuromorphic applications, namely from 10pA up to 100nA. A schematic

diagram for an n + 1 bit (bn…b2b1b0, where b0 is the least significant bit) current-scaling DAC is

shown in Figure 1. The binary bit pattern bn…b2b1b0 dictates which transistors pass current (on)

and which transistors do not (off).

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Figure 1: Schematic of an n+1 bit current scaling Digital-to-Analog Converter (DAC). A reference current, i reference, splits into n+1 different currents. The ratio between consecutive currents is 1/2. The binary digits bn…b2b1b0 are used to switch the n-channel Field Effect Transistors on/off, so that the desired currents can be summed to produce the output current, i out.

In the circuit diagram of Figure 1, a reference current, i reference, is split into n + 1

different currents that are scaled by increasing powers of base-2. The output current, i out, is a

function of these scaled currents and the binary sequence bn…b2b1b0 that determines which of the

scaled currents sum to the output current. The output current, i out, is given by the expression:

)222

...2

( 021

12

0 nn bbbb

iouti ++++×= (1)

For our application, since the DAC is supposed to produce currents ranging from 10pA to 100nA,

the number of bits required to represent this range in binary is:

Number of bits required = log2 (10 4) ≈ 14 (2)

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Therefore, a DAC design similar to the one in Figure 1 with 14 bits would be necessary.

Retaining the accuracy of such a design in the face of fabrication mismatch will be a challenge.

B. Monotonicity

Monotonicity in a DAC refers to the property that as the digital input signal to the DAC

increases, the analog output conversion also increases [2]. In other words, the analog conversion

should never exhibit a decrease as the digital binary sequence increases. To achieve reliable and

predictable digital-to-analog conversion, the DAC circuit used for this project must be monotonic.

C. Circuit Size

Another major restriction in the design of the DAC array is the size of the circuit. The

DAC array will be used as an infrastructure in most of the Neuromorphic VLSI chips that are

being researched in the CSSL, therefore, a large portion of the chip area should be dedicated to

Neuromorphic VLSI circuits so the size of the DAC array needs to be relatively small. Due to this

size restriction, conventional DAC’s were not deemed appropriate for this project. Most DACs

that are commonly found in the literature are either too bulky or make abundant use of scaled

resistors for current scaling. Fabricating resistors using Integrated Circuits microfabrication

processes is a difficult and unreliable task. Therefore, the DAC array should occupy a relatively

small chip area and should not use any resistors for scaling purposes.

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D. Pin Reduction

As was stated in the previous section, the motivation for this project was the reduction in

the number of pins used for constant transistor biases. Ideally, a DAC array design that can be

controlled using a minimum number of pins is preferable so that the number of pins available for

time-varying signals can be maximized.

E. Modularity

The design of the DAC array should be modular and should give the user flexibility in

increasing the precision or range of the currents without a corresponding increase in the number of

pins used to control the DAC array. In addition, the DAC array design should allow, theoretically,

an unlimited number of transistor biases for the same number of control pins.

F. Speed

The speed of the DAC array is not at all critical for this project. The transistor biases will

be tweaked as the circuit under study is tested; however, this process will not occur continuously

or frequently. Therefore, the speed of the circuit will be traded-off by using a serially-controlled

input mechanism to reduce pin count.

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III. Implementation of Digital-to-Analog Converter Imran Shamim

III. Implementation of Digital-to-Analog Converter

Before explaining the design of the overall system, I would first like to demonstrate the

heart of the Digital-to-Analog conversion so that it is clear how the rest of the system must interact

with it. To achieve monotonic base-2 current division, such as the one shown in Figure 1, most

Digital-to-Analog Converters use the resistive R-2R ladder network shown in Figure 2. For a R-

2R ladder network, A=R, B=2R, and C=R in Figure 2. A R-2R resistive ladder network employs

scaled resistors to achieve monotonic current division so that the current flowing in each branch of

the ladder network is half of the current flowing through its neighboring branch on the left (i.e.

r = Ii+1/Ii = 1/2). An analysis of resistive ladder network theory is given in Appendix B.

Figure 2: Schematic diagram of an A-B resistive ladder network for monotonic current division. The reference current provided by the current source is split into scaled currents with a ratio of r= Ii+1/Ii. The termination resistor C is appropriately chosen to make the ladder network seem infinite. For a R-2R ladder network, A=R, B=2R, and C=R.

However, as stated previously, fabricating resistors using Integrated Circuits

microfabrication techniques is unreliable. After investigating several different options to

circumvent this issue, I found that a pMOS Ladder Network could be devised from the Bias

Current Generator circuit invented by Tobi Delbrück and André van Schaik [3]. The operation of

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the pMOS Ladder Network is exactly analogous to the operation of a resistive R-2R ladder

network, the only difference being that the resistors in the ladder network are replaced with pMOS

transistors.

A. pMOS Ladder Network

As discussed above, a resistive ladder network can be accurately mimicked by a pMOS

Ladder Network. By replacing each resistor of Figure 2 with pMOS transistors, Figure 3 depicts a

portion of the resulting pMOS Ladder Network obtained. The voltage signals TLB (Top Ladder

Bias) and BLB (Bottom Ladder Bias) will be two of the six control signals of the DAC array.

TLB BLB

Figure 3: A portion of a pMOS Ladder Network for monotonic current scaling. BLB is the transistor bias for the bottom pMOS transistors while TLB is the transistor bias for the top pMOS transistors. A reference current source of 100nA is used and the transistor sizes are chosen to give a scaling ratio of r=0.5.

The pMOS transistors used in Figure 3 were scaled according to the relationships defined by

equations (B-11) and (B-12) from Appendix B. I define r as the ratio of the currents of adjacent

7


legs (i.e. r = Ii+1/Ii). Choosing a value of B = 6μm and imposing the condition that r = 0.5 (for

binary scaling) gives:

C = A = 3 μm (3)

Therefore, all the transistors that were used in Figure 3 have a width W and length L of 3 μm.

A closer look at the circuit of Figure 3 will reveal that unitary transistors (i.e. transistors

of the same size) were used in the entire circuit. Thus instead of using a W = L = 6 μm pMOS

transistor for B, two 3 μm transistors were used in series to avoid transistor mismatch problems,

since it is known that the transistor currents do not scale well with the W and L dimensions. In

addition, note that different voltage biases are used for the top and bottom pMOS ladder

transistors (TLB and BLB in Figure 3). Although theoretically the same bias can be used, having

separate biases allows additional flexibility in adjusting the ratio r if, due to mismatching issues, r

does not equal to 0.5.

B. PSPICE Simulation of pMOS Ladder Network

The DAC array of Figure 3 was simulated in PSPICE to verify that the pMOS Ladder

Network operates like the resistive R-2R ladder. In particular, for the values chosen for A, B, C,

and r, I wish to verify that the ratio of the currents r is indeed equal to 0.5. The current values for

all the 14 vertical branches, and the corresponding values of r for neighboring branches, have been

tabulated in Table 1. As shown in Table 1, the first vertical current I0=49.43nA and the next

current I1=24.88nA. Therefore,

r = I1/I0 = 24.88nA/49.43nA = 0.503 (4)

8


As seen in Table 1, the value of r seems to be quite consistent. The average value of r is

about 0.506 with a standard deviation of only 0.011. Therefore, the pMOS Ladder Network

enabled us to circumvent the use of a resistive ladder network while maintaining monotonicity.

Although the ratio r is not exactly 0.5, it is acceptable for our purposes and should not present any

problems.

# I (nA) r 1 49.43 2 24.88 0.5033383 12.64 0.5080394 6.461 0.5111555 3.316 0.5132336 1.704 0.5138727 0.8747 0.5133228 0.4486 0.5128629 0.2297 0.512037

10 0.1175 0.51153711 0.059 0.50212812 0.0297 0.5033913 0.01465 0.49326614 0.00699 0.477133

Average STDEV 0.505793 0.010554

Table 1: PSPICE simulation results for all 14 vertical branch currents of the pMOS Ladder Network of Figure 3. The corresponding r-values for consecutive branches are also given. The average value of r is 0.506 with a standard deviation of 0.011.

9

IV. DAC Array System Components Imran Shamim

IV. DAC Array System Components

Figure 4 depicts the block diagram representation of the DAC array. Each block of Figure

4 represents a circuit that I discuss in the next few sub-sections. Fundamentally, the DAC array

consists of a cascade of shift registers, a series of “DAC Latches” (consisting of static RAM cells

with current switches), digital AND gates, and a single high-precision pMOS Ladder Network.

The operation of the DAC array of Figure 4 proceeds as follows. A binary Data sequence

is input serially through the shift registers that make up the “Data Bits” and “DAC Select” blocks,

enclosed in a solid-line and dashed-line rectangle respectively. A high-speed digital Clock is used

to propagate the binary sequence into the shift registers. The digital binary digits are then stored

into non-volatile DAC Latches using an Update control signal. The DAC Select shift registers

determine which rows are updated. Finally, the stored digital sequence is converted into an analog

voltage signal using the scaled bias currents provided by the pMOS Ladder Network. The signals

Data, Clock, and Update represent three of the six control signals of the DAC array. The

remaining three control signals appear in the pMOS Ladder Network, which will be discussed in

section IV.C.

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Clock

Data DAC Select

Update

Data Bits

Figure 4: Information flow block diagram of DAC array. A series of Data bits are input serially through a cascade of shift registers (making up the Data Bits and DAC Select blocks) using a high-speed Clock signal. The binary digits are then stored in a series of DAC Latches upon the activation of an Update control signal. Finally, the stored digital binary sequence is converted into an analog output voltage for transistor biases using the scaled currents provided by the pMOS Ladder Network. Note that Data, Clock, and Update represent three of the six control signals of the DAC array.

I will now discuss the operation of each component of Figure 4 in more detail and present

the transistor-level schematics of each component.

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A. Shift Registers

As mentioned previously, the Data Bits and DAC Select blocks of Figure 4 consist of a

cascade of shift registers. A shift register consists of two cross-coupled inverter stages separated

by pass transistors. Conventionally, shift registers utilize two non-overlapping clock signals [4, 5].

The first clock is used to shift the data from the input to the output of the first cross-coupled

inverter stage. The second clock is used to shift the data from the output of the first cross-coupled

inverter stage to the output of the second cross-coupled inverters. Thus, whenever both clock

signals go through one transition, the data shifts down the line. The primary advantage of using

shift registers is that I can input as many bits as necessary using only one input terminal and

cascading the shift registers.

Figure 5 depicts the transistor-level schematic of the shift register used for this project.

The icon on the top-right corner of Figure 5 is used as a symbol for the shift register. As seen in

Figure 5, only one clock signal is required for the design given below. Since reducing the pin

count is the prime motivation for this project, using the design of Figure 5 ensures that the pin

count of the DAC array is kept to a minimum.

Figure 5: Transistor-level schematic of the shift register, along with its symbol given on the top-right corner. The shift register consists of two cross-coupled inverter stages separated by nMOS/pMOS pass transistors. When the Clock signal goes through one transition, the data shifts down the line and moves from the input terminals (Q_in and Qbar_in) to the output terminals (Q_out and Qbar_out).

12


The inputs of the shift register in Figure 5 consist of two complementary bits, labeled as

Q_in and Qbar_in. When the Clock signal goes high, the first cross-coupled inverter stage is

powered-down and the nMOS pass transistors are turned on. The input data bits (Q_in and

Qbar_in) then hold the input and output nodes of the cross-coupled inverter at the values to be

stored. When the Clock goes low, the first cross-coupled inverter stage is powered-up (thus storing

the previously supplied input bits), the second cross-coupled inverter stage is powered-down, and

the nMOS pass transistors turn off, while the pMOS pass transistors turn on. Now, the data stored

in the first stage is fed as input to the second cross-coupled inverter stage. Finally, when the Clock

signal goes high, thus completing one full high-low-high transition, the second cross-coupled

inverter stage is powered-up, and therefore, the initial input bits (Q_in and Qbar_in) appear at the

output of the second cross-coupled inverter stage (Q_out and Qbar_out).

Figure 6 shows the voltage versus time plots for a cascade of fourteen shift registers.

Only the outputs of the first three shift registers are shown in Figure 6. As seen in Figure 6, at each

transition of the Clock signal, the input sequence moves through the registers as discussed above.

Figure 6: Voltage versus time plots for a cascade of fourteen shift registers. The outputs of only the first three shift registers are shown above, along with the Clock signal. As the Clock signal completes one transition, the input sequence moves through the shift registers.

13


Finally, I would like to mention a problem encountered during the simulation of the shift

register of Figure 5. Note that the shift register propagation should theoretically be uni-directional,

i.e. the data moves from the left to the right of Figure 5. However, while performing the

simulation of a cascade of 14 shift registers, I noticed a bi-directional movement of data which

prevented the input data to propagate through the shift registers. I believe that this problem

occurred due to the fact that my shift register design uses only one Clock signal. Typically, uni-

directionality in shift registers is guaranteed by using two non-overlapping clock signals that

independently control the data movement of each cross-coupled inverter stage inside the shift

register [4]. To solve the bi-directionality problem in my design, I made the pass transistors weak

(by increasing their lengths) and the power-up/power-down transistors strong (by decreasing their

lengths), thus enabling the cross-coupled inverters to turn on before their stored data could be

affected by neighboring cross-coupled inverter stages.

B. Digital AND Gate

Figure 7 depicts the transistor schematic of a typical CMOS two-input AND gate [4, 5].

The AND gate was designed using complementary logic to create a NAND gate, and an inverter

was included to convert the NAND operation into an AND operation. The AND gate functions as

follows. When both inputs are high, the input of the inverter is pulled to logic low (ground), and

thus the output of the inverter is at logic high (vdd). When either of the inputs is low, the pMOS

transistor pulls the input of the inverter to logic high, and thus the output of the inverter is at logic

low. Finally, I will use the icon on the top-right corner of Figure 7 to represent the AND gate.

14


Figure 7: Transistor-level schematic of CMOS AND gate, along with its symbol given on the top-right corner. The two-input AND gate consists of a cascade connection of a NAND gate followed by a digital inverter.

C. pMOS Ladder Network

Figure 8 depicts the transistor-level schematic of the pMOS Ladder Network. The icon

given on the top-right corner of Figure 8 is used as a symbol for the pMOS Ladder Network. The

pMOS Ladder Network consists of a pMOS current source (M72) that is biased to produce a

current of about 100nA. The voltage signal CSB, for Current Source Bias, is one of the DAC array

control signals. Below the pMOS current source are fourteen legs (only three legs are shown in

Figure 8). Each leg consists of three pMOS transistors and two diode-connected nMOS transistors.

The three pMOS transistors form the ladder network, while the two diode-connected nMOS

transistors are part of a cascoded current mirror that will be used to duplicate the current flowing

through the leg. Note that the first pMOS (M10) along with the two series connected pMOS

transistors (M1 and M46) form a structure similar to the R-2R ladder network discussed earlier

(M1 and M46 are in series and correspond to the series connection of two R resistors). Thus, each

15


leg of the pMOS ladder network has a current whose value is half of the value of its neighboring

leg on the left. Note that the gate-source voltage of the pMOS Ladder Network transistors can be

varied to compensate for transistor mismatches. Finally, capacitors were attached to the diode-

connected nodes of the nMOS transistors to strongly hold their voltages constant, since I will use

these voltages in the DAC Latches to duplicate the currents flowing through each leg. The current

values for all fourteen legs of the pMOS Ladder Network were presented previously in

Table 1.

Finally, as discussed in section III.A, TLB and BLB represent the bias voltage signals for

the top and bottom pMOS transistors making up the pMOS Ladder Network. Along with Data,

Clock, and Update (discussed previously), the voltages CSB, TLB, and BLB make up the 6 signals

required to control the DAC array. Each signal will utilize one pin of the DIP chip. Therefore, the

entire DAC array system requires only 6 control pins to operate.

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CSB

BLB TLB

Figure 8: Transistor-level schematic of pMOS Ladder Network, along with its symbol given on the top-right corner. The pMOS Ladder Network consists of fourteen legs (only three legs are shown above) that contain three pMOS transistors that form the ladder network, and two diode-connected nMOS transistors that are part of a cascoded current mirror for current duplication. The voltage signals CSB (Current Source Bias), TLB (Top Ladder Bias), and BLB (Bottom Ladder Bias) represent 3 of the 6 DAC array control signals.

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D. DAC Latches

Figure 9 depicts the transistor-level schematic of the DAC Latch, while the icon on the

top-right corner represents its symbol. Essentially, the DAC Latch consists of a static RAM

(sRAM) cell [4], the current source part of a cascoded current mirror, two pMOS transistors acting

as switches, and two diode-connected pMOS transistors. The voltage biases of the diode-

connected nMOS transistors from the pMOS Ladder Network (discussed in the previous

subsection) connect to the nMOS transistors (M1 and M2) of Figure 9, thus completing the nMOS

cascoded current mirror circuit.

The complementary outputs of each shift register making up the Data Bits block are fed

to the sRAM cell nodes Q and Qbar (Figure 9). The contents of the sRAM cells are updated when

the signal RowSelect goes through a low-high-low transition. The bits stored in the sRAM cells are

then used to activate/deactivate a pair of pMOS transistors that switch the current between the two

diode-connected pMOS transistors (M58 and M43).

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Static Ram Cell

Figure 9: Transistor-level schematic of DAC Latch, along with its symbol given on the top-right corner. The DAC Latch consists of fourteen branches (only one shown above) where each branch contains a static RAM (sRAM) cell, two nMOS transistors, and two pMOS switches. The sRAM cell is updated using RowSelect and the Data Bits shift register outputs. Current is then switched between the diode-connected pMOS transistors (M58 and M43). The gate/drain voltage of pMOS M58 is used as the analog transistor bias voltage (Bias_Out).

19


I define one branch of the DAC Latch as being made up of the sRAM cell, the nMOS

transistors, and the pMOS switches (excluding the two diode-connected pMOS transistors M58

and M43 enclosed in the solid rectangle). Although Figure 9 only shows one branch, each branch

is repeated fourteen times (just like the fourteen legs of the pMOS Ladder Network). The diode-

connected nMOS transistors of each leg in the pMOS Ladder Network are connected to the

corresponding nMOS transistor gates (i.e. ports 1A and 1B) in the DAC Latch branch. The data

stored in the sRAM cells determines which of the currents is added to the diode-connected pMOS

transistor (M58) that specifies the analog transistor bias voltage, Bias_Out. Note that the diode

connected pMOS transistors M58 and M43, enclosed in a solid rectangle in Figure 9, appear only

once, while the DAC Latch branch is repeated fourteen times.

I initially had only one diode-connected pMOS transistor, however, whenever the sRAM

data changed from logic-1 (vdd=5V) to logic-0 (ground=0V) or from logic-0 to logic-1, transient

capacitive coupling effects caused the drain, source, and gate voltages of the cascode current

sources to be pulled down/up to ground/vdd. Using two diode-connected pMOS transistors

eliminates these transients (since we are only switching the current between the pMOS transistors

M43 or M58) and ensures that the drain, source, and gate voltages of the cascode current sources

remain constant.

Finally, during the simulation, I also noticed that updating the sRAM cells occasionally

resulted in a destructive-read of the Data Bits shift registers. To solve the destructive-read issue, I

included digital buffers at the output of each Data Bits shift register. The digital buffers consisted

of two inverters connected in series. Note that the buffers were not shown in the block diagram of

Figure 4.

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E. DAC Array System Operation Summary

Now that I have discussed each component of the DAC array circuit, I will present a

more detailed description of the operation of the DAC array block diagram of Figure 4. A string of

binary digits represents each transistor bias. The binary sequence consists of k = 14 + ymax bits,

where ymax represents the number of transistor biases required. For simplicity, assume that ymax =

3, so that k = 17 bits. The 14 most significant bits (MSBs) are stored in the horizontal shift

registers that make up the Data Bits block, while the 3 least significant bits (LSBs) are stored in

the vertical shift registers that make up the DAC Select block. Note that the 14 MSBs constitute

the digital signal that will be stored in a single row of DAC Latches. The remaining 3 LSBs are

used to select the row (or rows) whose DAC Latches will be updated. The 17-bit sequence is input

serially, starting with the least significant bit, and a Clock signal is used to propagate the binary

sequence through the shift registers.

After the proper 17-bit sequence has been stored in the shift registers, the Update control

signal is set to high (vdd) and Boolean ANDed with the outputs of each DAC Select shift register.

Note that the Boolean ANDed output is represented as RowSelect in Figure 9. If RowSelect is

high, it enables the storage of the Data Bits binary sequence into the sRAM cells. The data stored

in each sRAM cell determines which currents are added/subtracted to produce the analog

transistor bias voltage (Bias Out in Figure 4). The same procedure can be used to update any DAC

Select row. In particular, note that the same data sequence can be stored in multiple rows at the

same time by activating the corresponding DAC Select shift registers. Although the initial phase

of loading the DAC array with data represents a slow process, this phase is required only once and

can easily be programmed using an instrumentation’s software tool such as LabView. Moreover,

note that although I only showed three rows of DAC Latches in Figure 4, the actual number of

DAC Latch rows will depend on the number of transistor biases required for a given application.

21


Notice, however, that the number of control pins does not increase with the number of additional

bias outputs.

22

V. Testing: PSPICE Simulation Results of DAC Array Imran Shamim

V. Testing: PSPICE Simulation Results of DAC Array

The circuit design of Figure 4 was tested under PSPICE to verify the operation of various

aspects of the DAC array. I will now illustrate the simulation results of these tests.

Test A: Alternating Bits Input to Shift Register

The alternating 17-bit sequence 00110011001100110 (LSB goes in first) was input to the

shift registers that make up the Data Bits and DAC Select blocks. Using an alternating bit

sequence, I ensure that each shift register goes through all possible transition phases, i.e. 0 to 0, 0

to 1, 1 to 0, and 1 to 1 transitions. Figure 10 depicts the output voltage of the first three shift

registers versus time. As seen from Figure 10, the bit sequence propagates correctly and no

glitches or erroneous transitions are observed.

Figure 10: Voltage versus time plots for Data Bits shift registers 1, 2, and 3 (the first three MSBs registers). The plot at the bottom represents the Clock signal versus time. For the plots given above, an alternating input bit sequence was used. Note that at each clock transition, the input sequences moves (shifts) through the shift registers.

23


Test B: sRAM Cell Data Update

An important feature of the DAC array is to ensure that only the sRAM cells of the

activated (i.e. given an input of logic-1 or 5V) DAC Select row are updated. In Test B, the binary

input sequence 10000000000000100 was used so that the first DAC Select row is activated (third

LSB set to 1) and so that only the sRAM Cell of DAC Latch 1 is updated (MSB set to 1). The

PSPICE simulation result of Test B is given in Figure 11, which depicts the sRAM DAC Latch 1

stored data versus time for all three rows of the DAC array. As expected, upon the activation of

the Update control signal, only the sRAM cell of DAC Latch 1 in the first row changes. The data

stored in the sRAM cell of DAC Latch 1, first row, changes from logic-0 (0V) to logic-1 (5V).

Figure 11: Voltage versus time plots of sRAM cells of DAC Latch 1 for rows 1, 2, and 3. Only row 1 is active, therefore upon the activation of the Update control signal, only the sRAM cell of DAC Latch 1, row 1, is updated while the stored value for row 2 and row 3 remains unchanged.

Test C: Single DAC Select Row Activation

Another important aspect of the DAC array operation, which is related to Test B, is to

guarantee that if one of the DAC Select rows is modified or updated, the remaining rows remain

unchanged. In Test C, the 17-bit sequence 00110011001100100 (LSB goes in first) was input to

24


the shift registers so that only the first DAC Select row is activated (i.e. given an input of logic-1

or 5V). The computer simulation results for Test C are given in Figure 12. Figure 12 depicts the

voltage versus time plots of the analog transistor bias voltages Bias Out 1, Bias Out 2, and Bias

Out 3. As shown in Figure 12, upon the activation of the Update control signal, only the voltage

level of Bias Out 1 changes, while the voltage levels for Bias Out 2 and Bias Out 3 remain

unaffected, as predicted. The voltage level of Bias Out 1 changes from 5.000V to 4.031V while

the voltage levels for the remaining rows stays constant at 5.000V.

Figure 12: Voltage versus time plots of the analog transistor bias voltages Bias Out 1, Bias Out 2, and Bias Out 3. Only row 1 is set to be active. Upon the activation of the Update control signal, only the voltage level of Bias Out 1 changes, while the voltage for Bias Out 2 and Bias Out 3 is unaffected.

Test D: Monotonicity and Current Linearity

In Section II, I stated that the most important characteristic required from the DAC array

is monotonicity. We want to guarantee that as the binary sequence in the Data Bits shift register

increases, the corresponding current at Bias Out increases linearly. For Test D, the inputs of the

three LSB shift registers were varied so that the binary sequences 000 (decimal 0) to 111 (decimal

7) are covered. The resulting current at Bias Out 1 for each binary value was recorded and is given

25


in Figure 13. In Figure 13, the top three plots represent the input signal for the LSB Data Bits shift

registers 12, 13, and 14 respectively. The plot of the Update control signal versus time is also

given. The plot at the bottom corresponds to the current at Bias Out 1.

At the first Update signal transition, all shift registers have logic-0 stored in them and the

current at Bias Out 1 is negligibly small (100e-6 pA). At the second Update signal transition, shift

registers 12 and 13 have a logic-0 stored in them, while shift register 14 stores a logic-1. Thus, the

binary number 001 (decimal 1) is stored in the shift registers, and as seen in Figure 13, the current

level for 001 is 6.96pA. A zoomed-in version of the Bias Out 1 current versus time is given in

Figure 14. Note that as the binary number stored in the LSB shift registers increases, the absolute

value of the current at Bias Out 1 also increases. To assess the linearity of the current and binary

value relationship, the stable DC value of the currents were recorded and plotted in Figure 15 for

each binary value. Figure 15 shows that the current is indeed a linear function of the binary

sequence stored in the LSB shift registers. The data points of Figure 15 were fit to a straight line

(shown as a bold line) and a correlation coefficient of R2=0.9998 was obtained, suggesting a linear

relationship between the current and binary values.

26


Figure 13: The top three plots represent the voltage versus time variation of the LSB Data Bits shift registers 12, 13, and 14 respectively. The plot of the Update control signal versus time is also given. Update is activated so that the binary sequences 000 through 111 are covered. The plot at the bottom corresponds to the current at Bias Out 1.

Figure 14: A zoomed-in version of the Bias Out 1 current versus time variation from Figure 13. Note that as the binary sequence increases, the absolute value of the current increases.

27


R2 = 0.9998

0.00E+00

1.00E+01

2.00E+01

3.00E+01

4.00E+01

5.00E+01

6.00E+01

0 2 4 6 8

Binary Value (in decimal)

Cur

rent

(in

pA)

Figure 15: Current versus binary sequence value plotted for the data obtained from Figure 14. The data points were fit to a straight line (shown in bold). The relationship between the current and binary value was found to be linear with a correlation coefficient of R2=0.9998.

28

VI. Physical Layout of DAC Array Imran Shamim

VI. Physical Layout of DAC Array

The physical layout of VLSI circuits is an art. Although there are certain rules to

minimize transistor mismatches and circuit area, there is no standard, unique, way of

implementing a circuit schematic into a physical layout. In Appendix A, I have given a possible

implementation of the physical layout of the DAC array. I would like to emphasize that the

physical implementation given in Appendix A is not the most optimized representation of the

DAC array. With a lot of time and careful thought, a smaller physical layout for the DAC array

could be obtained. The physical layout shown in Appendix A is given for the sake of completeness

so that the DAC array circuit could be sent quickly to an Integrated Circuits fabrication foundry,

such as MOSIS, with a minimum amount of work.

One important point that I would like to mention is that transistor matching is crucial for

the proper operation of the pMOS Ladder Network. The pMOS Ladder Network was made by

replacing each resistor R in the resistive ladder network with a pMOS transistor. Obtaining

identical transistors is impossible due to process variations in Integrated Circuit fabrication

technology. However, using large transistors can reduce transistor mismatch. Therefore, the

pMOS Ladder Network was created using large, i.e. W=20λ and L=20λ, transistors. In addition to

using large transistor sizes, dummy stages were used at the left of the first pMOS Ladder Network

leg, and at the right of the last pMOS Ladder Network leg. The dummy stage ensures that the

physical environment around each transistor is the same. Besides the first and last legs of the

pMOS Ladder Network, each leg is surrounded by a leg on its left and its right. Therefore, to

match each transistor, it is essential to not only match the sizes, but also the physical environment

surrounding each transistor. Dummy stages were used only for the pMOS Ladder Network, which

is the only high-precision component of the DAC array.

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VII. Summary and Conclusion Imran Shamim

VII. Summary and Conclusion

This report presented the design, simulation, and physical layout of a serially-controlled

low power, mixed-signal, Digital-to-Analog Converter array for non-volatile, on-chip, bias

generation. The DAC array stores a binary sequence into a non-volatile memory and upon

activation of a control signal, converts the digital binary sequence into an analog output for

transistor biases. The schematics and computer simulation of the DAC array components and the

entire DAC array system were presented.

The DAC array presented here can be used in virtually all the VLSI chips being

researched in the CSSL and other circuit design research laboratories. The DAC array allows an

unlimited number of transistor biases using only 6 control pins. The remaining 34 pins of a 40-pin

DIP can be used to control and monitor time-varying signals, thus giving the circuit researchers

complete freedom in designing their circuits and eliminating the constraint imposed by the limited

availability of pins.

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VIII. References Imran Shamim

VIII. References

[1] MOSIS Integrated Circuit Fabrication Service. 2007. 1 February 2007 <www.mosis.org>.

[2] Phillip E. Allen, and Douglas R. Holberg. CMOS Analog Circuit Design. New York: Oxford

University Press, 2002.

[3] Tobi Delbrück and André van Schaik. “Bias Current Generators with Wide Dynamic Range.”

Analog Integrated Circuits and Signal Processing 43 (2005): 247–268.

[4] Adel Sedra, and Kenneth Smith. Microelectronic Circuits. New York: Oxford University

Press, 2004.

[5] Jacob Baker. CMOS: Circuit Design, Layout, and Simulation. New Jersey: Wiley-Interscience,

2005.

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Appendix A: Physical Layout of DAC Array Components Imran Shamim

Appendix A: Physical Layout of DAC Array Components

A. DAC Latch

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B. Shift Register

33


C. pMOS Ladder Leg

34


E. DAC Array (with 14-bit precision and 4 rows)

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Appendix B: Resistive Ladder Network Theory Imran Shamim

Appendix B: Resistive Ladder Network Theory

The simplest way of obtaining monotonic current division is by using a resistive ladder

network, such as that shown in Figure B1. I will now show a derivation for the values of the

resistors C and A given a ratio r (such that 0 < r < 1) and a value for the resistor B.

For the resistive ladder network of Figure B1, the termination resistor C must be properly

chosen so that the ladder appears to be infinite. Mathematically, this condition is expressed as:

(A+C)||B = C (B-1)

Using the notation of Figure B1, I define r as:

r = Ii+1/Ii (B-2)

Figure B1: Schematic diagram of an A-B resistive ladder network for monotonic current division. The reference current provided by the current source is split into scaled currents with a ratio of r=Ii+1/Ii. The termination resistor C is appropriately chosen to make the ladder network seems infinite.

36

Appendix B: Resistive Ladder Network Theory Imran Shamim

Therefore, using (B-1) and Ohm’s law:

Vi = ItC = IiB (B-3)

Vi+1 = It+1C = Ii+1B (B-4)

In addition, by using conservation of charge:

It+1= It - Ii (B-5)

From (B-3) and (B-4):

Ii = It(C/B) (B-6)

Ii+1 = It+1(C/B) (B-7)

Now using (B-7) on (B-5):

It+1= It - Ii = It(1-C/B) (B-8)

Therefore (B-7) becomes:

Ii+1 = It(1-C/B)C/B (B-9)

Using (B-2), (B-6), and (B-9) we find that:

r = Ii+1/Ii = (1-C/B) (B-10)

Finally using (B-1) and (B-10) to solve for A and C (given r and B), we find that:

C = B (1-r) (B-11)

A = B (1-r)2 / r (B-12)

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Design, Simulation, and Layout of a Serial Digital-to-Analog Converter (DAC) Array