Design Voltage Margining Circuit for UCD90xxx Power ... · PWM,1 3 C1 C1 3 4 3 4 C1 V R Z V = R R + R +R Z C1 R4 R3 Margin PWM out,step CLK PWM out,max out,min V F F = V -V Design

1SLVA845–October 2016Submit Documentation Feedback

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Design Voltage Margining Circuit for UCD90xxx Power Sequencer andSystem Manager

Application ReportSLVA845–October 2016

Design Voltage Margining Circuit for UCD90xxx PowerSequencer and System Manager

Zhiyuan Hu, Luke Lu

ABSTRACTThe UCD90xxx power sequencer and system manager provides margining function to trim output voltageof analog point-of-load converters. This application report discusses design considerations and provides adesign procedure of the margining circuit.

Contents1 Introduction ................................................................................................................... 22 Design Considerations ...................................................................................................... 23 Design Procedure .......................................................................................................... 104 Fusion GUI Configuration ................................................................................................. 135 Debugging Hints............................................................................................................ 166 Conclusion .................................................................................................................. 16

List of Figures

1 Closed-Loop Margining Circuit............................................................................................. 22 Equivalent Circuit at Maximum and Minimum Vout ....................................................................... 23 Equivalent Circuit of RC Filter.............................................................................................. 44 Block Diagram Without Margining Circuit................................................................................. 55 Block Diagram With Margining Circuit .................................................................................... 66 Example of VC1 to Vout Attenuation by Loop Response (Type-2)....................................................... 67 Block Diagram With Margining Circuit (Type-3 Compensator) ........................................................ 78 Equivalent Circuit in Normal Operation ................................................................................... 89 Pin Assignment Window .................................................................................................. 1310 Trim/Margining Configuration Window .................................................................................. 1411 OPERATION Command Window ........................................................................................ 1512 GPI Configuration Window................................................................................................ 1513 PMBus Log Window ....................................................................................................... 16

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Power Supply

R2

R1

Vout

FB

R3 R4

VOH or VOL

VFB

Power Stage

R2 C1

R1

VoutVin

ControllerVFB

R3 R4

UCD90xxx

Margin PWM

MON

Introduction www.ti.com

2 SLVA845–October 2016Submit Documentation Feedback



1 IntroductionThe UCD90xxx power sequencer and system manager provides margining function to trim output voltageof analog point-of-load converters. This function can be used to facilitate voltage corner testing, whichverifies the robustness of a product, as well as to actively trim output voltages in normal operation mode.

The UCD90xxx devices use digital pulse width modulator (DPWM) to implement the margining function. Aclosed-loop margining circuit is illustrated in Figure 1. The UCD90xxx device outputs a pulse widthmodulation (PWM) signal, which is filtered by an RC filter formed by R4 and C1. The DC component of C1voltage is controlled by the PWM duty cycle. The voltage on C1 sources or sinks current from the FB nodethrough R3 and, thus, changes the output voltage. The UCD90xxx compares the rail voltage and thetargeted value and slowly adjusts the duty cycle. The margin control loop is so slow that it does not affectthe power converter’s feedback loop.

Figure 1. Closed-Loop Margining Circuit

This application report discusses the selection of the margin DPWM frequency, initial duty cycle, andcomponent values of R3, R4, and C1. An Excel worksheet is available to carry out the calculationdiscussed in this application report (UCD90xxx Voltage Margining Circuit Design Tool).

2 Design Considerations

2.1 Resistor Values and Regulation RangeThe maximum and minimum Vout occurs when the margin PWM duty cycle is 0 and 100%, respectively.The equivalent circuit is shown in Figure 2. The minimum and maximum output voltages with marginingcircuit are derived in Equation 2 and Equation 3, respectively.

Figure 2. Equivalent Circuit at Maximum and Minimum Vout

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http://www.ti.com/lit/pdf/SLVC676

out,max out,min out,max out,minout,step PWM

CLK

V - V V - VV = = F

n F

CLK

PWM

Fn =

F

� �1 ref OL

3 4out,high out,nom

R V - VR + R =

V - V

� �1 OH ref

3 4out,nom out,low

R V - VR + R =

V - V

ref OLout,max out,nom 1

3 4

V - VV = V + R ×

R + R

§ ·¨ ¸¨ ¸© ¹

ref OHout,min out,nom 1

3 4

V - VV = V + R ×

R + R

§ ·¨ ¸¨ ¸© ¹

1 2out,nom ref

2

R + RV = V ×

R

www.ti.com Design Considerations




(1)

(2)

(3)

Where:• Vout,nom is the nominal output voltage determined by resistor divider values• VOH is the PWM high-level output voltage• VOL is the PWM low-level output voltage• Vref is the power supply’s reference voltage

Based on Equation 2 and Equation 3, the sum of R3 and R4 is determined by the desired margin low ormargin high values, whichever results in a smaller R3+R4 value. Equation 4 and Equation 5 can be usedto calculate R3+R4 value for margin low and margin high scenarios, respectively.

(4)

(5)

The above equations still hold true when R2 is not present in some applications.

2.2 DPWM Frequency and Vout ResolutionThe DPWM signals are generated from an internal clock. The number of quantization steps in eachDPWM period is inversely proportional to the DPWM frequency. The relation is shown in Equation 6.

(6)

Where:• n is the number of quantization steps in a DPWM period• FCLK is the internal clock frequency• FPWM is the DPWM frequency

The DPWM duty cycle can only have integer number of quantization steps. As a result, the Vout controlledby the margin DPWM has finite resolution. The Vout step size equals to the full voltage margining rangedivided by the number of quantization steps in a period, as shown in Equation 7.

(7)

Apparently, the Vout step size is proportional to the Vout margining range and the DPWM frequency.

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� �PWM,1 3 C1

C1

3 4 3 4 C1

V R ZV =

R R + R + R Z

C1

R4

R3

Margin PWM

out,step CLKPWM

out,max out,min

V FF =

V - V

Design Considerations www.ti.com




In margin mode and Active Trim mode, the UCD90xxx controls Vout with a very slow feedback loop. Theloop is executed approximately once every 500 µs. If the sampled Vout is unequal to the target value, theDPWM duty cycle will change by one quantization step towards the direction to minimize the error.Because Vout has voltage ripple and the analog-to-digital converter (ADC) has sampling noise, it can beexpected that the DPWM duty cycle will fluctuate by ±1 least significant bit (LSB) during margining andActive Trim operations, which will cause Vout to slightly fluctuate around the targeted margin or trim value.

To minimize the voltage fluctuation, Vout step size should be reduced in order for the Vout fluctuation, due tothe ±1 LSB duty cycle fluctuation, is acceptable. According to Equation 7, the DPWM frequency can bereduced to achieve this goal. The optimal DPWM frequency is calculated by making Vout,step an acceptablevalue then deriving the switching frequency accordingly. For example, Vout,step can be arbitrarily set to 1mV, then the margin DPWM frequency can be determined by Equation 8.

(8)

2.3 Margin DPWM Output FilteringThe square-wave signal from the margin DPWM should be sufficiently filtered so only the DC componentshows effect on Vout.

There are two filtering mechanisms:1. RC filter in the margining circuit2. Loop response of the power supply

2.3.1 Attenuation by RC FilterAs shown in Figure 1, the RC filter is formed by R4 and C1. The voltage of C1 is connected to FB nodethrough R3. Assuming the error amplifier is ideal, the FB node voltage is a DC voltage equal to thereference voltage. For AC analysis, the equivalent circuit of the RC filter can be drawn as in Figure 3.

Figure 3. Equivalent Circuit of RC Filter

The amplitude of the AC voltage on C1 can be estimated by Equation 9. The lower case v denotes ACvoltage component.

(9)

Where:• ZC1 is the C1 impedance at the DPWM frequency• vPWM,1 is the amplitude of the fundamental harmonic of the DPWM square-wave output

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PowerSupply

R2

R1

FB

A

G(s)

ÖVOUT(S)

VA(S)Ö

� ��

� �out

A

Öv sG s =

Öv s

� � � �OH OL

PWM,1

2 V - V sin �'

V =�





Only the fundamental harmonic is considered for simplicity. As shown in Equation 10, higher-orderharmonics have more attenuation by the power supply’s loop response and are, thus, negligible. ThevPWM,1 is determined by Fourier series:

(10)

Where:• D is the duty cycle of the margin DPWM

The biggest vPWM,1 value occurs at D=0.5.

2.3.2 Attenuation by Loop ResponseThe voltage ripple on C1 is further attenuated by the power supply’s loop response. The following analysisshows how to estimate the attenuation.

First consider a power supply without the margining circuit. If there is a break in the loop at point A, thecompensated open-loop transfer function, G(s), is defined in Figure 4 and Equation 11.

(11)

G(s) includes both power stage and compensator’s transfer functions, which can be obtained frommodeling or circuit measurement. G(s) should be available information to power supply designers.

Figure 4. Block Diagram Without Margining Circuit

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Gai

n /

dB

-140

-120

-100

-80

-60

-40

-20

0

20

40

VC1 to Vout when R3=R1

VC1 to Vout when R3=10R1

Frequency / Hertz

10 20 40 100 200 400 1k 2k 4k 10k 20k 40k 100k 400k 1M

Margin PWM frequency range

Open loop gain of the original power

supply (with Type-2 compensator)

� ��

� �

� �

� �out 1

C1 3

Öv s R G sT s = =

Öv s R 1- G s

SupplyPower

R2

R1

FB

R3

ÖVOUT(S)

ÖVC1(S)





Next consider a power supply with the margining circuit, as shown in Figure 5. The power supply's transferfunction from VC1 to Vout is in Equation 12.

Figure 5. Block Diagram With Margining Circuit

(12)

Based on Equation 12, it can be predicted that when R1=R3, the transfer function from VC1 to Vout isidentical to the closed-loop transfer function of the original power supply. Figure 6 provides simulationresults to verify the above conclusion supply: below the cross-over frequency, the closed-loop gain is 0dB,and above the cross-over frequency, the closed-loop gain is equal to open-loop gain.

Figure 6. Example of VC1 to Vout Attenuation by Loop Response (Type-2)

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alias SW PWMF = ±k×F ±F ,k =1,2,3...

� ��

� � � ��

1 PWMout PWM PWM

3C1 PWM PWM

Z 2�)Öv 2�) * ��)=

RÖv 2�) ��* ��)

� �1 a

PWM a

1 PWM

1 aPWM a

1R R +

j2�) &Z 2�)

1R + R +

j2�) &

§ ·¨ ¸¨ ¸© ¹

Ra

Ca

Z1

PowerSupply

R2

FB

R3Ö

VOUT(S)Ö

R1

VC1(S)

� ��

� ��

out PWM PWM1

3C1 PWM PWM

Öv 2�) * ��)R=

RÖv 2�) ��* ��)





The power supply’s loop gain at the margin DPWM frequency can be observed on the Bode plot,estimated from cross-over frequency, or calculated from the mathematical model. The voltage gain fromVC1 to Vout at the margin DPWM frequency can be calculated from Equation 13.

(13)

For the Type-3 compensator, there is an R-C network in parallel with R1. In this case, Z1 should be usedto replace R1 as shown in Figure 7 and Equation 14.

Figure 7. Block Diagram With Margining Circuit (Type-3 Compensator)

(14)

For simplicity, the Type-3 compensator can also use Equation 13 instead of Equation 14.

In conclusion, if the margin DPWM frequency is above the loop cross-over frequency, which is usually thecase, the compensator will provide significant attenuation. A large R3 value compared to R1 (or Z1) alsoprovides attenuation. The C1 value should be selected to provide additional attenuation in order toeliminate Vout voltage ripple at the margin DPWM frequency.

For switch mode power supply only (not applicable to LDO), an additional frequency component thatrequires attenuation is the alias generated by the power supply switching frequency (Fsw) and the marginDPWM frequency (FPWM). Due to the sampling nature of the PWM, the VC1 ripple is injected intocompensated error signal, which is then sampled at the PWM fall edges. If the VC1 ripple frequency isgreater than ½ Fsw, alias frequencies will occur at output

The alias frequencies can be calculated by Equation 15.

(15)

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Power Stage

R2 C1

R1

VOUTVin

VFBR3

UCD90xxx

Margin

PWMMON

+ Vref

Controller

EA

PWM SW

1F = m + ×F ,m = 0,1,2...

2§ ·¨ ¸© ¹

� ��

PWM

SW

a PWM SW PWM SW

Fm = floor

F

F = min F - m×F , F - m +1 ×F

§ ·¨ ¸¨ ¸© ¹





The lowest alias frequency (Fa) occurs in the first Nyquist zone (≤ ½ Fsw), which is the most difficult tofilter. Fa frequency can be calculated by Equation 16.

(16)

The margin DPWM frequency should be selected such that Fa is at its highest possible value (½ Fsw).

(17)

2.4 Impact on Power Supply Normal OperationWhen not in margin or Active Trim mode, the margin DPWM pin is in high-impedance state. The branchformed by R3 and C1 is in parallel with R2, as shown in Figure 8.

Figure 8. Equivalent Circuit in Normal Operation

Assuming the error amplifier in the controller is an ideal op-amp, the VFB is a DC voltage equal to thereference voltage. In this case, there is no small-signal current flowing through the R3-C1 branch, thus, ithas no impact to the power supply’s loop transfer function.

Real-world error amplifier has limited gain-bandwidth product, but the op-amp gain at the cross-overfrequency should be still greater than 100. Consider the case where there is a voltage disturbance on Voutat the cross-over frequency. Because the closed-loop gain is 1 at cross-over frequency and the erroramplifier still has a gain of 100, the voltage disturbance on VFB is about 1/100 of that on Vout. AssumingR3=10·R1, the small-signal current flowing through R3 is only 0.1% of that flowing through R1. Therefore,the impact of the R3-C1 branch on the power supply’s transfer function is negligible.

2.5 Impact on Power Supply Soft StartDuring closed-loop soft start, the FB node voltage ramps up with the reference voltage. C1 voltage isinitially zero. Current must flow from FB node to C1 to charge the capacitor. The additional charge currentto C1 is from Vout flowing through R1. Therefore, when C1 is charging, Vout will be higher than thereference voltage determined value. At the end of the soft start ramp, there is a possibility to overshoot.

In reality, the actual Vout ramp lags VFB ramp because the system has a steady state error for a slopeinput. At the end of VFB ramp, The Vout lag will cancel the overshoot. The VFB ramp is often flattenednear the end of the ramp, which reduces the current in R3 and thus reduces the overshoot. Therefore, theactual overshoot is often invisible. The following simplified math model is for sanity check and forreference only.

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ref OLinit

OH OL

V - VD =

V - V

� �rise-t

ref R3×C1out R3 rise 1 1 1

rise

Vû9 , W × R = × R ×C × 1- e

t

§ ·¨ ¸¨ ¸© ¹

� � � �-t

R3xC1R3 R3I t = I × 1- e

§ ·¨ ¸f¨ ¸© ¹

� � refR3 1

rise

VI = ×C

tf

� � refFB

rise

VV t = × t

t





Assuming the soft start ramp is strictly linear, the VFB can be expressed as a function of time.

(18)

Where:• trise is the soft start rise time

If the ramp is infinitely long, the R3 current will achieve a steady state.

(19)

The R3 current as a function of time can then be derived as:

(20)

At the end of soft start ramp, the voltage overshoot caused by C1 charging is:

(21)

Equation 21 can be used to check overshoot voltage at the end of soft start ramp. The actual overshootamount is often ~50-mV smaller than predicted because the soft start ramp is often flattened andgradually merges into steady state near the end. This calculation is for information only. If the overshoot istoo large, the C1 value needs to be decreased.

To minimize C1 value needed:1. Make R3=R4 (R3+R4 is fixed, which is discussed in Section 2.1).2. Reduce the Margin High/Low range so that the larger R3+R4 value can be used.3. Increase the R1 value so that larger R3+R4 value can be used.4. Allow a higher ripple at Vout.Alternately, increasing soft start rise time can also reduce overshoot.

2.6 Initial Duty CycleThe UCD90xxx adjusts the margin DPWM duty cycle by one LSB every 500 µs. If the initial duty cyclesetting is far from the steady state value, it will cause sudden Vout change when margining and Active Trimfunction is activated.

The suggested initial duty cycle is calculated by Equation 22. The margin DPWM’s initial DC outputvoltage equals to the reference voltage, which will allow the UCD90xxx to gradually bring Vout to thetargeted Margin High/Low level.

(22)

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ref OHout,min out,nom 1

3 4

V - VV = V + R ×

R + R

§ ·¨ ¸¨ ¸© ¹

out,step CLKPWM,max

out,max out,min

V FF =

V - V

� ��

1 ref OL

3 4

out,high out,nom

R V - VR = R =

2 V - V

� ��

1 OH ref

3 4

out,nom out,low

R V - VR = R =

2 V - V

out,nom out,lowDPWM

1

V - VI =

R

out,high out,nomDPWM

1

V - VI =

R

ref OLinit

OH OL

V - VD =

V - V

1 2out,nom ref

2

R + RV = V ×

R

Design Procedure www.ti.com




3 Design ProcedureStep 1: Use Equation 23 to calculate nominal output voltage. Vref is the reference voltage of the powersupply controller.

(23)

Step 2: Use Equation 24 to calculate initial margin DPWM duty cycle. VOH and VOL are output high andoutput low voltage levels of DPWM pins. Typical values are VOH = 3.2 V and VOL = 0 V.

(24)

Step 3: Use Equation 25 and Equation 26 to estimate the margin DPWM pin current. Vout,low is the margin-low output voltage, which must be less than Vout,nom. Vout,high is the margin-high output voltage, which mustbe greater than Vout,nom.If the higher current value of the two is greater than 1 mA, increase the R1 and R2 values. In general,larger R1 and R2 values are preferred to reduce margin DPWM pin’s current.

(25)

(26)

Step 4: Use Equation 27 and Equation 28 to calculate R3 and R4 values. The smaller value of the twoshould be selected. The actual resistor value must be equal to or less than the calculated value.

(27)

(28)

Step 5: Use Equation 29 to calculate maximum margin DPWM frequency that provides sufficient Voutresolution.

(29)

Vout,step is the allowed Vout fluctuation in margining and Active Trim mode. Larger Vout,step allows for highermargin DPWM frequency. A good starting point is Vout,step = 0.1% Vout,nom.

Vout,min and Vout,max are the output voltage levels when margin DPWM is at 100% and 0% duty cycle,respectively. The voltage levels can be calculated from Equation 30 and Equation 31.

(30)

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� � � �1 1VC1_to_Vout a OL a

3 3

R RGain 2�) PLQ �*DLQ ��)

R R

§ ·¨ ¸¨ ¸© ¹

� � SWOL a

a

0.2FGain 2�)

F

� ��

PWM

SW

a PWM SW PWM SW

Fn = floor

F

F = min F - n×F , F - n +1 ×F

§ ·¨ ¸¨ ¸© ¹

PWM,max

SW

PWM PWM,max SW

Fm = max 1, round

F

1F = min F , m - ×F

2

§ ·§ ·¨ ¸¨ ¸¨ ¸¨ ¸

© ¹© ¹

§ ·§ ·¨ ¸¨ ¸© ¹© ¹

ref OLout,max out,nom 1

3 4

V - VV = V + R ×

R + R

§ ·¨ ¸¨ ¸© ¹

www.ti.com Design Procedure




(31)

FCLK is the internal clock frequency of UCD90xxx devices:1. Use 80 MHz for UCD90240 and UCD90320’s Margin pins.2. Use 500 MHz for UCD9090(A), UCD90120(A), UCD90124(A), and UCD90160(A)’s FPWM pins.3. Use 15.625 MHz for UCD9090(A), UCD90120(A), UCD90124(A), and UCD90160(A)’s PWM3 and

PWM4 pins.

Step 6: Use Equation 32 to calculate optimal margin DPWM frequency, FPWM. FSW is power supply’sswitching frequency.

(32)

Step 7: Use Equation 33 to calculate the lowest alias frequency, Fa.

(33)

Step 8: Use Equation 34 to estimate switch mode power supply’s open loop gain at frequency Fa,assuming:(a) The loop bandwidth is approximately 20% of switching frequency(b) The gain slope is -20dB/decade between crossover frequency and Fa

(34)

This value can be also obtained from experimental result.

For the margining LDO output, use 1 for this value.

Step 9: Use Equation 35 to estimate closed-loop gain from VC1 ripple to Vout.

(35)

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rise-tref R3×C1

out 1 1rise

Vû9 ×R ×C × 1-e

t

§ ·¨ ¸¨ ¸© ¹

� �22 2

3 RC 3 4

1PWM RC 3 4

R - Gain R + RC =

2�) *DLQ 5 5

� �total

RC

VC1_to_Vout a

GainGain =

Gain 2�)

� �total out,step

OH OL

�Gain = V ×

2 V - V

� ��

2 2 2 2a a a

1 a 1 22 2 2a a 1 a

4C F � 5 ��Z 2�) 5

4C F � 5 �5 ��

� ��

� �� 1 a 1 a

VC1_to_Vout a OL a3 3

Z 2�) = ��)Gain 2�) PLQ �*DLQ ��)

R R

§ ·¨ ¸¨ ¸© ¹

Design Procedure www.ti.com




(Optional for Type-3 compensator)

(36)

Where:• Z1 is defined in Figure 7.

(37)

For simplicity, Equation 35 can be used for Type-3 compensator.

Step 10: Use Equation 38 to calculate the required total gain so the margin DPWM square-wave signal isattenuated to an acceptable Vout ripple, that is, Vout,step defined in Step 5. This step takes into account theworst case scenario where the margin DPWM duty cycle is 50%.

(38)

Step 11: Use Equation 39 to calculate the gain required to attenuate the margin DPWM square wave tothe required VC1 ripple.

(39)

Step 12: Use Equation 40 to calculate the C1 value. If GainRC is greater than R4/(R3+R4), C1 is notneeded.

(40)

Use Equation 41 to predict overshoot at the end of soft start ramp. trise is the soft start rise time.

The actual overshoot is often ~50-mV smaller than predicted because the soft start ramp is often flattenedand gradually merges into steady state near the end. This calculation is for information only.

If the overshoot is too large, the following measures can be used:1. Reduce unnecessarily wide Margin High/Low range to reduce the C1 value.2. Increase the allowed Vout ripple so as to increase DPWM frequency and, thus, decreases the C1 value.3. Increase the soft start rise time to reduce overshoot directly.4. Increase the R1 value to reduce C1 value needed for filtering.

(41)

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www.ti.com Fusion GUI Configuration




4 Fusion GUI ConfigurationThe margin DPWM setting can be configured in the Fusion Digital Power™ Designer (referred to asFusion GUI).

The margin DPWM pin assignment can be configured in the pin assignment window. Click the buttonunder Trim/Margin PWM column to assign a FPWM or PWM pin.

For UCD9090(A), UCD90120(A), UCD90124(A), and UCD90160(A), FPWM pins have higher resolutionthan PWM pins, so FPWM pings are preferred for the margining and trimming purpose. The PWM1 andPWM2 pins have fixed low switching frequency and are, thus, not recommended for margining function.

For UCD90240 and UCD90320, all Margin pins can be used for margining function.

Figure 9. Pin Assignment Window

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Fusion GUI Configuration www.ti.com




Once a margin DPWM pin is assigned, click the Configure button next to it to configure frequency, initialduty cycle, margin mode, and so on.

Figure 10. Trim/Margining Configuration Window

Upon completing the configuration, click Write to Hardware button on the left side of the Fusion GUI toconfirm the changes.

The margining function can be enabled by sending OPERATION command or by toggling general purposeinput (GPI).

The OPERATION command can be sent from Fusion GUI under Monitor page. Users can click a button inGUI to start margining a rail.

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www.ti.com Fusion GUI Configuration




Figure 11. OPERATION Command Window

Users can also assign two GPI pins to control the margining function. In the GPI configuration window, aGPI pin can be configured to enable margining for all rails or control the margining direction of all rails.

Figure 12. GPI Configuration Window

The Fusion GUI sends configuration data to UCD90xxx devices through PMBus commands. Users canalso use their own PMBus hosts to send PMBus commands. The related PMBus commands used by theFusion GUI are shown in the PMBus Log window on the lower-right corner of the Fusion GUI. Thisinformation can help users compose PMBus command scripts to configure UCD90xxx devices. Thedetailed explanation of PMBus commands can be found in UCD90xxx Sequencer and System HealthController PMBus Command Reference User's Guide.

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http://www.ti.com/lit/pdf/SLVU352

http://www.ti.com/lit/pdf/SLVU352

Debugging Hints www.ti.com




Figure 13. PMBus Log Window

5 Debugging Hints1. The margining function is not working.

Suggestion:(a) Check the margin DPWM pin output. If the pin outputs a PWM signal, 3.3 V (100% duty cycle), or 0

V (0% duty cycle), the margining function is working. In that case, check for problems in theexternal circuit. However, if the pin’s voltage is POL’s reference voltage, the margining function isnot enabled and the pin is in Hi-Z state. In that case, check the device configuration.

(b) Margining can only be enabled after the rail rises above Power Good On threshold at least onceafter the rail is enabled. If the rail output voltage stays below Power Good On, the marginingfunction will not start working.

(c) The rail may be shut down if the Margin High/Low threshold exceeds over voltage (OV) or undervoltage (UV) thresholds. The UCD90xxx device allows users to override the fault actions duringmargining (see Figure 11).

2. The margining function is working, but the rail voltage cannot reach configured Margin High/Low levels.Suggestion:The maximum and minimum Margin High/Low voltage is limited by the R3+R4 value (refer toSection 2.1). Reduce R3 and/or R4 value to increase margin voltage range.

3. When margining function is enabled, the output voltage ripple is too large.Suggestion:Check ripple frequency.(a) If the output voltage changes every 500 µs, the ripple is due to limited resolution (refer to

Section 2.2). In that case, use the Excel worksheet to calculate optimal R3 and R4 value andreduce margin DPWM frequency.

(b) If the output voltage is at the margin DPWM frequency or its alias frequency, the ripple is due toinsufficient attenuation (refer to Section 2.3). In that case, use the Excel worksheet to calculateoptimal R3 and R4 value and optimal margin DPWM frequency and increase C1 value.

4. There is a sudden output voltage drop or surge when margining function is enabled.Suggestion:The initial duty cycle is not properly configured (refer to Section 2.6). Use the Excel worksheet tocalculate optimal initial duty cycle and set the configuration accordingly (see Figure 10).

6 ConclusionThe UCD90xxx devices provide functions to closed-loop margining and trim power supply output voltagewith high accuracy. This application report discussed design considerations and provided a designprocedure to achieve optimal design.

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IMPORTANT NOTICE

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Documents

Design Voltage Margining Circuit for UCD90xxx Power ... · PWM,1 3 C1 C1 3 4 3 4 C1 V R Z V = R R + R +R Z C1 R4 R3 Margin PWM out,step CLK PWM out,max out,min V F F = V -V Design