1© 2017 The MathWorks, Inc.

Developing and Implementing

Software Defined Radio Applications

Stephan van Beek Technical Manager

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Introduction to the Speaker

Stephan van Beek

BSc in Electronics

Field Engineer at Anorad Europe BV

with a focus on motion control systems

Application Engineer at Océ Technologies BV (A Canon Company)

electronic design methodology group focusing on optimizing FPGA design-flows

Pan-EMEA Application Engineer / Technical Manager at MathWorks Netherlands

working with customers to optimize their FPGA/ASIC/SoC design-flows

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What is a Software Defined Radio system?

Analog Front

End

Filters, Mixer,

ADC/DAC

Tunable RF Card FPGA / SoC Board Host computer

Commercial-off-the-shelf hardware

Baseband

Processing

Modulation

Digital Front End

Digital Filters,

Sample Rate

Conversion

Radio in which some or all of the physical layer functions are software defined

A radio is a device that wirelessly transmits or receives signals in the radio

frequency (RF) spectrum to facilitate the transfer of information.

SDR enables: adding new functionality, remote upgrades, re-use of algorithms

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Why is streamlining the SDR design flow so important?

Radios are everywhere

New standards emerging to enable

new applications

Need a flexible platform for

rapid innovation!

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FPGA / Board

Design

Linux Driver

Development

Communications

Theory

Digital Signal

ProcessingRF Architecture

Challenges in SDR Design and Implementation

• Real scenarios - variety of waveforms

• Requires a wide range of skill sets

• Different working views/environments

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Test with Hardware and Over-the-Air Signals

Test your algorithms with real signals and scenarios

– Connectivity with instruments or SDR platforms

– Deployment to SDR platforms, or to your own hardware

RF Signal Generator

Spectrum Analyzer

Zynq Radio SDR

USRP SDR

Use Supported Hardware…

…Or Your Own Hardware

HDL Coder and Embedded

Coder to implement your design

on FPGA and DSP platformsEricsson paper: Radio Testbed Design Using HDL Coder:http://www.mathworks.com/videos/radio-testbed-design-using-hdl-coder-92636.html

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Ideal Design Environment Goal

Common design environment across multiple teams to streamline development

Target off-the-shelf hardware for prototype development – with a path to

production

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ChallengeDevelop a military standard SDR waveform for satellite

communications

SolutionUse Simulink to rapidly design, debug, and automatically

generate code for an SDR signal processing chain

Results Project development time reduced by 80%

Problems found and eliminated faster

Clocking and interfacing simplified

“Using Simulink we designed

and developed the signal

processing chain of the SDR

and achieved a 10-to-1

reduction in development time.”

Dr. David Haessig

BAE Systems

Custom board used in the

traditional design workflow.

BAE Systems Achieves 80% Reduction in Software-

Defined Radio Development Time

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BAE Systems Achieves 80% Reduction in Software-

Defined Radio Development Time

“It took 645 hours for an engineer with years of

VHDL coding experience to hand code a fully

functional SDR waveform using our traditional

design flow. A second engineer with limited

experience completed the same project using

Simulink in fewer than 46 hours.”

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Elements of Software Defined Radio (SDR) & Design Workflow

RF

Transceiver

Baseband

Processing

Test and

Verification

MATLAB and Simulink

Baseband

Processing

Test and

Verification

MATLAB and Simulink

Test and

Verification

MATLAB and Simulink

ZC7035

System ModelingRadio I/O

PrototypingStandalone

Implementation ready

model

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Xilinx Zynq SoC-Based / FPGA Radio – Workflow

Model Based Design

WorkflowDevelop & Verify receiver algorithms and design

• Simulation Model

• Radio I/O

• Implementation

Ready Model

• Prototyping and

Standalone

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Development of a QPSK Transmitter and ReceiverValidate system models through simulation with relevant metrics

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Executable Specification of AD9361 receive path

https://www.mathworks.com/hardware-

support/analog-devices-rf-transceivers.html

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Xilinx Zynq SoC-Based / FPGA Radio – Workflow

Model Based Design

WorkflowTest design with realistic impairments

• Simulation Model

• Radio I/O

• Implementation

Ready Model

• Prototyping and

Standalone

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Streaming

to/from hostRF I/O

Analog

Front-End

Baseband Processing

on HostInformation

Sample Rate Conversion

on FPGA / SoC

Desktop Design and SimulationSDR FPGA Hardware

Capability 1: Radio I/O

Execute fixed radio functions on FPGA / SoC

Tunable pre-defined radio parameters

Easy out-of-the-box experience

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Radio I/OUse realworld data to develop system models

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Xilinx Zynq SoC-Based / FPGA Radio – Workflow

Model Based Design

WorkflowUse HDL supported blocks and data types

• Simulation Model

• Radio I/O

• Implementation

Ready Model

• Prototyping and

Standalone

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Development of a QPSK Transmitter and Receiver

1. Convert model to fixed-point data types

2. Elaborate design for efficient HW implementation

3. Generate and synthesize HDL code

4. Optimize HDL performance

5. Test and verify against floating-point model at every design stage

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Optimize HDL Performance

Speed optimization options

– Distribute pipeline registers to reduce critical path

– Insert pipeline registers at clock rate for multi-rate designs

– Automatically balance delays on parallel data paths

Area optimization options

– Share multipliers, adders and subsystems

– Partly and fully serial FIR, IIR filter architectures

– Map delays to RAM blocks

– CSD/FCSD multipliers (shifts and adds)

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Requirements

Automatically Generate Efficient HDL code

Full bi-directional

traceability!!

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FIL simulation with FPGA development board:– Reuse of existing ML/SL testbenches

– HDL code execution on FPGA

– Flexible HDL sources (handwritten or auto generated code)

– Automated generation of co-simulation infrastructure

(Ethernet, JTAG, PCIe)

Algorithmic System-level Testbench

Component

ModelAnalysis

Component

Model

Environment

Model

Data

Source

Alg

ori

thm

FIL

FPGA-in-the-Loop Verification of HDL Source Code

HDL Verifier

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Xilinx Zynq SoC-Based / FPGA Radio – Workflow

Model Based Design

WorkflowImplement final design on SoC / FPGA

• Simulation Model

• Radio I/O

• Implementation

Ready Model

• Prototyping and

Standalone

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Capability 2: SDR Target

Streaming

to/from hostRF I/O

Analog

Front-End

User-Designed

Host AlgorithmsInformation

User-Designed

FPGA / SoC Algorithms

Desktop Design and SimulationSDR FPGA/SoC Hardware

Generate code to implement user-defined algorithms on FPGA / SoC

Customized using HDL Coder

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Targetable Receiver/Transmitter Model

Run on Programmable Logic

Run on ARM Processing System

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HW/SW Co-Design QPSK Transmit and Receive Using

Analog Devices AD9361/AD9364

Easy testing of algorithms on

SoC / FPGA hardware

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Software Interface Model

Interact with SDR application

running real-time on target

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ChallengeAccelerate the development of optimized digital receiver chains for

wireless RF devices

SolutionUse MathWorks tools for Model-Based Design to generate

production VHDL code for rapid FPGA and ASIC implementation

Results Prototypes created 50% faster

Verification time reduced from weeks to days

Optimized, better-performing design delivered

“Writing VHDL is tedious, and the

handwritten code still needs to be

verified. With Simulink and HDL

Coder, once we have simulated the

model we can generate VHDL directly

and prototype an FPGA. It saves a lot

of time, and the generated code

contains some optimizations we

hadn’t thought of.”

Frantz Prianon

Semtech

The Semtech SX1231 wireless transceiver.

Semtech Speeds Development of Digital Receiver

FPGAs and ASICs

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FPGA-based PrototypingTime spent on FPGA/ASIC implementation

Shorter implementation time by 48% (total project 33%)

Reduced FPGA prototype development schedule by 47%

Shorter design iteration cycle by 80%1st FPGA Prototype 2nd FPGA Prototype

1st FPGA Prototype

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ChallengeDevelop a novel digital RF power subsystem for use in

MRI systems

SolutionUse Simulink to model, simulate, and verify the design,

and use HDL Coder to generate consistent and predictable

VHDL code for the FPGA implementation

Results Design issues resolved early in development

Tradeoffs rapidly assessed and implemented

Process consistency and predictability improved

Van Helvoort (left) and van Bakel with a

Philips Healthcare MRI scanner.

Philips Healthcare Develops Smart Digital RF

Power Subsystem for MRI Systems

“Simulink helps system architects

and hardware designers

communicate. It is like a shared

language that enables us to

exchange knowledge, ideas, and

designs. Simulink and HDL Coder

enable us to focus on developing

our algorithms and refining our

design via simulation, not on

checking VHDL syntax and coding

rules.”

Marcel van Bakel

Philips Healthcare

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More information

mathworks.com/sdr

White papers

Videos

Examples

Nokia already had an FPGA prototyping workflow based on hand writing HDL code, but increased their productivity and found better hardware architectures by moving to higher-level design and verification:» More details: Rapid Prototyping Using HDL Coder at Nokia

If you would like an overview of how to start prototyping radio signal processing algorithms on FPGA platforms:» More details: Getting Started with Software-Defined Radio using MATLAB and Simulink